| The Fabrics / I： |
| Introduction / 1： |
| A Historical Perspective |
| Issues in Digital Integrated Circuit Design |
| Quality Metrics of a Digital Design |
| The Manufacturing Process / 2： |
| The CMOS Manufacturing Process |
| Design Rules-The Contract between Designer and Process Engineer |
| Packaging Integrated Circuits |
| Perspective-Trends in Process Technology |
| The Devices / 3： |
| The Diode |
| The MOS(FET) Transistor |
| A Word on Process Variations |
| Perspective: Technology Scaling |
| The Wire / 4： |
| A First Glance |
| Interconnect Parameters-Capitance, Resistance, and Inductance |
| Electrical Wire Models |
| SPICE Wire Models |
| Perspective: A Look into the Future |
| A Circuit Perspective / II： |
| The CMOS Inverter / 5： |
| The Static CMOS Inverter-An Intuitive Perspective |
| Evaluating the Robustness of the CMOS Inverter: The Static Behavior |
| Performance of CMOS Inverter: The Dynamic Behavior |
| Power, Energy, and Energy-Delay |
| Perspective: Technology Scaling and Its Impact on the Inverter Metrics |
| Designing Combinational Logic Gates in CMOS / 6： |
| Static CMOS Design |
| Dynamic CMOS Design |
| How to Choose a Logic Style? Perspective: Gate Design in the Ultra Deep-Submicron Era |
| Designing Sequential Logic Circuits / 7： |
| Timing Metrics for Sequential Circuits |
| Classification of Memory Elements |
| Static Latches and Registers |
| Dynamic Latches and Registers |
| Pulse Registers |
| Sense-Amplifier Based Registers |
| Pipelining: An Approach to Optimize Sequential Circuits |
| Non-Bistable Sequential Circuits |
| Perspective: Choosing a Clocking Strategy |
| A System Perspective / III： |
| Implementation Strategies for Digital ICS / 8： |
| From Custom to Semicustom and Structured-Array Design Approaches |
| Custom Circuit Design |
| Cell-Based Design Methodology |
| Array-Based Implementation Approaches |
| Perspective-The Implementation Platform of the Future |
| Coping with Interconnect / 9： |
| Capacitive Parasitics |
| Resistive Parasitics |
| Inductive Parasitics |
| Advanced Interconnect Techniques |
| Perspective: Networks-on-a-Chip |
| Timing Issues in Digital Circuits / 10： |
| Timing Classification of Digital Systems |
| Synchronous Design-An In-Depth Perspective |
| Self-Timed Circuit Design |
| Synchronizers and Arbiters |
| Clock Synthesis and Synchronization Using a Phased-Locked Loop |
| Future Directions and Perspectives |
| Designing Arithmetic Building Blocks / 11： |
| Datapaths in Digital Processor Architectures |
| The Adder |
| The Multiplier |
| The Shifter |
| Other Arithmetic Operators |
| Power and Spped Trade-Offs in Datapath Structures |
| Perspective: Design as a Trade-off |
| Designing Memory and Array Structures / 12： |
| The Memory Core |
| Memory Peripheral Circuitry |
| Memory Reliability and Yield |
| Power Dissipation in Memories |
| Case Studies in Memory Design |
| Perspective: Semiconductor Memory Trends and Evolutions |
| Problem Solutions |
| Index |
| The Fabrics / I： |
| Introduction / 1： |
| A Historical Perspective |
| Issues in Digital Integrated Circuit Design |
| Quality Metrics of a Digital Design |
| The Manufacturing Process / 2： |
