| Preface |
| SOI Materials / Part I： |
| The SOI odyssey / P.L.F. Hemment |
| Thin film transfer by Smart Cut technology beyond SOI / C. Mazure |
| Quality improvement of SIMOX wafers by utilizing nitrogen-doped Cz Silicon crystal / K. Kawamura ; I. Hamaguchi ; T. Sasaki ; S. Takayama ; Y. Nagatake ; A. Matsumura |
| Ultrathin SOI wafer fabrication and metrology / C. Maleville |
| Replacing the BOX with buried alumina: improved thermal dissipation in SOI MOSFETs / K. Oshima ; S. Cristoloveanu ; B. Guillaumot ; G. Le Carval ; H. Iwai ; M.S. Kang ; Y.H. Bae ; J.W. Kwon ; S. Deleonibus ; J.H. Lee |
| Studies on novel SOI-structure with AIN film as buried insulator / C. Lin ; M. Zhu ; C. Men ; Z. An ; M. Zhang |
| Fabrication of sub-micron active layer SSOI substrates using ion splitting and wafer bonding technologies / F.H. Ruddell ; M.F. Bain ; S. Suder ; R.E. Hurley ; B.M. Armstrong ; V.F. Fusco ; H.S. Gamble |
| Back-end analysis of SOI substrates incorporating metallic layers using a novel non-destructive picosecond ultrasonic technique / N.D. McCusker ; P. McCann ; W.A. Nevin |
| Silicon-on-insulator-multilayer structure fabricated by epitaxial layer tranfer / W. Liu ; X. Xie ; Q. Lin ; Z. Zhang |
| Status of 300 mm SOI material: comparisons with 200 mm / H. Hovel ; M. Almonte ; P. Tsai ; J.D. Lee ; S. Maurer ; R. Kleinhenz ; D. Schepis ; R. Murphy ; P. Ronsheim ; A. Domenicucci ; J. Bettinger ; D. Sadana |
| A study on selective Si[subscript 0.8]Ge[subscript 0.2] etch using polysilicon etchant diluted by H[subscript 2]O for three-dimensional Si structure application / S.M. Kim ; C.W. Oh ; J.D. Choe ; C.S. Lee ; D.G. Park |
| Estimation of oxygen dose by spectroscopic ellipsometry and investigation of oxide formation mechanism by FT-IR for 160[superscript +]-implanted Si wafers / H. Iikawa ; M. Nakao ; K. Izumi |
| Development of SiC substrate with buried oxide layer for electron-photon merged devices / S. Hirai |
| Very low Schottky barrier to n-type silicon with PtEr-stack silicide / X. Tang ; J. Katcki ; E. Dubois ; J. Ratajczak ; G. Larrieu ; P. Loumaye ; O. Nisole ; V. Bayot |
| Defects and electrical consequences in SOI buried oxides / H.J. Hovel |
| Relaxed SiGe-on-insulator substrates through implanting oxygen into pseudomorphic SiGe/Si heterostructure / Y. Wu ; Z. Di ; P. Chu |
| Effect of silicon nitride and silicon dioxide bonding on the residual stress in layer-transferred SOI / A. Tiberj ; J. Camassel ; N. Planes ; Y. Stoemenos ; H. Moriceau ; O. Rayssac |
| Double-Gate and Various SOI Devices / Part II： |
| Fully depleted SOI process and device technology for digital and RF application / F. Ichikawa ; Y. Nagatomo ; Y. Katakura ; S. Itoh ; H. Matsuhashi ; N. Hirashita ; S. Baba |
| Emerging silicon-on-nothing (SON) devices technology / T. Skotnicki ; S. Monfray ; C. Fenouillet-Beranger |
| 60-nm gate length SOI CMOS technology optimised for "System-on-a-SOI-chip" solution / K. Imai ; S. Maruyama ; T. Suzuki ; T. Kudo ; S. Miyake ; M. Ikeda ; T. Abe ; S. Masuda ; A. Tanabe ; J-W. Lee ; K. Shibahara ; S. Yokoyama ; H. Ooka |
| High performance strained-SOI CMOSFETs / S-I. Takagi ; T. Mizuno ; T. Tezuka ; N Sugiyama ; T. Numata ; K. Usuda ; Y. Moriyama ; S. Nakaharai ; J. Koga ; T. Maeda |
| Real space transfer devices in SOI / S. Luryi |
| Issues in high performance FinFET and FDSOI transistor design / J. Kedzierski ; M. Ieong ; E. Nowak |
| Extremely scaled FinFETs and ultra-thin body SOI CMOS Devices / S. Balasubramanian ; L. Chang ; Y.-K. Choi ; D. Ha ; J. Lee ; P. Ranade ; S. Xiong ; J. Bokor ; C. Hu ; T.-J. King |
| Ultralow-power FD-SOI design for future mobile systems / T. Douseki ; H. Kyuragi |
| Status and development of future PD/SOI MOSFETs / S. Krishnan |
| Investigation of charge control related performances in double-gate SOI MOSFETs / V. Kilchytska ; T.M. Chung ; H. van Meer ; K. de Meyer ; J.P. Raskin ; D. Flandre |
| Substrate bias effects in SOI FinFETs / J. Pretet ; F. Dauge ; A. Vandooren ; L. Mathew ; B.-Y. Nguyen ; J. Jomaah |
| The nanoscale double-gate MOSFET for analog applications / D. Jimenez ; B. Iniguez ; J. Sune ; J.J. Saenz |
| The benefit of SOI technologies for low-voltage RFID applications / P. Villard ; B. Gomez ; J. De Pontcharra ; D. Save ; S. Chouteau ; E. Mackowiak |
| A novel CMOS memory cell architecture for ultra-low power applications operating up to 280[degree]C / D. Levacq ; V. Dessard |
| Multi-fin double-gate MOSFET fabricated by using (110)-oriented SOI wafers and orientation-dependent etching / Y. Liu ; K. Ishii ; T. Tsutsumi ; M. Masahara ; H. Takashima ; E. Suzuki |
| Impact of the graded-channel architecture on double gate transistors for high-performance analog applications / M.A. Pavanello ; J.A. Martino ; A. Kranti ; J.-P. Raskin |
| Characteristics of two types of MEMS resonator structures in SOI applications / S. Myllymaki ; E. Ristolainen ; P. Heino ; A. Lehto ; K. Varjonen |
| High-voltage super-junction SOI-LDMOSFETs with reduced drift length / J.M. Park ; T. Grasser ; S. Selberherr |
| Comparative study of the dynamic performance of bulk and FDSOI MOSFET by means of a Monte Carlo simulation / R. Rengel ; D. Pardo ; M.J. Martin |
| Partially depleted SOI dynamic-threshold MOSFET for low-voltage and microwave applications / M. Dehan ; D. Vanhoenacker |
| Figures-of-merit of intrinsic, standard-doped and graded-channel SOI and SOS MOSFETs for analog baseband and RF applications |
| Comparison of SOI, poly-Si TFT and bulk Si MOS performance using gm/ID methodology / K. Takatori |
| Optimization of ultra-thin body, fully-depleted SOI device, with raised source/drain / J. Egley ; B. Winstead ; E. Verret ; B. White |
| Device Physics and Modeling / Part III： |
| Device models for silicon-on-insulator (SOI) insulated-gate PN-junction devices for electrostatic discharge (ESD) protection circuit design / Y. Omura ; S. Wakita |
| Evidence for a "linear kink effect" in ultra-thin gate oxide SOI MOSFETs / A. Mercha ; E. Simoen ; J.-M. Rafi ; C. Claeys ; N. Lukyanchikova ; M. Petrichuk ; N. Garbar |
| An accurate model for threshold voltage and S-factor of partially-depleted surrounding gate transistor (PD-SGT) / Y. Yamamoto ; M. Hioki ; R. Nishi ; H. Sakuraba ; F. Masuoka |
| Reduction of pass-gate leakage by silicon-thickness thinning in double-gate MOSFETs / W. Sakamoto ; T. Endoh |
| Accurate and efficient method for accelerated history effect simulations / T. Poiroux ; G. Labourey ; P. Flatresse ; O. Faynot ; M. Belleville ; D. Souil ; B. Giffard |
| Electron mobility in strained-Si inversion layers grown on SiGe-on-insulator substrates / F. Gamiz ; J.B. Roldan ; A. Godoy ; P. Cartujo-Cassinello ; F. Jimenez-Molinos |
| Strained Si/SiGe channels: a new performance advantage for PD/SOI CMOS / W. Zhang ; J.G. Fossum |
| Modeling of Coulomb scattering of electrons in ultrathin symmetrical DG SOI transistor / J. Walczak ; B. Majkusiak |
| Comparison of partially and fully depleted SOI transistors down to the sub 50-nm-gate length regime / L. Dreeskornfeld ; J. Hartwich ; E. Landgraf ; R.J. Luyken ; W. Rosner ; T. Schulz ; M. Stadele ; D. Schmitt-Landsiedel ; L. Risch |
| Saturation current model for the n-channel G[superscript 4]-FET / B. Dufrene ; B. Blalock ; M. Mojarradi ; E. Kolawa |
| Quasi-three-dimensional device simulation of fully depleted MOSFET/SOI focused on surface roughness |
| Threshold voltage quantum simulations for ultra-thin silicon-on-insulator transistors / J. Lolivier ; F. Balestra |
| Impact of quantum-mechanical effects on the double-gate MOSFET characteristics / G. Ghibaudo |
| Analysis of HALO implant influence on the self-heating and self-heating enhanced impact ionization on 0.13 [mu]m floating-body partially-depleted SOI MOSFET at low temperature / K. De Meyer |
| SOI thermal resistance and its application to thermal modeling of SOI MOSFETs / M.-C. Cheng ; F. Yu |
| Fully-quantum theory of SOI MOSFETs / T.J. Walls ; V.A. Sverdlov ; K.K. Likharev |
| Oxidation simulation of silicon nanostructure on silicon-on-insulator substrates / M. Uematsu ; H. Kageshiwa ; K. Shiraishi |
| Characterisation and Reliability Issues / Part IV： |
| Characterization of SOI wafers by photoluminescence spectroscopy, decay and micro/macro-mapping / M. Tajima |
| Feasibility of surface photovoltage based characterization of ultra-thin SOI wafers / L. Lukasiak ; E. Kamieniecki ; A. Jakubowski ; J. Ruzyllo |
| Analysis of soft errors in floating channel type surrounding gate transistor (FC-SGT) DRAM cells / F. Matsuoka |
| Radiation damage in deep submicron partially depleted SOI CMOS / J.M. Rafi ; X. Serra-Gallifa ; M. Kokkoris ; E. Kossionides ; G. Fanourakis |
| Study of the leakage drain current in graded-channel SOI nMOSFETs at high-temperatures / M. Bellodi |
| Radiation response of SOI CMOS transistors/4M SRAMs fabricated in UNIBOND substrates / S.T. Liu ; W. Heikkila ; K. Golke ; B. Stinger ; M. Flanery ; A. Hurst ; G. Panning ; G. Kirchner ; W.C. Jenkins |
| Nature of high-temperature charge instability of fully depleted SOI MOSFETs / A.N. Nazarov ; V.S. Lysenko ; J.P. Colinge |
| Control of SEU in SOI SRAMs through carrier lifetime engineering / S. Mitra ; D.P. Ioannou ; D.E. Ioannou |
| Evaluation of commercial ultra-thin SOI substrates using confocal laser inspection system / A. Ogura ; O. Okabayashi |
| Extraction of high frequency noise parameters of 0.25 [mu]m partially depleted silicon-on-insulator MOSFET: impact of the high resistivity substrate / R. Daviot ; O. Rozeau ; N. Abouchi ; A. Grouillet ; L. Tosti |
| Temperature and magnetic field dependence of the carrier mobility in SOI wafers by the pseudo-MOSFET method / C. Rossel ; D. Halley |
| Carrier lifetimes in SOI material |
| Total dose radiation hardness of double-gate ultra-thin SOI MOSFETs / C.R. Cirba ; R.D. Schrimpf ; L.C. Feldman ; D.M. Fleetwood ; K.F. Galloway |
| Steady-state characterization of partially depleted SOI CMOS gates / A. Bracale ; E. Dupont-Nivet ; J.-L. Pelloie |
| Changes in the parameters of silicon-on-insulator structures under irradiation / I.V. Antonova ; D.V. Nikolaev ; O.V. Naumova ; S.A. Smagulova ; V.P. Popov |
| Spectroscopic ellipsometry characterization of the interfacial roughness in SIMOX wafer / W.J. Li ; Z.R. Song ; K. Tao ; Y.H. Yu ; X. Wang ; S.C. Zou |
| Subject Index |
| Author Index |
| Preface |
| SOI Materials / Part I： |
| The SOI odyssey / P.L.F. Hemment |
| Thin film transfer by Smart Cut technology beyond SOI / C. Mazure |
| Quality improvement of SIMOX wafers by utilizing nitrogen-doped Cz Silicon crystal / K. Kawamura ; I. Hamaguchi ; T. Sasaki ; S. Takayama ; Y. Nagatake ; A. Matsumura |
| Ultrathin SOI wafer fabrication and metrology / C. Maleville |
