Guest Editorial / L. Chua ; E. Pierzchala ; G. Gulak ; A. Rodriguez-Vazquez |
A 16 x 16 Cellular Neural Network Universal Chip: The First Complete Single-Chip Dynamic Computer Array with Distributed Memory and with Gray-Scale Input-Output / J. M. Cruz ; L. O. Chua |
A 6 x 6 Cells Interconnection-Oriented Programmable Chip for CNN / M. Salerno ; F. Sargeni ; Vincenzo Bonaiuto |
Analog VLSI Design Constraints of Programmable Cellular Neural Networks / P. Kinget ; M. Steyaert |
Focal-Plane and Multiple Chip VLSI Approaches to CNNs / M. Anguita ; F. J. Pelayo ; E. Ros ; D. Palomar ; A. Prieto |
Architecture and Design of 1-D Enhanced Cellular Neural Network Processors for Signal Detection / M. Y. Wang ; B. J. Sheu ; T. W. Berger ; W. C. Young ; A. K. Cho |
Analog VLSI Circuits for Competitive Learning Networks / H. C. Card ; D. K. McNeill ; C. R. Schneider |
Design of Neural Networks Based on Wave-Parallel Computing Technique / Y. Yuminaka ; Y. Sasaki ; T. Aoki ; T. Higuchi |
Guest Editorial / L. Chua ; E. Pierzchala ; G. Gulak ; A. Rodriguez-Vazquez |
A 16 x 16 Cellular Neural Network Universal Chip: The First Complete Single-Chip Dynamic Computer Array with Distributed Memory and with Gray-Scale Input-Output / J. M. Cruz ; L. O. Chua |
A 6 x 6 Cells Interconnection-Oriented Programmable Chip for CNN / M. Salerno ; F. Sargeni ; Vincenzo Bonaiuto |
Analog VLSI Design Constraints of Programmable Cellular Neural Networks / P. Kinget ; M. Steyaert |
Focal-Plane and Multiple Chip VLSI Approaches to CNNs / M. Anguita ; F. J. Pelayo ; E. Ros ; D. Palomar ; A. Prieto |
Architecture and Design of 1-D Enhanced Cellular Neural Network Processors for Signal Detection / M. Y. Wang ; B. J. Sheu ; T. W. Berger ; W. C. Young ; A. K. Cho |