| Signal Processing |
| Reconfigurable Processors for High-Performance, Embedded Digital Signal Processing / P. Graham ; B. Nelson |
| Auditory Signal Processing in Hardware: A Linear Gammatone Filterbank Design for a Model of the Auditory System / M. Brucke ; A. Schulz ; W. Nebel |
| SONIC - A Plug-In Architecture for Video Processing / S. D. Haynes ; P. Y. K.Cheung ; W. Luk ; J. Stone |
| CAD Tools for DRL |
| DRIVE: An Interpretive Simulation and Visualization Environment for Dynamically Reconfigurable Systems / K. Bondalapati ; V. K. Prasanna |
| Modelling and Synthesis of Configuration Controllers for Dynamically Reconfigurable Logic Systems Using the DCS CAD Framework / D. Robinson ; P. Lysaght |
| Optimization Studies |
| Optimal Finite Field Multipliers for FPGAs / G. C. Ahlquist ; M. Rice |
| Memory Access Optimization and RAM Inference for Pipeline Vectorization / M. Weinhardt |
| Analysis and Optimization of 3-D FPGA Design Parameters / S. M. S. A. Chiricescu ; M. M. Vai |
| Physical Design |
| Tabu Search: Ultra-Fast Placement for FPGAs / J. M. Emmert ; D. K. Bhatia |
| Placement Optimization Based on Global Routing Updating for System Partitioning onto Multi-FPGA Mesh Topologies / J. de Vicente ; J. Lanchares ; R. Hermida |
| Hierarchical Interactive Approach to Partition Large Designs into FPGAs / H. Krupnova ; G. Saucier |
| Logical-to-Physical Memory Mapping for FPGAs with Dual-Port Embedded Arrays / W. K. C. Ho ; S. J. E. Wilton |
| Dynamically Reconfigurable Logic |
| DYNASTY: A Temporal Floorplanning Based CAD Framework for Dynamically Reconfigurable Logic Systems / M. Vasilko |
| A Bipartitioning Algorithm for Dynamic Reconfigurable Programmable Logic / E. Cantó ; J. M. Moreno ; J. Cabestany ; J. Faura ; J. M. Insenser |
| Self Controlling Dynamic Reconfiguration: A Case Study / G. McGregor |
| Design Tools |
| An Internet Based Development Framework for Reconfigurable Computing / R. W. Hartenstein ; M. Herz ; U. Nageldinger ; T. Hoffmann |
| On Tool Integration in High-Performance FPGA Design Flows / A. Koch |
| Hardware-Software Codesign for Dynamically Reconfigurable Architectures / K. S. Chatha ; R. Vemuri |
| Reconfigurable Computing |
| Serial Hardware Libraries for Reconfigurable Designs / A. Derbyshire ; S. Guo ; D. Siganos |
| Reconfigurable Computing in Remote and Harsh Environments / G. Brebner ; N. Bergmann |
| Communication Synthesis for Reconfigurable Embedded Systems / M. Eisenring ; M. Platzner ; L. Thiele |
| Run-Time Parameterizable Cores / S. A. Guccione ; D. Levi |
| Applications |
| Rendering PostScriptÖ Fonts on FPGAs / D. MacVicar ; J. W. Patterson ; S. Singh |
| Implementing PhotoshopÖ Filters in VirtexÖ / S. Ludwig ; R. Slous |
| Rapid FPGA Prototyping of a DAB Test Data Generator Using Protocol Compiler / K. Feske ; M. Scholz ; G. Döring ; D. Nareike |
| Quantitative Analysis of Run-Time Reconfigurable Database Search / N. Shirazi ; D. Benyamin ; P. Y. K. Cheung |
| Novel Architectures |
| An On-Line Arithmetic Based FPGA for Low-Power Custom Computing / A. Tisserand ; P. Marchal ; C. Piguet |
| A New Switch Block for Segmented FPGAs / M. I. Masud |
| PulseDSP - A Signal Processing Oriented Programmable Architecture / G. Jones |
| Machine Applications |
| FPGA Viruses / I. Had&zbreve;ić ; S. Udani ; J. M. Smith |
| Genetic Programming Using Self-Reconfigurable FPGAs / R. P. S. Sidhu ; A. Mei |
| Specification, Implementation and Testing of HFSMs in Dynamically Reconfigurable FPGAs / A. Oliveira ; A. Melo ; V. Sklyarov |
| Synthia : Synthesis of Interacting Automata Targeting LUT-based FPGAs / G. A. Constantinides |
| Short Papers |
| An FPGA-based Prototyping System for Real-Time Verification of Video Processing Schemes / H. Kropp ; C. Reuter ; M. Wiege ; T.-T. Do ; P. Pirsch |
| An FPGA Implementation of Goertzel Algorithm / T. Dulik |
| Pipelined Multipliers and FPGA Architectures / M. Wojko |
| FPGA Design Trade-Offs for Solving the Key Equation in Reed-Solomon Decoding / E. M. Popovici ; P. Fitzpatrick ; C. C. Murphy |
| Reconfigurable Multiplier for Virtex FPGA Family / J. Põldre ; K. Tammemäe |
| Pipelined Floating Point Arithmetic Optimized for FPGA Architectures / I. Stamoulis ; M. White ; P. F. Lister |
| SL - A Structural Hardware Design Language / S. Holmström |
| High-Level Hierarchical HDL Synthesis of Pipelined FPGA-Based Circuits Using Synchronous Modules / R. B. Maunder ; Z. A. Salcic ; G. G. Coghill |
| Mapping Applications onto Reconfigurable KressArrays / R. Hartenstein |
| Global Routing Models / M. Dan&ebreve;k ; Z. Muziká&rbreve; |
| Power Modelling in Field Programmable Gate Arrays (FPGA) / A. Garcia ; W. Burleson ; J.-L. Danger |
| NEBULA: A Partially and Dynamically Reconfigurable Architecture / D. Bhatia ; K. S. Simha ; P. Kannan |
| High Bandwidth Dynamically Reconfigurable Architectures Using Optical Interconnects / K. J. Symington ; J. F. Snowdon ; H. Schroeder |
| AHA-GRAPE: Adaptive Hydrodynamic Architecture - GRAvity PipE / T. Kuberka ; A. Kugel ; R. Mäanner ; H. Singpiel ; R. Spurzem ; R. Klessen |
| DIME - The First Module Standard for FPGA Based High Performance Computing / M. Devlin ; A.J.Cantle |
| The Proteus Processor - A Conventional CPU with Reconfigurable Functionality / M. Dales |
| Logic Circuit Speeding up through Multiplexing / V. F. Tomashau |
| A Wildcarding Mechanism for Acceleration of Partial Configurations / P. James-Roxby ; E. Cerro-Prada |
| Hardware Implementation Techniques for Recursive Calls and Loops / T. Maruyama ; M. Takagi ; T. Hoshino |
| A HW/SW Codesign-Based Reconfigurable Environment for Telecommunication Network Simulation / J. Noguera ; R. M. Badia ; J. Domingo ; J. Solé-Pareta |
| An Alternative Solution for Reconfigurable Coprocessors Hardware and Interface Synthesis / M. D. Valdés ; M. J. Moure ; E. Mandado ; A. Salaverría |
| Reconfigurable Programming in the Large on Extendable Uniform Reconfigurable Computing Array's: An Integrated Approach Based on Reconfigurable Virtual Architectures / A. Touhafi ; W. Brissinck ; E. F. Dirkx |
| A Concept for an Evaluation Framework for Reconfigurable Systems / S. Sawitzki ; R. G. Spallek |
| Debugging Application-Specific Programmable Products / R. Kress ; A. Pyttel |
| IP Validation for FPGAs Using Hardware Object TechnologyÖ / S. Casselman ; J. Schewel ; C. Beaumont |
| A Processor for Artificial Life Simulation / M. Böge |
| A Distributed, Scalable, Multi-Layered Approach to Evolvable System Design Using FPGA's / C. Slorach ; S. Fulton ; K. Sharman |
| Dynamically Reconfigurable Reduced Crossbar: A Novel Approach to Large Scale Switching / T. Caohuu ; T. Trong Le ; M. Glesner ; J. Becker |
| A Reconfigurable Architecture for High Speed Computation by Pipeline Processing |
| Seeking (the right) Problems for the Solutions of Reconfigurable Computing / B. Kastrup ; J. van Meerbergen ; K. Nowak |
| A Runtime Reconfigurable Implementation of the GSAT algorithm / H. Y. Wong ; W. S. Yuen ; K. H. Lee ; P. H. W. Leong |
| Accelerating Boolean Implications with FPGAs / K. Sulimma ; D. Stoffel ; W. Kunz |
| Author Index |
| Signal Processing |
| Reconfigurable Processors for High-Performance, Embedded Digital Signal Processing / P. Graham ; B. Nelson |
| Auditory Signal Processing in Hardware: A Linear Gammatone Filterbank Design for a Model of the Auditory System / M. Brucke ; A. Schulz ; W. Nebel |
| SONIC - A Plug-In Architecture for Video Processing / S. D. Haynes ; P. Y. K.Cheung ; W. Luk ; J. Stone |
| CAD Tools for DRL |
| DRIVE: An Interpretive Simulation and Visualization Environment for Dynamically Reconfigurable Systems / K. Bondalapati ; V. K. Prasanna |
