| Foreword |
| Organizing Committee |
| Technical Program Committee |
| Reviewers |
| System Design: Traditional Concepts and New Paradigms / A. Ferrari ; A. Sangiovanni-Vincentelli |
| The Marco/Darpa Gigascale Silicon Research Center / Kurt Keutzer ; A. Richard Newton |
| Embedded Tutorial |
| CAD Techniques for Embedded Systems-on-Silicon |
| Applied Verification Techniques |
| Verification of Real Time Controllers against Timing Diagram Specifications Using Constraint Logic Programming / E. Cerny ; F. Jin |
| Formal Verification of Synthesized Analog Designs / A. Ghosh ; R. Vemuri |
| Implicit Verification of Structurally Dissimilar Arithmetic Circuits / T. Stanion |
| Automatic Error Correction of Tri-State Circuits / D. Hoffmann ; T. Kropf |
| Computer Arithmetic |
| Design Methodology for a One-Shot Reed-Solomon Encoder and Decoder / S. Morioka ; Y. Katayama |
| High-Speed CORDIC Architecture Based on Redundant Sum Formation and Overlapped [sigma]-Selection / J. Choi ; J.-H. Kwak ; E. Swartzlander, Jr. |
| Multilevel Reverse-Carry Computation for Comparison and for Sign and Overflow Detection in Addition / T. Lang ; J. Bruguera |
| A Unified Method for Iterative Computation of Modular Multiplication and Reduction Operations / W. Freking ; K. Parhi |
| Evolution of DSP Architecture |
| Machines and Characterization |
| Designing the M - CORE M3 CPU Architecture / J. Scott ; L. Lee ; A. Chin ; J. Arends ; B. Moyer |
| Performance Evaluation of Configurable Hardware Features on the AMD-K5 / M. Clark ; L. John |
| Detailed Characterization of a Quad Pentium Pro Server Running TPC-D / Q. Cao ; P. Trancoso ; J.-L. Larriba-Pey ; J. Torrellas ; R. Knighten ; Y. Won |
| Power and Noise Considerations in Microprocessor Design |
| Simultaneous Switching Noise Considerations in the Design of a High Speed, Multiported TLB of a Server-Class Microprocessor / N. Kalyanasundharam ; N. Patwa |
| On the Use of Pseudorandom Sequences for High Speed Resource Allocators in Superscalar Processors / S. Srinivasan |
| Power Estimation of System-Level Buses for Microprocessor-Based Architectures: A Case Study / W. Fornaciari ; D. Sciuto ; C. Silvano |
| Architectures for Embedded Systems |
| A DSP with Caches -- A Study of the GSM-EFR Codec on the TI C6211 / T. Jeremiassen |
| Evaluation of Computing in Memory Architectures for Digital Image Processing Applications / D. Landis ; P. Hulina ; S. Deno ; L. Roth ; L. Coraor |
| Customization of a CISC Processor Core for Low-Power Applications / Y.-S. Chang ; B.-I. Park ; I.-C. Park ; C.-M. Kyung |
| Built-In Self Test |
| A New Weight Set Generation Algorithm for Weighted Random Pattern Generation / H. Lee ; S. Kang |
| Multiple Paths Sensitization of Digital Oscillation Built-In Self Test / C. Dufaza |
| Design and Implementation of a Parallel Weighted Random Pattern and Logic Built in Self Test Algorithm / P. Chang ; B. Keller ; S. Paliwal |
| Intelligent Memory |
| Design and Evaluation of a Selective Compressed Memory System / J.-S. Lee ; W.-K. Hong ; S.-D. Kim |
| FlexRAM: Toward an Advanced Intelligent Memory System / Y. Kang ; W. Huang ; S.-M. Yoo ; D. Keen ; Z. Ge ; V. Lam ; P. Pattnaik |
| ActiveOS: Virtualizing Intelligent Memory / M. Oskin ; F. Chong ; T. Sherwood |
| Performance and Area Optimization |
| An Efficient Buffer Insertion Algorithm for Large Networks Based on Lagrangian Relaxation / I.-M. Liu ; A. Aziz ; D. Wong ; H. Zhou |
| An Exact Tree-Based Structural Technology Mapping Algorithm for Configurable Logic Blocks in FPGAs / K. Lee |
| An Effective Algorithm for Gate-Level Power-Delay Tradeoff Using Two Voltages / C. Chen ; M. Sarrafzadeh |
| VLSI Implementation of Arithmetic Circuits |
| Switching Characteristics of Generalized Array Multiplier Architectures and Their Applications to Low Power Design / K. Muhammad ; D. Somasekhar ; K. Roy |
| Low-Power Radix-4 Combined Division and Square Root / A. Nannarelli |
| A Regular Layout Structured Multiplier Based on Weighted Carry-Save Adders |
| Design Convergence |
| A Robust Solution to the Timing Convergence Problem in High-Performance Design / N. Shenoy ; M. Iyer ; R. Damiano ; P. Thilking ; K. Harer ; H.-K. Ma |
| Performance Driven Optimization of Network Length in Physical Placement / W. Donath ; P. Kudva ; L. Reddy |
| Efficient Crosstalk Estimation / M. Kuhlmann ; S. Sapatnekar |
| Poster Presentations |
| A High-Performance Hardware-Efficient Memory Allocation Technique and Design / H. Cam ; M. Abd-El-Barr ; S. Sait |
| Improving Microcontroller Power Consumption through a Segmented Gray Code Program Counter / R. Hakenes ; Y. Manoli |
| A Superscalar RISC Processor with 160 FPRs for Large Scale Scientific Processing / K. Shimada ; T. Kawashimo ; M. Hanawa ; R. Yamagata ; E. Kamada |
| Characterization of Java Applications at Bytecode and Ultra-SPARC Machine Code Levels / R. Radhakrishnan ; J. Rubio |
| Automatic Generation of Tree Multipliers Using Placement-Driven Netlists / A. Gautam ; V. Visvanathan ; S. Nandy |
| Yield Optimization by Design Centering and Worst-Case Distance Analysis / G. Samudra ; H. Chen ; D. Chan ; Y. Ibrahim |
| Area, Performance, and Yield Implications of Redundancy in On-Chip Caches / T. Thomas ; B. Anthony |
| Conceptual Modeling and Simulation / W. Cyre |
| System-on-a-Chip Bus Architecture for Embedded Applications / P. Aldworth |
| CalmRISC: A Low Power Microcontroller with Efficient Coprocessor Interface / K.-M. Lim ; S.-W. Jeong ; Y.-C. Kim ; S.-J. Jeong ; H.-K. Kim ; Y.-H. Kim ; B.-Y. Chung ; H.-L. Roh ; H. Yang |
| An Even Wiring Approach to the Ball Grid Array Package Routing / S.-S. Chen ; J.-J. Chen ; C.-C. Tsai ; S.-J. Chen |
| Synthesis of Pseudo Kronecker Lattice Diagrams / P. Lindgren ; R. Drechsler ; B. Becker |
| Generic Universal Switch Blocks / M. Shyu ; Y.-D. Chang ; G.-M. Wu ; Y.-W. Chang |
| Multi-Level Logic Minimization through Fault Dictionary Analysis / R. Mehler ; M. Mercer |
| A Fast and Exact Cell Matching Method for MUX-Based FPGA Technology Mapping / K. Yi ; S. Ohm |
| Novel Formulations for Low-Power Binding of Function Units in High-Level Synthesis / A. Kumar ; M. Bayoumi |
| An Efficient Functional Coverage Test for HDL Descriptions at RTL / C.-N. Liu ; J.-Y. Jou |
| An Efficient Interconnect Test Using BIST Module in a Boundary-Scan Environment / H.-J. Kim ; J. Shin |
| On-Line BIST for Testing Analog Circuits / J. Velasco-Medina ; I. Rayane ; M. Nicolaidis |
| Iteration-Free Timing Closure |
| MicroProcessor Architecture; Trends and Directions / Uri Weiser |
| System Level Issues |
| A Design Methodology for a Fully Synthesized High Speed DSP Core in a Deep Sub-Micron Technology / J. Rao ; K. Madathil ; V. Shah ; H. Udayakumar ; A. Menon ; S. Chandar |
| An Environment for Exploring Low Power Memory Configurations in System Level Design / S. Coumeri ; D. Thomas |
| Architectural Synthesis of Timed Asynchronous Systems / B. Bachman ; H. Zheng ; C. Myers |
| Computing Minimum Feedback Vertex Sets by Contraction Operations and Its Applications on CAD / H.-M. Lin |
| Compilers and Algorithms |
| A Compiler-Assisted Data Prefetch Controller / S. Vander Wiel ; D. Lilja |
| Energy and Performance Improvements in Microprocessor Design Using a Loop Cache / N. Bellas ; I. Hajj ; C. Polychronopoulos ; G. Stamoulis |
| A Fast Median Filter Using AltiVec / P. Kolte ; R. Smith ; W. Su |
| Approximating Hexagonal Steiner Minimal Trees by Fast Optimal Layout of Minimum Spanning Trees / G.-H. Lin ; G. Xue ; D. Zhou |
| Test Generation and Delay Testing |
| On Detecting Bridges Causing Timing Failures / S. Mandava ; S. Chakravarty ; S. Kundu |
| Design for Testability to Combat Delay Faults / J. Savir |
| Fault Simulation Based Test Generation for Combinational Circuits Using Dynamically Selected Subcircuits / I. Pomeranz ; S. Reddy |
| Using an Embedded Processor for Efficient Deterministic Testing of Systems-on-a-Chip / A. Jas ; N. Touba |
| Microarchitecture |
| Architecture of the Atlas Chip-Multiprocessor: Dynamically Parallelizing Irregular Applications / L. Codrescu ; D. Wills |
| Load-Balancing Branch Target Cache and Prefetch Buffer / C.-H. Chi ; J.-L. Yuan |
| Dynamic Branch Decoupled Architecture / A. Tyagi ; H.-C. Ng ; P. Mohapatra |
| Efficient State-Space Exploration |
| Improving Witness Search Using Orders on States / R. Sumners ; J. Bhadra ; J. Abraham |
| Verification of Scheduling in the Presence of Loops Using Uninterpreted Symbolic Simulation / P. Ashar ; A. Raghunathan ; A. Gupta ; S. Bhattacharya |
| Efficient Fixpoint Computation for Invariant Checking / K. Ravi ; F. Somenzi |
| Clocking and Analog Circuit Prototyping |
| A Low-Power Microcontroller with On-Chip Self-Tuning Digital Clock-Generator for Variable-Load Applications / M. Olivieri ; A. Trifiletti ; A. De Gloria |
| A Methodology for Rapid Prototyping of Analog Systems / S. Ganesan |
| Transmission Line Clock Driver / M. Becker ; T. Knight, Jr. |
| Benchmarking, Selection and Debugging of Microcontrollers |
| Digital Signal Processors |
| The Specialization of General Purpose Processor Architecture Elements for Programmable Digital Signal Processors / D. Steiss |
| DSP for the Third Generation Wireless Communications / U. Ko ; M. McMahan ; E. Auslander |
| Performance and Reliability Verification of C6201/C6701 Digital Signal Processors / N. NS ; F. Cano ; S. Thiruvengadam ; D. Kapoor |
| Caching Approaches |
| Pursuing the Performance Potential of Dynamic Cache Line Sizes / P. van Vleet ; E. Anderson ; L. Brown ; J.-L. Baer ; A. Karlin |
| The Non-Critical Buffer: Using Load Latency Tolerance to Improve Data Cache Efficiency / B. Fisk ; R. Bahar |
| Cache Optimization for Memory-Resident Decision Support Commercial Workloads |
| CMOS Circuit Design Techniques |
| An Investigation of Power Delay Trade-Offs for Dual V[subscript t] CMOS Circuits / Q. Wang ; S. Vrudhula |
| Delay Optimization of CMOS Logic Circuits Using Closed-Form Expressions / M. Shams ; M. Elmasry |
| Design and Synthesis of Monotonic Circuits / T. Thorp ; G. Yee ; C. Sechen |
| SOI Implementation of a 64-Bit Adder / J. Tran ; F. Mounes-Toussi ; S. Storino ; D. Stasiak |
| Forty Five Years of Computer Architecture -- All That's Old is New Again / Harvey G. Cragon |
| The TriMedia CPU64 VLIW Media Processor |
| TriMedia CPU64 Application Domain and Benchmark Suite / A. Riemens ; K. Vissers ; R. Schutten ; F. Sijstermans ; G. Hekstra ; G. La Hei |
| TriMedia CPU64 Architecture / J. van Eijndhoven ; E. Pol ; M. Tromp ; P. Struik ; R. Bloks ; P. van der Wolf ; A. Pimentel ; H. Vranken |
| TriMedia CPU64 Application Development Environment / B. Aarts ; J. van de Waerdt |
| TriMedia CPU64 Design Space Exploration / P. Bingley |
| Logic Synthesis |
| On State Assignment of Finite State Machines Using Hypercube Embedding Approach / I. Ahmad ; R. Ul-Mustafa |
| Synthesis of Arrays and Records / P. Jha ; S. Barnfield ; J. Weaver ; R. Mukherjee ; R. Bergamaschi |
| Decomposition of Finite State Machines for Area, Delay Minimization / R. Shelar ; M. Desai ; H. Narayanan |
| BDD Decomposition for Efficient Logic Synthesis / C. Yang ; V. Singhal ; M. Ciesielski |
| Hardware Software Partitioning and Synthesis |
| Software Synthesis for Complex Reactive Embedded Systems / F. Balarin ; M. Chiodo |
| Hardware/Software Partitioning of Multirate System Using Static Scheduling Theory / R. Kamdem ; A. Fonkoua ; A. Zenatti |
| Compositional Software Synthesis of Communicating Processes / X. Zhu ; B. Lin |
| Preference-Driven Hierarchical Hardware/Software Partitioning / G. Quan ; X. Hu ; G. Greenwood |
| Author Index |
| Foreword |
| Organizing Committee |
| Technical Program Committee |
| Reviewers |
| System Design: Traditional Concepts and New Paradigms / A. Ferrari ; A. Sangiovanni-Vincentelli |
| The Marco/Darpa Gigascale Silicon Research Center / Kurt Keutzer ; A. Richard Newton |
