| Foreword |
| Committees |
| Reviewers |
| Welcome and Keynote / Uri WeiserSession 1： |
| New Microarchitecture Challenges in the Coming Generations of CMOS Process Technologies / F. Pollack |
| Faster FrontEnd / Gary TysonSession 2： |
| Control Independence in Trace Processors / E. Rotenberg ; J. Smith |
| Fetch Directed Instruction Prefetching / G. Reinman ; B. Calder ; T. Austin |
| Improving Branch Predictors by Correlating on Data Values / T. Heil ; Z. Smith |
| Instruction Fetch Mechanisms for Multipath Execution Processors / A. Klauser ; D. Grunwald |
| 3D and MultiMedia / Matthew FarrensSession 3： |
| A Superscalar 3D Graphics Engine / A. Wolfe ; D. Noonburg |
| Dynamic 3D Graphics Workload Characterization and the Architectural Implications / T. Mitra ; T. Chiueh |
| Exploiting a New Level of DLP in Multimedia Applications / J. Corbal ; R. Espasa ; M. Valero |
| Efficient Embedded Processors / Kemal EbciogluSession 4： |
| Compiler-Driven Cached Code Compression Schemes for Embedded ILP Processors / S. Larin ; T. Conte |
| Evaluation of a High Performance Code Compression Method / C. Lefurgy ; E. Piccininni ; T. Mudge |
| Low-Cost Branch Folding for Embedded Applications with Small Tight Loops / L. Lee ; J. Scott ; B. Moyer ; J. Arends |
| Memory Hierarchy / Doug BurgerSession 5： |
| Automatic and Efficient Evaluation of Memory Hierarchies for Embedded Systems / S. Abraham ; S. Mahlke |
| Hardware Identification of Cache Conflict Misses / J. Collins ; D. Tullsen |
| Access Region Locality for High-Bandwidth Processor Memory System Design / S. Cho ; P. Yew ; G. Lee |
| Code Transformations to Improve Memory Parallelism / V. Pai ; S. Adve |
| Better Scheduling / Stephan JourdanSession 6： |
| Compiler-Directed Dynamic Computation Reuse: Rationale and Initial Results / D. Connors ; W. Hwu |
| Dynamic Memory Disambiguation in the Presence of Out-of-Order Store Issuing / S. Onder ; R. Gupta |
| Read-After-Read Memory Dependence Prediction / A. Moshovos ; G. Sohi |
| Delaying Physical Register Allocation through Virtual-Physical Registers / T. Monreal ; A. Gonzalez ; J. Gonzalez ; V. Vinals |
| Invited Speaker / Gabby SilbermanSession 7： |
| Core Technologies in Hardware and Software / B. Shriver |
| Novel Microarchitectures and Multithreading / Brad CalderSession 8： |
| DIVA: A Reliable Substrate for Deep Submicron Microarchitecture Design |
| Exploiting ILP in Page-based Intelligent Memory / M. Oskin ; J. Hensley ; D. Keen ; F. Chong ; M. Farrens ; A. Chopra |
| The Use of Multithreading for Exception Handling / C. Zilles ; J. Emer |
| Value Prediction for Speculative Multithreaded Architectures / P. Marcuello ; J. Tubella |
| Low Power Enhancements / Mateo ValeroSession 9： |
| Predicting the Usefulness of a Block Result: A Micro-Architectural Technique for High-Performance Low-Power Processors / E. Musoll |
| Selective Cache Ways: On-Demand Cache Resource Allocation / D. Albonesi |
| Compilers / David BernsteinSession 10： |
| Wavefront Scheduling: Path based Data Representation and Scheduling of Subgraphs / J. Bharadwaj ; K. Menezes ; C. McKinsey |
| Balance Scheduling: Weighting Branch Tradeoffs in Superblocks / A. Eichenberger ; W. Meleis |
| Optimizations and Oracle Parallelism with Dynamic Translation / K. Ebcioglu ; E. Altman ; S. Sathaye ; M. Gschwind |
| Summary and Awards / Session 11： |
| Index of Authors |
| Foreword |
| Committees |
| Reviewers |
| Welcome and Keynote / Uri WeiserSession 1： |
| New Microarchitecture Challenges in the Coming Generations of CMOS Process Technologies / F. Pollack |
| Faster FrontEnd / Gary TysonSession 2： |
