Records of the 2000 IEEE International Workshop on Memory Technology, Design and Testing, August 7-8, 2000, San Jose, California, USA

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Records of the 2000 IEEE International Workshop on Memory Technology, Design and Testing, August 7-8, 2000, San Jose, California, USA / edited by R. Rajsuman, T. Wik ; sponsored by IEEE Computer Society, IEEE Computer Society Technical Committee on VLSI, IEEE Computer Society Technical Council on Test Technology ; in cooperation with The IEEE Solid State Circuits Society

資料種別:

図書

出版情報:

Los Alamitos, Calif. : Institute of Electrical and Electronics Engieers, c2000

形態:

x, 131 p. ; 28 cm

著者名:

IEEE International Workshop on Memory Technology, Design, and Testing <DA12300318>

Rajsuman, Rochit <DA06745397>

Wik, T.

IEEE Computer Society <DA00479199>

IEEE Computer Society. Test Technology Technical Council <DA1250352X>

IEEE Computer Society. Technical Committee on VLSI <DA04967445>

IEEE Solid State Circuits Society

さらに 2 件

ISBN:

9780769506890 [0769506895]
9780769506906 [0769506909] (:case.)

書誌ID:

BA48496452

子書誌情報

フルテキスト

所蔵情報

他の版・巻

書誌詳細

その他の標題:

PR00689
Memory Technology, Design and Testing
MTDT 2000

ISSN:

10874852

注記:

"IEEE Computer Society Order Number PR00689"--T.p. verso
Includes bibliographical references and index

言語:

英語

目次情報:

Message from the General Chair

Message from the Technical Program Chair

Conference Committee

Plenary Session

Welcome Message / R. Rajsuman, General Chair

Program Introduction / T. Wik, Program Chair

Keynote Address

Key Trends in Memory Applications and Impact on Memory Technology and Design / Dr. Handel Jones

Failure Mechanism/Defects / Betty PrinceSession 1：

Failure Mechanisms in Semiconductor Memory Circuits / R. Haythornthwaite

Diagnosing the Interconnect of Bus-Connected Multi-RAM Systems under Restricted and General Fault Models / J. Zhao ; F. Meyer ; F. Lombardi

Optimizing Memory Tests by Analyzing Defect Coverage / A. Jee ; J. Colburn ; V. Irrinki ; M. Puri

Flash/EEPROM Design / Alex Shubat ; Virage LogicSession 2：

Hierarchical Sector Biasing Organization for Flash Memories / R. Micheloni ; M. Zammattio ; G. Campardo ; O. Khouri ; G. Torelli

Fast Voltage Regulator for Multilevel Flash Memories / S. Gregori

Design Techniques for Embedded Eeprom Memories in Portable Asic and Assp Solutions / J. Daga ; C. Papaix ; M. Merandat ; S. Ricard ; G. Medulla ; J. Guichaoua ; D. Auvergne

New Ideas / Fabrizio LombardiSession 3：

Windowed Mram Sensing Scheme / R. Zhang ; W. Black, Jr. ; M. Hassoun

Panel: Future Memorq Challenges / Session 4：

Test and Yield / Robert EvansSession 5：

Tutorial: Synchronous Dynamic Memory Test Construction: A Field Approach / J. Vollrath

Yield Analysis Methodology for Low Defectivity Wafer Fabs / K. Rajkanan

Memorq Testing and Built-In Self-Test / Swamy IrrinkiSession 6：

March Tests for Realistic Faults in Two-Port Memories / S. Hamdioui ; M. Rodgers ; Ad J. van de Goor ; D. Eastwick

A Simple Built-In Self Test for Dual Ported SRAMs / K. Truong

Using Glfsrs for Pseudo-Random Memory Bist / M. Redeker ; M. Rudack ; T. Lobbe ; D. Niggemeyer

Invited Rddress

1-T Sram / Fu-Chieh Hsu

Memorq Design / Robert GibbinsSession 7：

Optimizing Meory Bandwidth with ILP Based Memory Exploration and Assignment for Low Power Embedded Systems / W.-T. Shiue

66MHz 2.3M Ternary Dynamic Content Addressable Memory / V. Lines ; A. Ahmed ; P. Ma ; S. Ma ; R. McKenzie ; H.-S. Kim ; C. Mar

A Low Voltage Embedded Single Port Sram Generator in a 0.18[mu]m Standard Cmos Process / C. Frey ; F. Genevaux ; C. Issartel ; D. Turgis ; JP. Schoellkopf

Diagnosis / Sharon MurraySession 8：

Diagnostic Testing of Embedded Memories Based on Output Tracing / E. Rudnick

Defect Analysis and Realistic Fault Model Extensions for Static Random Access Memories / K. Zarrineh ; A. Deo ; R. Adams

Crosstalk in Deep Submicron Drams / Z. Yang ; S. Mourad

Author Index

Message from the General Chair

Message from the Technical Program Chair

Conference Committee

Plenary Session

Welcome Message / R. Rajsuman, General Chair

Program Introduction / T. Wik, Program Chair

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