Proceedings : 2000 International Conference on Computer Design, 17-20 September 2000, Austin, Texas

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Proceedings : 2000 International Conference on Computer Design, 17-20 September 2000, Austin, Texas / sponsored by IEEE Computer Society, IEEE Circuits and Systems Society ; in cooperation with IEEE Electron Devices Society

資料種別:

図書

出版情報:

Los Alamitos, Calif. : IEEE Computer Society, c2000

形態:

xvii, 611 p. ; 28 cm

著者名:

ISBN:

9780780366282 [078036628X] (: case)
9780769508016 [0769508014] (: pbk)
9780780366299 [0780366298] (: microfiche)

書誌ID:

BA49326695

子書誌情報

フルテキスト

所蔵情報

他の版・巻

書誌詳細

その他の標題:

2000 IEEE International Conference on Computer Design
ICCD 2000
00PR0801, 00CB37151

注記:

Includes bibliographical references and index
"IEEE CSP No. 00PR0801"--T.p. verso

言語:

英語

目次情報:

Chairs' Message

Conference Organizers

Program Committee

Additional Reviewers

Keynote Address

On the Road to a Mobile Information Society / Dirk Friebel

New Architectures / Mauricio BreternitzSession 1.1：

Architectural Impact of Secure Socket Layer on Internet Servers / K. Kant ; R. Iyer ; P. Mohapatra

Fast Subword Permutation Instructions Using Omega and Flip Network Stages / X. Yang ; R. Lee

Sleipnir--An Instruction-Level Simulator Generator / T. Jeremiassen

Fault-Simulation and ATPG at Different Design Levels / Nur ToubaSession 1.2：

Analog Transient Concurrent Fault Simulation with Dynamic Fault Grouping / J. Hou ; A. Chatterjee

Pseudoexhaustive TPG with a Provably Low Number of LFSR Seeds / D. Kagaris ; S. Tragoudas

An Application of Genetic Algorithms and BDDs to Functional Testing / F. Ferrandi ; A. Fin ; F. Fummi ; D. Sciuto

Advanced Design Techniques / Ken ShepardSession 1.3：

High-Performance, Low-Power Skewed Static Logic in Very Deep-Submicron (VDSM) Technology / C. Kim ; J. Lee ; K.-H. Baek ; E. Martina ; S.-M. Kang

Estimation of Inductive and Resistive Switching Noise on Power Supply Network in Deep Sub-micron CMOS Circuits / S. Zhao ; K. Roy ; C.-K. Koh

Self-Calibrating Clocks for Globally Asynchronous Locally Synchronous Systems / S. Moore ; G. Taylor ; P. Cunningham ; R. Mullins ; P. Robinson

Improving CPU Performance / Brian GraysonSession 2.1：

Hybridizing and Coalescing Load Value Predictors / M. Burtscher ; B. Zorn

A 2-Way Thrashing-Avoidance Cache (TAC): An Efficient Instruction Cache Scheme for Object-Oriented Languages / Y. Chu ; M. Ito

Architectural Support for Dynamic Memory Management / J. Chang ; W. Srisa-an ; C.-T. Lo

SCIMA: Software Controlled Integrated Memory Architecture for High Performance Computing / M. Kondo ; H. Okawara ; H. Nakamura ; T. Boku

Parasitic Modeling, Analysis, and Optimization / Tom DillingerSession 2.2：

Worst Delay Estimation in Crosstalk Aware Static Timing Analysis / T. Xiao ; M. Marek-Sadowska

Analysis and Optimization of Ground Bounce in Digital CMOS Circuits / P. Heydari ; M. Pedram

An Efficient and Accurate Model for RF/Microwave Spiral Inductors Using Microstrip Lines Theory / N. Masoumi ; S. Safavi-Naeini ; M. Elmasry

Comparative Study of Parallel Algorithms for 3-D Capacitance Extraction on Distributed Memory Multiprocessors / Y. Yuan ; P. Banerjee

Low Power and Arithmetic / Margarida JacomeSession 2.3：

A Novel Low-Power Microprocessor Architecture / R. Hakenes ; Y. Manoli

A Power Perspective of Value Speculation for Superscalar Microprocessors / R. Moreno ; L. Pinuel ; S. del Pino ; F. Tirado

Multilevel Reverse-Carry Adder / J. Bruguera ; T. Lang

Evaluating Signal Processing and Multimedia Applications on SIMD, VLIW and Superscalar Architectures / D. Talla ; L. John ; V. Lapinskii ; B. Evans

Servers and Parallelism / Ruby LeeSession 3.1：

Unified Fine-Granularity Buffering of Index and Data: Approach and Implementation / Q. Cao ; J. Torrellas ; H. Jagadish

Analysis of Shared Memory Misses and Reference Patterns / J. Rothman ; A. Smith

Power-Sensitive Multithreaded Architecture / J. Seng ; D. Tullsen ; G. Cai

Circuit Optimization and Analysis / Shervin HojatSession 3.2：

Delay Constrained Optimization by Simultaneous Fanout Tree Construction, Buffer Insertion/Sizing and Gate Sizing / I-M. Liu ; A. Aziz

Application-Based, Transistor-Level Full-Chip Power Analysis for 700 MHz PowerPC Microprocessor / Y.-K. Cheng ; D. Bearden ; K. Suryadevara

Buffer Library Selection / C. Alpert ; R. Gandham ; J. Neves ; S. Quay

High-Performance Low-Power CMOS Circuits Using Multiple Channel Length and Multiple Oxide Thickness / N. Sirisantana ; L. Wei

Logic Circuit Families / Shyh-Jye JouSession 3.3：

Current-Mode Threshold Logic Gates / S. Bobba ; I. Hajj

Skewed CMOS: Noise-Immune High-Performance Low-Power Static Circuit Family / A. Solomatnikov ; D. Somasekhar

Output Prediction Logic: A High-Performance CMOS Design Technique / L. McMurchie ; S. Kio ; G. Yee ; T. Thorp ; C. Sechen

The Future of Populist Parallelism / Greg Pfister

Intelligent Memory / Steven ReinhardtSession 4.1：

A Study of Channeled DRAM Memory Architectures / L. Friebe ; Y. Yabe ; M. Motomura

DRAM-Page Based Prediction and Prefetching / H. Yu ; G. Kedem

Reducing Cost and Tolerating Defects in Page-Based Intelligent Memory / M. Oskin ; D. Keen ; J. Hensley ; L.-V. Lita ; F. Chong

Processor Microarchitecture / Steve FurberSession 4.2：

A Selective Temporal and Aggressive Spatial Cache System Based on Time Interval / J.-H. Lee ; J.-S. Lee ; S.-D. Kim

Design of Instruction Stream Buffer with Trace Support for X86 Processors / J.-C. Chiu ; I-H. Huang ; C.-P. Chung

A Trace Based Evaluation of Speculative Branch Decoupling / A. Nadkarni ; A. Tyagi

Digital Logic Techniques / Barbara ChappellSession 4.3：

An Adder Using Charge Sharing and Its Application in DRAMs / H.-S. Yu ; S. Lee ; J. Abraham

Fixed-Width Multiplier for DSP Application / S.-J. Jou ; H.-H. Wang

Dynamic Flip-Flop with Improved Power / N. Nedovic ; V. Oklobdzija

Embedded Processors: Architecture and System-Design Issues / Ricardo GonzalesSession 5.1：

Processors for Mobile Applications / F. Koushanfar ; V. Prabhu ; M. Potkonjak ; J. Rabaey

AMULET3: A 100 MIPS Asynchronous Embedded Processor / S. Furber ; D. Edwards ; J. Garside

Xtensa with User Defined DSP Coprocessor Microarchitectures / G. Ezer

Predictive Strategies for Low-Power RTOS Scheduling / P. Kumar ; M. Srivastava

Floorplanning and Partitioning / Tim BurksSession 5.2：

Rectilinear Block Placement Using B*-Trees / G.-M. Wu ; Y.-C. Chang ; Y.-W. Chang

Fast Hierarchical Floorplanning with Congestion and Timing Control / A. Ranjan ; K. Bazargan ; M. Sarrafzadeh

An Evaluation of Move-Based Multi-Way Partitioning Algorithms / E. Yarack ; J. Carletta

Assignment-Space Exploration Approach to Concurrent Data-Path/Floorplan Synthesis / K. Oohashi ; M. Kaneko ; S. Tayu

Basic Algorithms in Verification and Test / Yatin HoskoteSession 5.3：

On Solving Stack-Based Incremental Satisfiability Problems / J. Kim ; J. Whittemore ; K. Sakallah

Efficient Dynamic Minimization of World-Level DDs Based on Lower Bound Computation / W. Gunther ; R. Drechsler ; S. Horeth

Sensitivity Levels of Test Patterns and Their Usefulness in Simulation-Based Test Generation / I. Pomeranz ; S. Reddy

On Test Application Time and Defect Detection Capabilities of Test Sets for Scan Designs

Special Session: Advancements in DSP Architecture / Jim Bondi ; Nagaraj NSSession 6.1：

Effective Hardware-Based Two-Way Loop Cache for High Performance Low Power Processors / T. Anderson ; S. Agarwala

A Multi-Level Memory System Architecture for High-Performance DSP Applications / C. Fuoco ; D. Comisky ; C. Mobley

A Scalable High-Performance DMA Architecture for DSP Applications

Advanced Architectural Design and Synthesis / Edward GrochowskiSession 6.2：

Efficient Place and Route for Pipeline Reconfigurable Architectures / S. Cadambi ; S. Goldstein

PEAS-III: An ASIP Design Environment / M. Itoh ; S. Higaki ; J. Sato ; A. Shiomi ; Y. Takeuchi ; A. Kitajima ; M. Imai

Symbolic Binding for Clustered VLIW ASIPs / S. Pillai ; M. Jacome

Interfacing Hardware and Software Using C++ Class Libraries / D. Ramanathan ; R. Roth ; R. Gupta

Application and Case Studies in Test and Verification / Carl PixleySession 6.3：

Formal Verification of an Industrial System-on-a-Chip / H. Choi ; M.-K. Yim ; J.-Y. Lee ; B.-W. Yun ; Y.-T. Lee

Equivalence Checking Combining a Structural SAT-Solver, BDDs, and Simulation / V. Paruthi ; A. Kuehlmann

Efficient Design Error Correction of Digital Circuits / D. Hoffmann ; T. Kropf

An Automatic Validation Methodology for Logic BIST in High Performance VLSI Design / M. Cogswell ; D. Pearl ; J. Sage ; A. Troidl

Invited Paper

The Birth of the Baby / H. Kahn ; R. Napper

Logic Optimization / Chin-Long WeySession 7.1：

Efficient Logic Optimization Using Regularity Extraction / T. Kutzschebauch

Binary and Multi-Valued SPFD-Based Wire Removal in PLA Networks / S. Sinha ; S. Khatri ; R. Brayton ; A. Sangiovanni-Vincentelli

Minimization of Ordered Pseudo Kronecker Decision Diagrams / P. Lindgren ; B. Becker

High Level Specification and Synthesis / Pranav AsharSession 7.2：

Rethinking Behavioral Synthesis for a Better Integration within Existing Design Flows / W. Cesario ; A. Jerraya ; Z. Sugar ; I. Moussa

Synthesis and Optimization of Interface Hardware between IP's Operating at Different Clock Frequencies / B.-I. Park ; I.-C. Park ; C.-M. Kyung

Multi-Level Communication Synthesis of Heterogeneous Multilanguage Specification / F. Hessel ; P. Coste ; G. Nicolescu ; P. LeMarrec ; N. Zergainoh

Poster Sessions

Low Power Video Object Motion-Tracking Architecture for Very Low Bit Rate Online Video Applications / W. Badawy ; M. Bayoumi

An SEU Injection Tool to Evaluate DSP-Based Architectures for Space Applications / A. Benso ; S. Martinetto ; P. Prinetto ; R. Mariani

On Integrating a Proprietary and a Commercial Architecture for Optimal BIST Performances in SoCs / S. Di Carlo ; S. Chiusano ; F. Ricciato ; M. Bodoni ; M. Spadari

Static Timing Analysis with False Paths / H. Chen ; B. Lu ; D.-Z. Du

A Methodology and Tool for Automated Transformational High-Level Design Space Exploration / J. Gerlach ; W. Rosenstiel

Cheap Out-of-Order Execution Using Delayed Issue / J. Grossman

Representing and Scheduling Looping Behavior Symbolically / S. Haynal ; F. Brewer

Advanced Wiring RC Timing Design Techniques for Logic LSIs in Gigahertz Era and Beyond / Y. Ito ; S. Isomura ; T. Hiyama ; K. Nojiri

A Register File with Transposed Access Mode / Y. Jung ; S. Berg ; D. Kim ; Y. Kim

Leakage Power Analysis and Reduction during Behavioral Synthesis / K. Khouri ; N. Jha

An Advanced Instruction Folding Mechanism for a Stackless Java Processor / A. Kim ; M. Chang

OpenDesign: An Open User-Configurable Project Environment for Collaborative Design and Execution on the Internet / H. Lavana ; F. Brglez ; R. Reese ; G. Konduri ; A. Chandrakasan

A Decompression Architecture for Low Power Embedded Systems / H. Lekatsas ; J. Henkel ; W. Wolf

Optimal vs. Heuristic Approaches to Context Scheduling for Multi-Context Reconfigurable Architectures / R. Maestre ; F. Kurdahi ; M. Fernandez ; R. Hermida ; N. Bagherzadeh ; H. Singh

The M-CORE M340 Unified Cache Architecture / A. Malik ; B. Moyer ; D. Cermak

Crosstalk-Constrained Performance Optimization by Using Wire Sizing and Perturbation / S.-R. Pan

Hierarchical Simulation of a Multiprocessor Architecture / M. Pirvu ; L. Bhuyan ; R. Mahapatra

On Multiple Precision Based Montgomery Multiplication without Precomputation of N[subscript 0]' = -N[subscript 0 superscript -1] mod W / H. Ploog ; D. Timmerman

A Technique for Identifying RTL and Gate-Level Correspondences / S. Ravi ; I. Ghosh ; V. Boppana

A Direct Mapping FPGA Architecture for Industrial Process Control Applications / J. Welch

Source-Level Transformations for Improved Formal Verification / B. Winters ; A. Hu

Author Index

Chairs' Message

Conference Organizers

Program Committee

Additional Reviewers

Keynote Address

On the Road to a Mobile Information Society / Dirk Friebel

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