Proceedings, 2000 IEEE Symposium on Field-Programmable Custom Computing Machines, April 17-19, 2000, Napa Valley, California

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Proceedings, 2000 IEEE Symposium on Field-Programmable Custom Computing Machines, April 17-19, 2000, Napa Valley, California / sponsored by IEEE Computer Society Technical Committee on Computer Architecture ; edited by Brad L. Hutchings

資料種別:

図書

出版情報:

Los Alamitos, Calif. : IEEE Computer Society Press, c2000

形態:

x, 348 p. ; 28 cm

著者名:

ISBN:

9780769508719 [0769508715]

書誌ID:

BA51157750

子書誌情報

フルテキスト

所蔵情報

他の版・巻

書誌詳細

その他の標題:

PR00871
FCCM 2000

ISSN:

10823409

注記:

"IEEE Computer Society Order Number PR00871"--T.p. verso
"IEEE Order Plan Catalog Number PR00871"--T.p. verso
Includes bibliographical references and index

言語:

英語

目次情報:

Conference Organizers

Architecture / Andre DeHonSession 1：

Design of a VLIW Compute Accelerator on the Transmogrifier-2 / L. Zhang ; Q. Wang ; D. Lewis

A Scalable, Loadable Custom Programmable Logic Device for Solving Boolean Satisfiability Problems / M. Boyd ; T. Larrabee

Configuration Caching Management Techniques for Reconfigurable Computing / Z. Li ; K. Compton ; S. Hauck

Compilation 1 / Wayne LukSession 2：

A Matlab Compiler for Distributed, Heterogeneous, Reconfigurable Computing Systems / P. Banerjee ; N. Shenoy ; A. Choudhary ; C. Bachmann ; M. Haldar ; P. Joisha ; A. Jones ; A. Kanhare ; A. Nayak ; S. Periyacheri ; M. Walkden ; D. Zaretsky

Stream-Oriented FPGA Computing in the Streams-C High Level Language / M. Gokhale ; J. Stone ; J. Arnold ; M. Kalinowski

Applications 1 / Philip FreidenSession 3：

A Reconfigurable Computing Architecture for Microsensors / S. Scalera ; M. Falco ; B. Nelson

FPGA Implementation of a Microcoded Elliptic Curve Cryptographic Processor / K. Leung ; K. Ma ; W. Wong ; P. Leong

Customizing Graphics Applications: Techniques and Programming Interface / H. Styles ; W. Luk

Compilation 2 / Scott HauckSession 4：

Automatic Synthesis of Data Storage and Control Structures for FPGA-Based Computing Engines / P. Diniz ; J. Park

A C to HDL Compiler for Pipeline Processing on FPGAs / T. Maruyama ; T. Hoshino

Cryptographic Applications / John McHenrySession 5：

High Performance DES Encryption in Virtex FPGAs Using Jbits / C. Patterson

A Bit-Serial Implementation of the International Data Encryption Algorithm IDEA / M. Leong O. Cheung ; K. Tsoi

An Adaptive Cryptographic Engine for IPSec Architectures / A. Dandalis ; V. Prasanna ; J. Rolim

Programming Tools / Brad HutchingsSession 6：

Death of the RLOC? / S. Singh

Automated Extraction of Run-Time Parameterizable Cores from Programmable Device Configurations / P. James-Roxby ; S. Guccione

Fault Tolerance / Philip KuekesSession 7：

Dynamic Fault Tolerance in FPGAs via Partial Reconfiguration / J. Emmert ; C. Stroud ; B. Skaggs ; M. Abramovici

An ACS Robotic Control Algorithm with Fault Tolerant Capabilities / S-Y. Yu ; N. Saxena ; E. McCluskey

Tunable Fault Tolerance for Runtime Reconfigurable Architectures / S. Sinha ; P. Kamarchik ; S. Goldstein

Wireless Applications / Tom KeanSession 8：

Synchronization in Software Radios--Carrier and Timing Recovery Using FPGAs / C. Dick ; F. Harris ; M. Rice

Architecture and Application of a Dynamically Reconfigurable Hardware Array for Future Mobile Communication Systems / A. Alsolaim ; J. Becker ; M. Glesner ; J. Starzyk

Applications 2 / Mike ButtsSession 9：

Implementation of Near Shannon Limit Error-Correcting Codes Using Reconfigurable Hardware / B. Levine ; R. Taylor ; H. Schmit

Hardware-Software Codesign and Parallel Implementation of a Golomb Ruler Derivation Engine / E. Sotiriades ; A. Dollas ; P. Athanas

An FPGA-Based Coprocessor for the Parsing of Context-Free Grammars / C. Ciressan ; E. Sanchez ; M. Rajman ; J-C. Chappelier

Applications 3 / Don BouldinSession 10：

A Reliable LZ Data Compressor on Reconfigurable Coprocessors / W-J. Huang

Evidence: An FPGA-Based System for Photon EVent IDENtification and CEntroiding / M. Alderighi ; S. D'Angelo ; G. Sechi

Improving the Performance and Efficiency of an Adaptive Amplification Operation Using Configurable Hardware / M. Wirthlin ; S. Morrison ; P. Graham ; B. Bray

Poster Session 1

Configuration Relocation and Defragmentation for Reconfigurable Computing / J. Cooley ; S. Knol

Mapping Algorithms for a Multi-Bit Data Path Processing Reconfigurable Chip RHW / T. Yamauchi ; S. Nakaya ; T. Inuo ; N. Kajihara

Hardware Accelerator for Subgraph Isomorphism Problems / S. Ichikawa ; L. Udorn ; K. Konishi

A Reconfigurable Hardware Platform for Digital Real-Time Signal Processing in Television Studios / K. Henriss ; P. Ruffer ; R. Ernst ; S. Hasenzahl

Reconfigurable Array Media Processor (RAMP) / K. Rath ; S. Tangirala ; P. Friel ; P. Bolsara ; J. Flores ; J. Wadley

Internet Connected FPGAs / H. Fallside ; M. Smith

A Reconfigurable Stochastic Model Simulator for analysis of parallel systems / O. Yamamoto ; Y. Shibata ; H. Kurosawa ; H. Amano

Poster Session 2

A Virtual Hardware System on a Dynamically Reconfigurable Logic Device / M. Uno ; K. Furuta ; T. Fujii ; M. Motomura

Optimal vs. Heuristic Approaches to Context Scheduling for Multi-Context Reconfigurable Architectures / R. Maestre ; F. Kurdahi ; M. Fernandez ; R. Hermida ; N. Bagherzadeh ; H. Singh

A Communication Scheduling Algorithm For Multi-FPGA Systems / J. Suh ; D-I. Kang ; S. Crago

Preemptive Multitasking on FPGAs / L. Levinson ; R. Manner ; M. Sessler ; H. Simmler

BigSky--An On-Line Arithmetic Design Tool for FPGAs / A. Schneider ; R. McIlhenny ; M. Ercegovac

Improving the FPGA Design Process through Determining and Applying Logical-to-Physical Design Mappings / B. Hutchings

Multiple Precision for Resource Minimization / G. Constantinides ; P. Cheung

StReAm: Object-Oriented Programming of Stream Architectures Using PAM-Blox / O. Mencer ; H. Hubert ; M. Morf ; M. Flynn

Poster Session 3

An FPGA-Based Array Processor for an Ionospheric-Imaging Radar / T. Tuan ; M. Figueroa ; F. Lind ; X. Zhou ; X. Diorio ; J. Sahr

Embedded Compilation for Multimedia Applications / N. Daw ; D. Strelow

Interfacing Reconfigurable Logic with a CPU / K. Walker ; M. Budiu

A Run-Time Reconfigurable Plug-In for the Winamp MP3 Player / J. Scalera ; M. Jones

Accelerating Embedded Applications Using Dynamically Reconfigurable Hardware and Evolutionary Algorithms / J. Harkin ; T. McGinnity ; L. Maguire

Implementation of a Configurable Controller for an AC Drive Control: A Case Study / M. Imecs ; P. Bikfalvi ; S. Nedevschi ; J. Vasarhelyi

Pattern Recognition and Reconstruction on an FPGA Coprocessor Board

Poster Session 4

FCCMs and the Memory Wall / S. Derrien ; S. Rajopadhye

A C to Hardware/Software Compiler / K. Bazargan ; R. Kastner ; S. Ogrenci ; M. Sarrafzadeh

Evaluating Hardware Compilation Techniques / M. Weinhardt

Adapting Constant Multipliers in a Neural Network Implementation / B. Blodget

A Networked FPGA-Based Hardware Implementation of a Neural Network Application / H. Restrepo ; R. Hoffmann ; A. Perez-Uribe ; C. Teuscher

Design of C++ Class Library and Bit-Serial Compiler for Variable-Precision Datapath Synthesis on Adaptive Computing Systems / K. Suzuki ; M. Wang ; F. Zhao ; W. Dai

An Investigation of Reconfigurable Multipliers for Use in Adaptive Signal Processing / T. Courtney ; R. Turner ; R. Woods

Combining Serialization and Reconfiguration for Convolver Designs / A. Derbyshire

Author Index

Conference Organizers

Architecture / Andre DeHonSession 1：

Design of a VLIW Compute Accelerator on the Transmogrifier-2 / L. Zhang ; Q. Wang ; D. Lewis

A Scalable, Loadable Custom Programmable Logic Device for Solving Boolean Satisfiability Problems / M. Boyd ; T. Larrabee

Configuration Caching Management Techniques for Reconfigurable Computing / Z. Li ; K. Compton ; S. Hauck

Compilation 1 / Wayne LukSession 2：

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