Proceedings IEEE International Conference on Application-Specific Systems, Architectures, and Processors, July 10-12, 2000, Boston, Massachusetts

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Proceedings IEEE International Conference on Application-Specific Systems, Architectures, and Processors, July 10-12, 2000, Boston, Massachusetts / Sponsored by IEEE Computer Society ; edited by Earl E. Swartlander, Graham A. Jullien, Machael J. Schulte

資料種別:

図書

出版情報:

Los Alamitos, Calif. ; Tokyo : IEEE Computer Society Press, c2000

形態:

xiv, 360 p. ; 24 cm

著者名:

ISBN:

9780769507163 [0769507166]

書誌ID:

BA51160890

子書誌情報

フルテキスト

所蔵情報

他の版・巻

書誌詳細

その他の標題:

PR00716, 97TB100177
ASAP 2000

ISSN:

10636862

注記:

"IEEE Computer Society order number PR00716"-T.p. verso
"IEEE order plan catalog number 97TB100177"-on cover
Includes bibliographical references and author index

言語:

英語

目次情報:

Message from the Conference Chairs

Conference Organizers

Keynote

High-Performance Front-End Embedded Signal Processors for Adaptive Sensor Arrays / W. Song

Video and Multimedia Processors / Jurgen Teich

Subword Permutation Instructions for Two-Dimensional Multimedia Processing in MicroSIMD Architectures / R. Lee

Architecture of an Image Rendering Co-Processor for MPEG-4 Systems / M. Berekovic ; P. Pirsch ; T. Selinger ; K.-I. Wels ; C. Miro ; A. Lafage ; C. Heer ; G. Ghigo

A Multiplication-Free Parallel Architecture for Affine Transformation / W. Badawy ; M. Bayoumi

A Simple RISC Microprocessor Core Designed for Digital Set-Top-Box Applications / M. Dal Poz ; J. Aedo Cobo ; W. Van Noije ; M. Zuffo

Reconfigurable Computing / Doran Wilde

Formal Verification for Microprocessors with Extendable Instruction Set / S. Sawitzki ; R. Spallek ; J. Schonherr ; B. Straube

Compiling Image Processing Applications to Reconfigurable Hardware / R. Rinker ; J. Hammes ; W. Najjar ; W. Bohm ; B. Draper

Integration of High-Performance ASICs into Reconfigurable Systems Providing Additional Multimedia Functionality / H. Blume ; H.-M. Bluthgen ; C. Henning ; P. Osterloh

Modeling and Synthesis / Shuvra Bhattacharyya

High Level Modeling for Parallel Executions of Nested Loop Algorithms / E. Deprettere ; E. Rijpkema ; P. Lieverse ; B. Kienhuis

Minimal Complexity Hierarchical Loop Representations of SFG Processors for Optimal High Level Synthesis / A. Stone ; E. Manolakos

High Level Synthesis for Peak Power Minimization Using ILP / W.-T. Shiue

High-Level Synthesis of Nonprogrammable Hardware Accelerators / R. Schreiber ; S. Aditya ; B. Ramakrishna Rau ; V. Kathail ; S. Mahlke ; S. Abraham ; G. Snider

Cryptography / Ruby Lee

Implementing 1,024-bit RSA Exponentiation on a 32-bit Processor Core / B. Phillips ; N. Burgess

Bit Permutation Instructions for Accelerating Software Cryptography / Z. Shi

Performance-Scalable Array Architectures for Modular Multiplication / W. Freking ; K. Parhi

Digital Signal Processing / Joseph Cavallaro

A 108 Gbps, 1.5 GHz 1D-DCT Architecture / A. Shams

Efficient VLSI Architectures for Baseband Signal Processing in Wireless Base-Station Receivers / S. Rajagopal ; S. Bhashyam ; J. Cavallaro ; B. Aazhang

A Vector Multiprocessor for Real-Time Multi-User Detection in Spread-Spectrum Communication / N. Manjikian

A 550 Mb/s Radix-4 Bit-level Pipelined 16-State 0.25-[mu]m CMOS Viterbi Decoder / V. Gierenz ; O. Weiss ; T. Noll ; I. Carew ; J. Ashley ; R. Karabed

Arithmetic / Magdy Bayoumi

A Booth Multiplier Accepting Both a Redundant or a Non-Redundant Input with No Additional Delay / M. Daumas ; D. Matula

A Hardware Algorithm for Variable-Precision Logarithm / J. Hormigo ; J. Villalba ; M. Schulte

Block-Update Parallel Processing QRD-RLS Algorithm for Throughput Improvement with Low Power Consumption / L. Gao

A 16-bit x 16-bit MAC Design Using Fast 5:2 Compressors / O. Kwon ; K. Nowka ; E. Swartzlander

Multiprocessor Systems / Ed Deprettere

Control for High-Speed PE Arrays / M. Herbordt ; J. Cravy ; H. Zhang ; C. Lin ; H. Rao

Explicit SIMD Programming for Asynchronous Applications / A. Di Blas ; R. Hughey

Quadratic Control Signals in Linear Systolic Arrays / S. Bowden ; D. Wilde ; S. Rajopadhye

Contention-Conscious Transaction Ordering in Embedded Multiprocessors / M. Khandelia ; S. Bhattacharyya

Application-Specific Architectures / Neil Burgess

Architecture for Wavelet Packet Transform with Best Tree Searching / M. Trenas ; J. Lopez ; M. Sanchez ; F. Arguello ; E. Zapata

Tradeoff Analysis and Architecture Design of a Hybrid Hardware/Software Sorter / M. Bednara ; O. Beyer ; J. Teich ; R. Wanka

A Programmable Processor for Approximate String Matching with High Throughput Rate

Design Methodology / Elias Manolakos

A New Algorithm for the Elimination of Common Subexpressions in Hardware Implementation of Digital Filters by Using Genetic Programming / H. Safiri ; M. Ahmadi ; G. Jullien ; W. Miller

A Theory for Software-Hardware Co-Scheduling for ASIPs and Embedded Processors / R. Govindarajan ; E. Altman ; G. Gao

Partitioning Conditional Data Flow Graphs for Embedded System Design / M. Auguin ; L. Bianco ; L. Capella ; E. Gresset

Generation of Scheduling Functions Supporting LSGP-Partitioning / D. Fimmel

Author Index

Message from the Conference Chairs

Conference Organizers

Keynote

High-Performance Front-End Embedded Signal Processors for Adaptive Sensor Arrays / W. Song

Video and Multimedia Processors / Jurgen Teich

Subword Permutation Instructions for Two-Dimensional Multimedia Processing in MicroSIMD Architectures / R. Lee

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