Preface |
Symposium Organizers and Program Committee |
Referees |
Invited Address / Session 1: |
Algebras for Hazard Detection / J. Brzozowski ; Z. Esik ; Y. Iland |
Circuits I / Session 2a: |
A New Improved Cost-Table-Based Technique for Synthesis of 4-Valued Unary Functions Implemented Using Current-Mode CMOS Circuits / M. Abd-El-Barr ; A. Al-Mutawa |
Dual-Rail Multiple-Valued Current-Mode VLSI with Biasing Current Sources / T. Ike ; T. Hanyu ; M. Kameyama |
Realization of NMAX and NMIN Functions with Multi-Valued Voltage Comparators / M. Inaba ; K. Tanno ; O. Ishizuka |
Design and Verification of Systems / Session 2b: |
An Application of Multiple-Valued Logic to Test Case Generation for Software System Functional Testing / M. Hu |
Spectral Techniques in Binary and Multiple-Valued Switching Theory / M. Karpovsky ; R. Stankovic ; C. Moraga |
Tunnelling Diode Technology / W. Prost ; U. Auer ; F-J. Tegude ; C. Pacha ; K. Goser ; R. Duschl ; K. Eberl ; O. SchmidtSession 3: |
Circuits II / Session 4a: |
Power Efficient Inter-Module Communication for Digit-Serial DSP Architectures in Deep-Submicron Technology / I. Ben Dhaou ; E. Dubrova ; H. Tenhunen |
A 4-Digit CMOS Quaternary to Analog Converter with Current Switch and Neuron MOS Down-Literal Circuit / S. Han ; Y. Choi ; H. Kim |
Fuzzy Logics and Their Applications I / Session 4b: |
On Some Classes of Fuzzy Information Relations / A. Radzikowska ; E. Kerre |
On Complete Residuated Many-Valued Logics with T-Norm Conjunction / F. Esteva ; L. Godo |
Circuits III / Session 5a: |
A Three-Valued D-Flip-Flop and Shift Register Using Multiple-Junction Surface Tunnel Transistors / T. Uemura ; T. Baba |
Flash Analog-to-Digital Converter Using Resonant-Tunneling Multiple-Valued Circuits / T. Waho ; K. Hattori ; Y. Takamatsu |
The Use of Arithmetic Operators in a Self-Restored Current-Mode CMOS Multiple-Valued Logic Design Architecture / H. Teng ; R. Bolton |
Fuzzy Logics and Their Applications II / Session 5b: |
Evaluation of Inconsistency in a 2-Way Fuzzy Adaptive System Using Shadowed Sets / E. Gurkan ; A. Erkmen ; I. Erkmen |
Identification of Incompletely Specified Fuzzy Unate Logic Function / H. Kikuchi |
Representation Theorems and the Semantics of (Semi)Lattice-Based Logics / V. Sofronie-StokkermansSession 6: |
Tutorial / Session 7: |
Tutorial: Complexity of Many-Valued Logics / R. Hahnle |
Exploiting Polarity in Multiple-Valued Inference Systems / Z. StachniakSession 8: |
Logic Design I / Session 9a: |
Multiple-Valued Galois Field S/D Trees for GFSOP Minimization and Their Complexity / A. Al-Rabadi ; M. Perkowski |
Multiple-Valued Mask-Programmable Logic Array Using One-Transistor Universal-Literal Circuits / K. Shimabukuro ; C. Zukeran |
Decomposition of Multi-Valued Functions into Min- and Max-Gates / C. Lang ; B. Steinbach |
Automated Reasoning and Complexity I / Session 9b: |
Cut-Elimination in a Sequents-of-Relations Calculus for Godel Logic / M. Baaz ; A. Ciabattoni ; C. Fermuller |
Model Checking with Multi-Valued Temporal Logics / M. Chechik ; S. Easterbrook ; B. Devereux |
Automated Reasoning with Ordinary Assertions and Default Assumptions / D. Van Heule ; A. Hoogewijs |
Logic Design II / Session 10a: |
Information Theory Method for Flexible Network Synthesis / V. Cheushev ; S. Yanushkevich ; V. Shmerko ; J. Kolodziejczyk |
Compact SOP Representations for Multiple-Output Functions: An Encoding Method Using Multiple-Valued Logic / T. Sasao |
Two-Stage Exact Detection of Symmetries / A. Tomaszewska ; P. Dziurzanski |
Automated Reasoning and Complexity II / Session 10b: |
A Modular Reduction of Regular Logic to Classical Logic / R. Bejar ; F. Manya |
Hypersequents as a Uniform Framework for Urquhart's C, MTL and Related Logics |
Polynomial-Time Algorithms for Verification of Some Properties of k-Valued Functions Represented by Polynomials / S. Selezneva |
Challenge of a Multiple-Valued Technology in Recent Deep-Submicron VLSI / Session 11: |
Computing Paradigms / Session 12a: |
A Model of Reaction-Diffusion Cellular Automata for Massively Parallel Molecular Computing / M. Hiratsuka ; T. Aoki ; T. Higuchi |
Synthesis of Multiple-Valued Arithmetic Circuits Using Evolutionary Graph Generation / M. Natsui |
An Axiomatization of Generalized Entropy of Partitions / D. Simovici ; S. Jaroszewicz |
MV Logics and Algebras I / Session 12b: |
Many Valued Paraconsistent Logic / C. Morgan |
On Logical Fiberings and Decomposition of Many-Valued Operations: A Brief Survey / J. Pfalzgraf |
Relations between Clones and Full Monoids / H. Machida ; M. Miyakawa ; I. Rosenberg |
Classical Gentzen-Type Methods in Propositional Many-Valued Logics / A. AvronSession 13: |
Decision Diagrams / Session 14a: |
Selection of Efficient Re-Ordering Heuristics for MDD Construction / F. Schmiedle ; W. Gunther ; R. Drechsler |
Bit-Level and Word-Level Polynomial Expressions for Functions in Fibonacci Interconnection Topologies / M. Stankovic ; J. Astola ; K. Egiazarian |
Design of Haar Wavelet Transforms and Haar Spectral Transform Decision Diagrams for Multiple-Valued Functions |
Fuzzy Logics and Set Theories / Session 14b: |
A Set Theory within Fuzzy Logic / P. Hajek ; Z. Hanikova |
On a Kleenean Extension of Fuzzy Measure / T. Araki ; M. Mukaidono ; F. Yamamoto |
On Axiomatic Characterization of Fuzzy Approximation Operators II. The Rough Fuzzy Set Based Case / H. Thiele |
Neural Networks / Session 15a: |
A Functional Manipulation for Improving Tolerance against Multiple-Valued Weight Faults of Feedforward Neural Networks / N. Kamiura ; Y. Taniguchi ; N. Matsui |
Logic Circuit Diagnosis by Using Neural Networks / H. Tatsumi ; Y. Murai ; S. Tokumasu |
The Designing and Training of a Fuzzy Neural Hamming Classifier / Q. Hua ; Q-L. Zhen |
MV Logics and Algebras II / Session 15b: |
Weierstrass Approximations by Lukasiewicz Formulas with One Quantified Variable / S. Aguzzoli ; D. Mundici |
Composing Submonads / P. Eklund ; M. Galan ; J. Medina ; M. Ojeda-Aciego ; A. Valverde |
A Method of Uncertainty Reasoning by Using Information / J. Ma ; J. Liu ; Y. Xu |
Author Index |
Preface |
Symposium Organizers and Program Committee |
Referees |
Invited Address / Session 1: |
Algebras for Hazard Detection / J. Brzozowski ; Z. Esik ; Y. Iland |
Circuits I / Session 2a: |