| Message from the Symposium Chair |
| Message from the Program Chair |
| Message from the 10th Anniversary Committee Chair |
| ATS 2000 Best Paper Award |
| Asian Test Committee |
| The 10th Asian Test Symposium Committee |
| Program Committee |
| Reviewers |
| TTTC Activities Board |
| Plenary Session: Keynote Address |
| DFT for High-Quality Low Cost Manufacturing Test / Janusz Rajski (Mentor Graphics Corporation, USA) |
| Design for Testability / Session 1A： |
| Design for Hierarchical Two-Pattern Testability of Data Paths / Md. Altaf-UI-Amin ; S. Ohtake ; H. Fujiwara |
| A Multiple Phase Partial Scan Design Method / D. Xiang ; Y. Xu |
| Sequential Redundancy Removal Using Test Generation and Multiple Unreachable States / H. Yotsuyanagi ; S. Hata ; M. Hashizume ; T. Tamesada |
| Fault Modeling for Memories / Session 1B： |
| Tests for Resistive and Capacitive Defects in Address Decoders / M. Klaus ; Ad J. van de Goor |
| Detecting Unique Faults in Multi-port SRAMs / S. Hamdioui ; D. Eastwick ; M. Rodgers |
| A Memory Specific Notation for Fault Modeling / Z. Al-Ars ; J. Braun ; D. Richter |
| Diagnosis / Session 1C： |
| On Pass/Fail Dictionaries for Scan Circuits / I. Pomeranz |
| Diagnosis by Repeated Application of Specific Test Inputs and by Output Monitoring of the MISA / M. Gossel ; V. Ocheretnij ; S. Chakrabarty |
| Simulation-Based Diagnosis for Crosstalk Faults in Sequential Circuits / H. Takahashi ; M. Phadoongsidhi ; Y. Higami ; K. Saluja ; Y. Takamatsu |
| ATPG / Session 2A： |
| Test Generation for Double Stuck-at Faults / N. Takahashi |
| Faulty Resistance Sectioning Technique for Resistive Bridging Fault ATPG Systems / T. Shinogi ; T. Kanbayashi ; T. Yoshikawa ; S. Tsuruoka ; T. Hayashi |
| On Improving a Fault Simulation Based Test Generator for Synchronous Sequential Circuits / R. Guo ; S. Reddy |
| Embedded Memory Test / Session 2B： |
| Automatic Generation of Memory Built-in Self-Test Cores for System-on-Chip / K.-L. Cheng ; C.-M. Hsueh ; J.-R. Huang ; J.-C. Yeh ; C.-T. Huang ; C.-W. Wu |
| A P1500 Compliant BIST-Based Approach to Embedded RAM Diagnosis / D. Appello ; F. Corno ; M. Giovinetto ; M. Rebaudengo ; M. Reorda |
| A Built-in Self-Test and Self-Diagnosis Scheme for Heterogeneous SRAM Clusters / C.-W. Wang ; R.-S. Tzeng ; C.-F. Wu ; S.-Y. Huang ; S.-H. Lin ; H.-P. Wang |
| I[subscript DDQ] Test and Diagnosis / Session 2C： |
| I[subscript DDQ] Sensing Technique for High Speed I[subscript DDQ] Testing / T. Takeda ; M. Ichimiya ; Y. Miura ; K. Kinoshita |
| CMOS Open Defect Detection Based on Supply Current in Time-Variable Electric Field and Supply Voltage Application |
| An Approach to Improve the Resolution of Defect-Based Diagnosis / I. Yamazaki ; H. Yamanaka ; T. Ikeda ; M. Takakura ; Y. Sato |
| Test Compaction / Session 3A： |
| A Postprocessing Procedure to Reduce the Number of Different Test Lengths in a Test Set for Scan Circuits |
| A Method of Static Compaction of Test Stimuli / K. Boateng ; H. Konishi ; T. Nakata |
| Dynamic Test Compression Using Statistical Coding / H. Ichihara ; A. Ogawa ; T. Inoue ; A. Tamura |
| Pattern Generation for Memory Test / Session 3B： |
| Guardband Determination for the Detection of Off-State and Junction Leakages in DRAM Testing / M.-J. Wang ; R.-L. Jiang ; J.-W. Hsia ; C.-H. Wang ; J. Chen |
| Memory Read Faults: Taxonomy and Automatic Test Generation / A. Benso ; S. Di Carlo ; G. Di Natale ; P. Prinetto |
| Simulation and Development of Short Transparent Tests for RAM / S. Demidenko ; A. van de Goor ; S. Henderson ; P. Knoppers |
| Virtual Tester and Beam Testing / Session 3C： |
| Test Time Reduction through Minimum Execution of Tester-Hardware Setting Instructions / J. Hirase |
| EB-Testing-Pad Method and Its Evaluation by Actual Devices / N. Kuji ; T. Ishihara |
| Benefits of Phase Interference Detection to IC Waveform Probing / J. Block ; W. Lo ; C. Shaw |
| SoC Test Access Mechanism / Session 4A： |
| A DFT Method for Core-Based Systems-on-a-Chip Based on Consecutive Testability / T. Yoneda |
| Compaction Schemes with Minimum Test Application Time / O. Sinanoglu ; A. Orailoglu |
| Design of an Optimal Test Access Architecture Using a Genetic Algorithm / Z. Ebadi ; A. Ivanov |
| RTL ATPG / Session 4B： |
| An RT-Level ATPG Based on Clustering of Circuit States / H. Li ; Y. Min ; Z. Li |
| An Approach to RTL Fault Extraction and Test Generation / Z. Yin ; X. Li |
| Effective Techniques for High-Level ATPG / G. Cumani ; G. Squillero |
| Delay Test / Session 4C： |
| An Efficient Method to Identify Untestable Path Delay Faults / Y. Shao ; S. Kajihara |
| SpeedGrade: An RTL Path Delay Fault Simulator / K. Kim ; R. Jayabharathi ; C. Carstens |
| Test Generation for Multiple-Threshold Gate-Delay Fault Model / M. Nakao ; Y. Kiyoshige ; K. Hatayama ; T. Nagumo |
| SoC Test Scheduling / Session 5A： |
| A Gated Clock Scheme for Low Power Scan Testing of Logic ICs or Embedded Cores / Y. Bonhomme ; P. Girard ; L. Guiller ; C. Landrault ; S. Pravossoudovitch |
| Test Scheduling and Scan-Chain Division under Power Constraint / E. Larsson ; Z. Peng |
| Resource Allocation and Test Scheduling for Concurrent Test of Core-Based SoC Design / Y. Huang ; W.-T. Cheng ; C.-C. Tsai ; N. Mukherjee ; O. Samman ; Y. Zaidan |
| FSM Test / Session 5B： |
| A Unified Scheme for Designing Testable State Machines / P. Lala ; A. Walker |
| Generation of an Ordered Sequence of Test Vectors for Single State Transition Faults in Large Sequential Machines / S. Goswami ; A. Chanda ; D. Choudhury |
| Enhancing BIST Quality of Sequential Machines through Degree-of-Freedom Analysis / B. Sikdar ; S. Roy ; D. Das |
| On-line Testing and Fault Injection / Session 5C： |
| Robust Self Concurrent Test of Linear Digital Systems / E. Simeu ; A. Abdelhay ; M. Naal |
| Control-Flow Checking via Regular Expressions / L. Tagliaferri |
| FPGA-Based Fault Injection for Microprocessor Systems / P. Civera ; L. Macchiarulo ; M. Violante |
| Advances in BIST / Session 6A： |
| A BIST Method Based on Concurrent Single-Control Testability of RTL Data Paths / K. Yamaguchi ; H. Wada ; T. Masuzawa |
| Faults in Processor Control Subsystems: Testing Correctness and Performance Faults in the Data Prefetching Unit / S. Almukhaizim ; P. Petrov |
| A SmartBIST Variant with Guaranteed Encoding / B. Koenemann ; C. Barnhart ; B. Keller ; T. Snethen ; O. Farnsworth ; D. Wheater |
| Analog Test / Session 6B： |
| MEMS Comb-Actuator Resonance Measurement Method Using the 2[superscript nd] Harmonics of the GND Current / Y. Takahashi |
| On Test and Characterization of Analog Linear Time-Invariant Circuits Using Neural Networks / Z. Guo ; X. Zhang ; J. Savir ; Y.-Q. Shi |
| Specification Based Digital Compatible Built-in Test of Embedded Analog Circuits / A. Halder ; A. Chatterjee |
| Fault Tolerance / Session 6C： |
| Yield Increase of VLSI after Redundancy-Repairing |
| An Improvement in Weight-Fault Tolerance of Feedforward Neural Networks / N. Kamiura ; Y. Taniguchi ; T. Isokawa ; N. Matsui |
| A New Code-Disjoint Sum-Bit Duplicated Carry Look-Ahead Adder for Parity Codes / E. Sogomonyan |
| Various Ideas for BIST / Session 7A： |
| Selecting a PRPG: Randomness, Primitiveness, or Sheer Luck? / I. Bayraktaroglu |
| Hybrid BIST Using Partially Rotational Scan / K. Ichino ; T. Asakawa ; S. Fukumoto ; K. Iwasaki |
| Multiple Attractor Cellular Automata for Hierarchical Diagnosis of VLSI Circuits / N. Ganguly ; A. Karmakar ; S. Chowdhury ; P. Chaudhuri |
| A Microcode-Based Memory BIST Implementing Modified March Algorithm / D. Youn ; T. Kim ; S. Park |
| Fault Simulation for VHDL Based Test Bench and BIST Evaluation / H. Farshbaf ; M. Zolfy ; S. Mirkhani ; Z. Navabi |
| Analog/Mixed Signal Test / Session 7B： |
| Automatic Test Generation for Analog Circuits Using Compact Test Transfer Function Models / B. Sahu |
| Distance Constrained Dimensionality Reduction for Parametric Fault Test Generator / A. Gomes |
| Short Circuit Faults in State-of-the-Art ADCs - Are They Hard or Soft? / A. Lechner ; A. Richardson ; B. Hermes |
| An Embedded Built-in-Self-Test Approach for Digital-to-Analog Converters / J.-H. Tsai ; M.-J. Hsiao ; T.-Y. Chang |
| Verification / Session 7C： |
| An Improved AVPG Algorithm for SoC Design Verification Using Port Order Fault Model / C.-Y. Wang ; S.-W. Tung ; J.-Y. Jou |
| Framework of Timed Trace Theoretic Verification Revisited / B. Zhou ; C. Myers |
| Efficient Pattern-Based Verification of Connections to IP Cores / I. Polian ; W. Gunther ; B. Becker |
| Design Verification and Robust Design Technique for Cross-Talk Faults / B. Paul ; S.-H. Choi ; Y. Im ; K. Roy |
| DFT Application to Real Chips / Poster Session 1： |
| A Practical Logic BIST for ASIC Designs / M. Sato ; K. Tsutsumida ; T. Ikeya ; M. Kawashima |
| TX7901 DFT / T. Kamada |
| An Application of Partial Scan Techniques to a High-End System LSI Design / T. Ono ; A. Kozawa ; T. Kimura ; Y. Konno ; K. Saga |
| Built-out Self-Test (BOST) for Analog Circuits in a System LSI: Test Solution to Reduce Test Costs / H. Hanai ; S. Yamada ; H. Mori ; E. Yamashita ; T. Funakura |
| High-Speed Interface Testing / M. Suzuki ; R. Shimizu ; N. Naka ; K. Nakamura |
| A New Inter-core Built-in-Self-Test Circuits for Tri-state Buffers in the System on a Chip / T. Kishi ; M. Ohta ; T. Taniguchi ; H. Kadota |
| A Flexible Logic BIST Scheme and Its Application to SoC Designs / X. Wen |
| Practical Ideas from Universities / Poster Session 2： |
| Experimental Results of Forward-Looking Reverse Order Fault Simulation on Industrial Circuits with Scan / X. Lin |
| Non-exhaustive Parity Testing / S. Xu |
| Built-in Self-Test for State Faults Induced by Crosstalk in Sequential Circuits / K. Shimizu ; N. Itazaki |
| A Low-Power LFSR Architecture / T.-C. Huang ; K.-J. Lee |
| Author Index |
| Message from the Symposium Chair |
| Message from the Program Chair |
| Message from the 10th Anniversary Committee Chair |
| ATS 2000 Best Paper Award |
| Asian Test Committee |
| The 10th Asian Test Symposium Committee |
図書
Proceedings : 10th anniversary compendium of papers from Asian Test Symposium, 1992-2001 (: case)