Proceedings, 20th IEEE VLSI Test Symposium (VTS 2002) : 28 April-2 May 2002, Monterey, California

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Proceedings, 20th IEEE VLSI Test Symposium (VTS 2002) : 28 April-2 May 2002, Monterey, California / sponsored by IEEE Computer Society Test Technology Technical Council

資料種別:

図書

出版情報:

Los Alamitos, Calif. : IEEE Computer Society, c2002

形態:

xxxvii, 452 p. ; 28 cm

著者名:

ISBN:

9780769515700 [0769515703]

書誌ID:

BA5705997X

子書誌情報

フルテキスト

所蔵情報

他の版・巻

書誌詳細

その他の標題:

PR01570

注記:

Includes bibliographical references and index
"IEEE Computer Society Press order number PR01570" -- T. p. verso

主題:

Integrated circuits--Very large scale integration--Testing--Congresses

言語:

英語

目次情報:

Foreword

VTS 20th Anniversary Page

Acknowledgements

Organizing Committee

Steering Committee

Program Committee

Reviewers

Test Technology Technical Council

Test Technology Educational Program: Overview of Tutorials

Plenary Session

Welcome Message

Keynote Address

Program Introduction

Plenary Address: Business and Technical Challenges for Testing the Ghz Age

Microprocessor Test / Session 1：

Novel Techniques for Achieving High At-Speed Transition Fault Test Coverage for Motorola's Microprocessors Based on PowerPC Instruction Set Architecture / N. Tendolkar ; R. Raina ; R. Woltenberg ; X. Lin ; B. Swanson ; G. Aldrich

Reconfiguration Technique for Reducing Test Time and Test Data Volume in Illinois Scan Architecture Based Designs / A. Pandey ; J. Patel

Scan Islands--A Scan Partitioning Architecture and Its Implementation on the Alpha 21364 Processor / D. Bhavsar ; R. Davies

Applications of Very Low Voltage and Slow Speed Testing / Session 2：

Very Low Voltage Testing of SOI Integrated Circuits / E. MacDonald ; N. Touba

Performance Comparison of VLV, ULV, and ECR Tests / W. Jiang ; E. Peterson

Experimental Results for Slow-Speed Testing / C.-W. Tseng ; J. Li ; E. McCluskey

Innovations in Test Automation / IP Session 1：

Advancements in Scan-Based Testing / Session 3：

Scan-Path with Directly Duplicated and Inverted Duplicated Registers / M. Goessel ; A. Singh ; E. Sogomonyan

An Efficient Test Relaxation Technique for Combinational & Full-Scan Sequential Circuits / A. El-Maleh ; A. Al-Suwaiyan

Logic BIST and Scan Test Techniques for Multiple Identical Blocks / K. Arabi

Burn-in Reduction or Alternatives / Session 4：

Statistical Post-Processing at Wafersort--An Alternative to Burn-in and a Manufacturable Solution to Test Limit Setting for Sub-micron Technologies / R. Madge ; M. Rehani ; K. Cota ; W. Daasch

Yield-Reliability Modeling: Experimental Verification and Application to Burn-in Reduction / T. Barnett ; M. Grady ; K. Purdy

Evaluation of Effectiveness of Median of Absolute Deviations Outlier Rejection-Based I[subscript DDQ] Testing for Burn-in Reduction / S. Sabade ; D. Walker

DFT Testers 1 / IP Session 2：

A Successful DFT Tester: What Will It Look Like? Is Revolution in Test Approaches Required?

Test Set Compression Techniques / Session 5：

How Effective Are Compression Codes for Reducing Test Data Volume? / A. Chandra ; K. Chakrabarty ; R. Medina

Test Vector Compression Using EDA-ATE Synergies / A. Khoche ; E. Volkerink ; J. Rivoir ; S. Mitra

On Test Data Volume Reduction for Multiple Scan Chain Designs / S. Reddy ; K. Miyase ; S. Kajihara ; I. Pomeranz

Analog BIST / Session 6：

Spectrum-Based BIST in Complex SoCs / G. Kasturirangan ; M. Hsiao

A Self Calibrated ADC BIST Methodology / H.-K. Chen ; C.-H. Wang ; C.-C. Su

Self-Testing Second-Order Delta-Sigma Modulators Using Digital Stimulus / C.-K. Ong ; K.-T. Cheng

DFT Testers 2 / IP Session 3：

A Successful DFT Tester: What Will It Look Like? Is DFT Tester a Logical Next Step in ATE Evolution?

Increased Efficiency Testing / Session 7：

Testing High-Speed SoCs Using Low-Speed ATEs / M. Nourani ; J. Chin

Software-Based Weighted Random Testing for IP Cores in Bus-Based Programmable SoCs / M. Iyer

On Using Efficient Test Sequences for BIST / R. David ; P. Girard ; C. Landrault ; S. Pravossoudovitch ; A. Virazel

Controlling and Reducing Test Power / Session 8：

Controlling Peak Power during Scan Testing / R. Sankaralingam

Test Vector Modification for Power Reduction during Scan Testing / K. Ishida

Test Power Reduction through Minimization of Scan Chain Transitions / O. Sinanoglu ; I. Bayraktaroglu ; A. Orailoglu

Wireless Test / IP Session 4：

Panel / Special Session 1：

Analog & Mixed Signal BIST: Too Much, Too Little, Too Late?

Test as a Key Enabler for Faster Yield Ramp-Up / Special Session 2：

Diagnosis / Session 9：

Theorems for Efficient Identification of Indistinguishable Fault Pairs in Synchronous Sequential Circuits / M. Amyeen ; W. Fuchs

Diagnosis of Sequence-Dependent Chips

Speeding up the Byzantine Fault Diagnosis Using Symbolic Simulation / S.-Y. Huang

Analog Circuit Testing / Session 10：

Filters Designed for Testability Wrapped on the Mixed-Signal Test Bus / J. Calvano ; V. Alves ; M. Lubazewski ; A. Mesquita

Timing Jitter Measurement of 10 Gbps Bit Clock Signals Using Frequency Division / T. Yamaguchi ; M. Soma ; L. Malarsie ; M. Ishida ; H. Musha

Boosting the Accuracy of Analog Test Coverage Computation through Statistical Tolerance Analysis / S. Ozev

High Level Test Techniques / Session 11：

Instruction-Based Self-Testing of Processor Cores / N. Kranitis ; D. Gizopoulos ; A. Paschalis ; Y. Zorian

An Industrial Environment for High-Level Fault-Tolerant Structures Insertion and Validation / L. Berrojo ; F. Corno ; L. Entrena ; I. Gonzalez ; C. Lopez ; M. Sonza Reorda ; G. Squillero

Program Slicing for Hierarchical Test Generation / V. Vedula ; J. Abraham ; J. Bhadra

SoC Test Infrastructure / Session 12：

Design for Testability and Testing of IEEE 1149.1 Tap Controller / S. Makar

On Using Rectangle Packing for SoC Wrapper/TAM Co-optimization / V. Iyengar ; E. Jan Marinissen

Cluster-Based Test Architecture Design for System-on-Chip / S. Goel

Multi-GigaHertz Testing Challenges and Solutions / IP Session 5：

Test Tools and Algorithms / Session 13：

Exploiting Dominance and Equivalence Using Fault Tuples / K. Dwarakanath ; R. Blanton

Is State Mapping Essential for Equivalence Checking Custom Memories in Scan-Based Designs? / N. Krishnamurthy ; M. Abadir

RAMSES-FT: A Fault Simulator for Flash Memory Testing and Diagnostics / K.-L. Cheng ; J.-C. Yeh ; C.-W. Wang ; C.-T. Huang ; C.-W. Wu

Supply Current Testing / Session 14：

Eigen-Signatures for Regularity-Based I[subscript DDQ] Testing / Y. Okuda

Speeding-up I[subscript DDQ] Measurements / C. Thibeault

Dynamic Supply Current Testing of Analog Circuits Using Wavelet Transform / S. Bhunia ; K. Roy

IEEE P1500 in Practice / IP Session 6：

Debating the Future of Burn-In / Special Session 3：

Hot Topic / Special Session 4：

Beyond CMOS

Embedded Tutorial / Special Session 5：

Challenges of Mixed-Signal Board Design and Test / G. Roberts

Test Pattern Generation / Session 15：

A Method of Test Generation for Path Delay Faults in Balanced Sequential Circuits / S. Ohtake ; S. Miwa ; H. Fujiwara

A Test Generation Method Using a Compacted Test Table and a Test Generation Method Using a Compacted Test Plan Table for RTL Data Path Circuits / T. Hosokawa ; H. Date ; M. Muraoka

Test Pattern Generation for Signal Integrity Faults on Long Interconnects / A. Attarha

Tester Hardware Modeling and Improvements / Session 16：

Improved Test Monitor Circuit in Power Pin DfT / R. Schuttert ; F. de Jong ; B. Kup

Measuring Stray Capacitance on Tester Hardware / A. Halder ; P. Variyam ; A. Chatterjee ; J. Ridley

Power Supply Transient Signal Analysis under Real Process and Test Hardware Models / J. Plusquellic ; A. Gattiker

FPGA Test Practices / IP Session 7：

Fault Modeling & Extraction / Session 17：

Layout Analysis to Extract open Nets Caused by Systematic Failure Mechanisms / S. Chakravarty ; K. Komeyli ; E. Savage ; M. Carruthers ; B. Stastny ; S. Zachariah

Fault Models for Speed Failures Caused by Bridges and Opens / A. Jain

Timed Test Generation Crosstalk Switch Failures in Domino CMOS Circuits / R. Kundu

Memory Testing / Session 18：

Testing and Diagnosing Embedded Content Addressable Memories / J.-F. Li ; R.-S. Tzeng

Testing Static and Dynamic Faults in Random Access Memories / S. Hamdioui ; Z. Al-Ars ; Ad J. van de Goor

Approximating Infinite Dynamic Behavior for DRAM Cell Defects

IP Session 8

Validation & Test of Network Processors and ASICs

Test-Cost Reduction / Session 19：

Test Economics for Multi-site Test with Modern Cost Reduction Techniques / K. Hilliges

LI-BIST: A Low-Cost Self-Test Scheme for SoC Logic Cores and Interconnects / K. Sekar ; S. Dey

Useless Memory Allocation in System-on-a-Chip Test: Problems and Solutions / P. Gonciari ; B. Al-Hashimi ; N. Nicolici

Oscillation - Based Test / Session 20：

Practical Solutions for the Application of the Oscillation-Based-Test: Start-up and On-Chip Evaluation / D. Vazquez ; G. Huertas ; G. Leger ; A. Rueda ; J. Huertas

Evaluation of the Oscillation-Based Test Methodology for Micro-Electro-Mechanical Systems / V. Beroulle ; Y. Bertrand ; L. Latorre ; P. Nouet

Reducing Time to Volume and Time to Market: Is Silicon Debug and Diagnosis the Answer? / Special Session 6：

Challenges in Nanometric Technology Scaling: Trends and Projections / Special Session 7：

SoCs with MEMS? Can We Include MEMS in the SoCs Design and Test Flow? / Special Session 8：

Author Index

Foreword

VTS 20th Anniversary Page

Acknowledgements

Organizing Committee

Steering Committee

Program Committee

続きを見る

東工大ブックレビュー

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