Proceedings : 32nd IEEE International Symposium on Multiple-Valued Logic, May 15-18, 2002, Boston, Massachusetts, USA

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Proceedings : 32nd IEEE International Symposium on Multiple-Valued Logic, May 15-18, 2002, Boston, Massachusetts, USA / sponsored by IEEE Computer Society Technical Committee on Multiple-Valued Logic, University of Massachusetts, Boston

資料種別:

図書

出版情報:

Los Alamitos, Calif. : IEEE Computer Society, c2002

形態:

xi, 289 p. ; 28 cm

著者名:

ISBN:

9780769514628 [0769514626]

書誌ID:

BA57418256

子書誌情報

フルテキスト

所蔵情報

他の版・巻

書誌詳細

その他の標題:

ISMVL 2002
PR01462

ISSN:

0195623X

注記:

Includes bibliographical references and index
"IEEE Computer Society Order Number PR01462" -- T.p. verso

主題:

Many-valued logic--Congresses

言語:

英語

目次情報:

Message from the General Chair

Message from the Program Committee

Reviewers

Invited Talk

Equations in the Algebra of Logic / S. Rudeanu

Algebra I

Some Results on the Centralizers of Monoids in Clone Theory / H. Machida ; I. Rosenberg ; M. Miyakawa

Partial Hyperclones on a Finite Set / B. Romov

On the Structures of Weak Interlaced Bilattice / M. Kondo

Logical Design I

Improving the Characterization of p-Valued Threshold Functions / C. Moraga

A Conjunctive Canonical Expansion of Multiple-Valued Functions / E. Dubrova ; P. Farm

Sierpinski Gaskets for Logic Functions Representation / D. Popel ; A. Dani

Logic for Static Hazard Detection of Multiple-Valued Logic Circuits with Tsum, Min, and Literals / N. Takagi ; K. Nakashima

Circuits I

Multiple-Valued Data Recovery Techniques for Band-Limited Channels in VLSI / Y. Yuminaka ; T. Morishita ; T. Aoki ; T. Higuchi

An Impact of Introducing Multi-Level Signals to a Bandpass Cascaded Delta-Sigma Modulator / T. Waho ; S. Kobayashi ; K. Matsuura

Voltage Comparator Circuits for Multiple-Valued CMOS Logic / Y. Guo ; K. Current

Logical Design II

Efficient Calculation of Fixed-Polarity Polynomial Expressions for Multiple-Valued Logic Functions / D. Jankovic ; R. Stankovic ; R. Drechsler

Comparison of Different Features of Quaternary Reed-Muller Canonical Forms and Some New Statistical Results / K. Adams ; J. McGregor

Design and Implementation of Error Detection and Correction Circuitry for Multilevel Memory Protection / B. Polianskikh ; Z. Zilic

Parallel Evolutionary Graph Synthesis on a PC Cluster and Its Application to Multiple-Valued Circuit Synthesis / M. Natsui

Consequence and Complexity in Infinite-Valued Logic: A Survey / V. Marra ; D. Mundici

Spectral Techniques

Some Remarks on Linear Transform of Variables in Representation of Adders by Word-Level Expressions and Spectral Transform Decision Diagrams / J. Astola

Chrestenson Spectrum Computation Using Cayley Color Graphs / M. Thornton ; D. Miller ; W. Townsend

The Role of Super-Fast Transforms in Speeding Up Quantum Computations / K. Radecka

Multiple-Valued and Spectral Approach to Lossless Compression of Binary, Gray Scale and Color Biomedical Images / B. Falkowski ; B. Olejnicka

Circuits II

Design of Dynamic Reliability Indices / E. Zaitseva ; V. Levashenko

PODEM Based on Static Testability Measures and Dynamic Testability Measures for Multiple-Valued Logic Circuits / N. Kamiura ; T. Isokawa ; N. Matsui

Design of Ternary Schmitt Triggers Based on Its Sequential Characteristics / X. Wu ; P. Wang ; Y. Xia

Multiple-Valued Logic-in-Memory VLSI Based on Ferroelectric Capacitor Storage and Charge Addition / H. Kimura ; T. Hanyu ; M. Kameyama

Optimization of Multi-Valued Multi-Level Networks / M. Gao ; J. Jiang ; Y. Jiang ; Y. Li ; A. Mishchenko ; S. Sinha ; T. Villa ; R. Brayton

Algebra II

de Morgan Bisemilattice of Fuzzy Truth Value / H. Kikuchi

Independence of Each Axiom in a Set of Axioms and Complete Sets of Axioms of Boolean Algebra / T. Ninomiya ; M. Mukaidono

On Functions Defined on Free Boolean Algebras / D. Simovici ; S. Jaroszewicz

Logical Design III

The Word-Level Models for Efficient Computation of Multiple-Valued Functions. Part 1: LAR Based Model / S. Yanushkevich ; P. Dziurzanski ; V. Shmerko

The Word-Level Models for Efficient Computation of Multiple-Valued Functions. Part 2: LWL Based Model / A. Tomaszewska

Efficient Bridging Fault Simulation of Sequential Circuits Based on Multi-Valued Logics / I. Polian ; P. Engelke ; B. Becker

Multiple-Valued-Digit Number Representations in Arithmetic Circuit Algorithms

Decision Diagrams

Variable Selection Heuristics and Optimum Decision Trees--An Experimental Study / N. Otsu

On the Construction of Multiple-Valued Decision Diagrams

Evaluation of Static Variable Ordering Heuristics for MDD Construction

Representations of Logic Functions Using QRMDDs / S. Nagayama ; T. Sasao ; Y. Iguchi ; M. Matsuura

Circuits III

Fully Source-Coupled Logic Based Multiple-Valued VLSI / T. Ike

A Current-Mode Folding/Interpolating CMOS Analog to Quaternary Converter Using Binary to Quaternary Encoding Block / S. Han ; S. Park ; H. Seong ; H. Kim

Multi-Valued Flip-Flop with Neuron-CMOS NMIN Circuits / M. Inaba ; K. Tanno ; O. Ishizuka

Author Index

Message from the General Chair

Message from the Program Committee

Reviewers

Invited Talk

Equations in the Algebra of Logic / S. Rudeanu

Algebra I

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