| General Co-Chairs' Message |
| Program Chair's Message |
| Committees |
| Reviewers |
| Keynote 1 |
| Computer Architecture: Challenges and Opportunities for the Next Decade / Tilak Agerwala |
| Architecture Evaluations / Session 1： |
| Evaluation of the Raw Microprocessor: An Exposed-Wire-Delay Architecture for ILP and Streams / M. Taylor ; W. Lee ; J. Miller ; D. Wentzlaff ; B. Greenwald ; V. Strumpen ; N. Shnidman ; I. Bratt ; H. Hoffmann ; P. Johnson ; J. Kim ; A. Saraf ; J. Psota ; M. Frank|cS. Amarasinghe ; A. Agarwal |
| Evaluating the Imagine Stream Architecture / J. Ahn ; W. Dally ; B. Khailany ; U. Kapasi ; A. Das |
| Field-testing IMPACT EPIC Research Results in Itanium 2 / J. Sias ; S. Ueng ; G. Kent ; I. Steiner ; E. Nystrom ; W. Hwu |
| Parallelism in Microarchitectures / Session 2A： |
| Wire Delay is Not a Problem for SMT (In the Near Future) / Z. Chishti ; T. Vijaykumar |
| The Vector-Thread Architecture / R. Krashinsky ; C. Batten ; S. Gerding ; M. Hampton ; B. Pharris ; J. Casper ; K. Asanovic |
| Single-ISA Heterogeneous Multi-Core Architectures for Multithreaded Workload Performance / R. Kumar ; D. Tullsen ; P. Ranganathan ; N. Jouppi ; K. Farkas |
| Microarchitecture Optimizations for Exploiting Memory-Level Parallelism / Y. Chou ; B. Fahs ; S. Abraham |
| Memory Consistency / Session 2B： |
| Memory Ordering: A Value-Based Approach / H. Cain ; M. Lipasti |
| Transactional Memory Coherence and Consistency / L. Hammond ; V. Wong ; M. Chen ; B. Hertzberg ; J. Davis ; B. Carlstrom ; M. Prabhu ; H. Wijaya ; C. Kozyrakis ; K. Olukotun |
| TSOtool: A Program for Verifying Memory Systems Using the Memory Consistency Model / S. Hangal ; D. Vahia ; C. Manovit ; J. Lu ; S. Narayanan |
| SMTp: An Architecture for Next-generation Scalable Multi-threading / M. Chaudhuri ; M. Heinrich |
| Panel: Supporting ILP in Tiled Architectures: Wasted Effort, or a Good Idea? |
| Keynote 2 |
| High Performance Throughput Computing / Marc Tremblay ; Sun Microsystems |
| Power and Energy / Session 3： |
| A Formal Approach to Frequent Energy Adaptations for Multimedia Applications / C. Hughes ; S. Adve |
| Synchroscalar: A Multiple Clock Domain, Power-Aware, Tile-Based Embedded Processor / J. Oliver ; R. Rao ; P. Sultana ; J. Crandall ; E. Czernikowski ; L. Jones ; D. Franklin ; V. Akella ; F. Chong |
| Power Awareness through Selective Dynamically Optimized Traces / R. Rosner ; Y. Almog ; M. Moffie ; N. Schwartz ; A. Mendelson |
| Interconnect and I/O / Session 3B： |
| X-RAY: A Non-Invasive Exclusive Caching Mechanism for RAIDs / L. Bairavasundaram ; M. Sivathanu ; A. Arpaci-Dusseau ; R. Arpaci-Dusseau |
| Low-Latency Virtual-Channel Routers for On-Chip Networks / R. Mullins ; A. West ; S. Moore |
| Immunet: A Cheap and Robust Fault-Tolerant Packet Routing Mechanism / V. Puente ; J. Gregorio ; F. Vallejo ; R. Beivide |
| Compression and Debugging / Session 4A： |
| Adaptive Cache Compression for High-Performance Processors / A. Alameldeen ; D. Wood |
| iWatcher: Efficient Architectural Support for Software Debugging / P. Zhou ; F. Qin ; W. Liu ; Y. Zhou ; J. Torrellas |
| Superscalars / Session 4B： |
| From Sequences of Dependent Instructions to Functions: An Approach for Improving Performance without ILP or Speculation / S. Yehia ; O. Temam |
| Prophet/Critic Hybrid Branch Prediction / A. Falcon ; J. Stark ; A. Ramirez ; K. Lai ; M. Valero |
| Support for Reliability / Session 5A： |
| Techniques to Reduce the Soft Error Rate of a High-Performance Microprocessor / C. Weaver ; J. Emer ; S. Mukherjee ; S. Reinhardt |
| The Case for Lifetime Reliability-Aware Microprocessors / J. Srinivasan ; P. Bose ; J. Rivers |
| Exploiting Resonant Behavior to Reduce Inductive Noise / M. Powell |
| Register File / Session 5B： |
| Use-Based Register Caching with Decoupled Indexing / J. Butts ; G. Sohi |
| A Content Aware Integer File Organization / R. Gonzalez ; A. Cristal ; D. Ortega ; A. Veidenbaum |
| Physical Register Inlining / B. Mestan ; E. Gunadi |
| Performance Methodologies / Session 6A： |
| A First-Order Superscalar Processor Model / T. Karkhanis ; J. Smith |
| Control Flow Modeling in Statistical Simulation for Accurate and Efficient Processor Design Studies / L. Eckhout ; R. Bell ; B. Stougie ; K. De Bosschere ; L. John |
| Microarchitectural Concepts / Session 6B： |
| Extended Split-Issue: Enabling Flexibility in the Hardware Implementation of NUAL VLIW DSPs / B. Iyer ; S. Srinivasan ; B. Jacob |
| A Complexity-Effective Approach to ALU Bandwidth Enhancement for Instruction-Level Temporal Redundancy / A. Parashar ; S. Gurumurthi ; A. Sivasubramaniam |
| Author Index |
| General Co-Chairs' Message |
| Program Chair's Message |
| Committees |
| Reviewers |
| Keynote 1 |
| Computer Architecture: Challenges and Opportunities for the Next Decade / Tilak Agerwala |
