| Welcome Letter |
| Organizing Committee |
| Program Committee |
| Additional Reviewers |
| Keynote Addresses |
| Gigascale System Design--Challenges and Opportunities / S. Borkar |
| Error Tolerance / M. Breuer |
| Digital Integrated Circuit Testing for Art Historians and Test Experts / E. McCluskey |
| High-Speed and Energy-Efficient Circuit Design / Session 1： |
| PCAM: A Ternary CAM Optimized for Longest Prefix Matching Tasks / M. Akhbarizadeh ; M. Nourani ; D. Vijayasarathi ; P. Balsara |
| Area and Energy-Efficient Crosstalk Avoidance Codes for On-Chip Buses / S. Sridhara ; A. Ahmed ; N. Shanbhag |
| An Area- and Energy-Efficient Asynchronous Booth Multiplier for Mobile Devices / J. Hensley ; A. Lastra ; M. Singh |
| A High-Frequency Decimal Multiplier / R. Kenney ; M. Schulte ; M. Erle |
| An Efficient Twin-Precision Multiplier / M. Sjalander ; H. Eriksson ; P. Larsson-Edefors |
| Energy-Efficient Processor Microarchitecture (1) / Session 1.2： |
| Defining Wakeup Width for Efficient Dynamic Scheduling / A. Aggarwal ; M. Franklin ; O. Ergin |
| Power-Aware Deterministic Block Allocation for Low-Power Way-Selective Cache Structure / J.-W. Park ; G.-H. Park ; S.-B. Park ; S.-D. Kim |
| Thermal-Aware Clustered Microarchitectures / P. Chaparro ; J. Gonzalez ; A. Gonzalez |
| Reducing Issue Queue Power for Multimedia Applications Using a Feedback Control Algorithm / Y. Bai ; R. Bahar |
| Scan Design and Test / Session 1.3： |
| A Novel Low-Power Scan Design Technique Using Supply Gating / S. Bhunia ; H. Mahmoodi ; S. Mukhopadhyay ; D. Ghosh ; K. Roy |
| Asynchronous Scan-Latch Controller for Low Area Overhead DFT / M. Tsukisaka ; M. Imai ; T. Nanya |
| End-to-End Testability Analysis and DfT Insertion for Mixed-Signal Paths / S. Ozev ; A. Orailoglu |
| Functional Illinois Scan Design at RTL / H. Ko ; N. Nicolici |
| On Undetectable Faults in Partial Scan Circuits Using Transparent-Scan / I. Pomeranz ; S. Reddy |
| Routing and Floorplanning / Session 2： |
| A Depth-First-Search Controlled Gridless Incremental Routing Algorithm for VLSI Circuits / H. Arslan ; S. Dutt |
| Simultaneous Shield and Buffer Insertion for Crosstalk Noise Reduction in Global Routing / T. Zhang ; S. Sapatnekar |
| A Two-Layer Bus Routing Algorithm for High-Speed Boards / M. Ozdal ; M. Wong |
| Reticle Floorplanning with Guaranteed Yield for Multi-Project Wafers / A. Kahng ; S. Reda |
| Formal Verification Embedded Tutorial / Session 2.2： |
| Fine-Grain Abstraction and Sequential Don't Cares for Large Scale Model Checking / C. Wang ; G. Hachtel ; F. Somenzi |
| Comparative Study of Strategies for Formal Verification of High-Level Processors / M. Velev |
| Signal Integrity and Leakage / Session 2.3： |
| A Highly-Efficient Technique for Reducing Soft Errors in Static CMOS Circuits / S. Krishnamohan ; N. Mahapatra |
| A Signal Integrity Test Bed for PCB Buses / J. Ren ; M. Greenstreet |
| A New Threshold Voltage Assignment Scheme for Runtime Leakage Reduction in On-Chip Repeaters / S. Shah ; K. Agarwal ; D. Sylvester |
| A General Post-Processing Approach to Leakage Current Reduction in SRAM-Based FPGAs / J. Lach ; J. Brandon ; K. Skadron |
| Special Session on High-Performance On-Chip Communication / Session 3： |
| Design Methodologies and Architecture Solutions for High-Performance Interconnects (Invited Paper) / D. Pandini ; C. Forzan ; L. Baldi |
| On-Chip Transparent Wire Pipelining (Invited Paper) / M. Casu ; L. Macchiarulo |
| Toward an Integrated Design Methodology for Fault-Tolerant, Multiple Clock/Voltage Integrated Systems (Invited Paper) / R. Marculescu ; D. Marculescu ; L. Pileggi |
| Network-on-Chip: The Intelligence is in the Wire (Invited Paper) / G. Mas ; P. Martin |
| Test Generation and Characterization / Session 3.2： |
| Low Power Test Data Compression Based on LFSR Reseeding / J. Lee ; N. Touba |
| An Infrastructure IP for On-Chip Clock Jitter Measurement / J.-J. Huang ; J.-L. Huang |
| Diagnosis of Hold Time Defects / Z. Wang ; M. Marek-Sadowska ; K.-H. Tsai ; J. Rajski |
| Extending the Applicability of Parallel-Serial Scan Designs / B. Arslan ; O. Sinanoglu |
| Quality Improvement Methods for System-Level Stimuli Generation / R. Emek ; I. Jaeger ; Y. Katz ; Y. Naveh |
| Physically-Aware Design Tools / Session 3.3： |
| XTalkDelay: A Crosstalk-Aware Timing Analysis Tool for Chip-Level Designs / Y. Li ; R. Murgai ; T. Miyoshi ; A. Verma |
| A Flexible Data Structure for Efficient Buffer Insertion / R. Chen ; H. Zhou |
| Simultaneous Scheduling, Binding and Layer Assignment for Synthesis of Vertically Integrated 3D Systems / M. Mukherjee ; R. Vemuri |
| Transistor and Pin Reordering for Gate Oxide Leakage Reduction in Dual T[subscript ox] Circuits / A. Sultania |
| Energy-Efficient Processor Microarchitecture (2) / Session 4： |
| Best of Both Latency and Throughput / E. Grochowski ; R. Ronen ; J. Shen ; H. Wang |
| Fetch Halting on Critical Load Misses / N. Mehta ; B. Singer ; M. Leuchtenburg ; R. Weiss |
| Frontend Frequency-Voltage Adaptation for Optimal Energy-Delay[superscript 2] / G. Magklis |
| Power and Timing Optimization / Session 4.2： |
| Gate Sizing and V[subscript t] Assignment for Active-Mode Leakage Power Reduction / F. Gao ; J. Hayes |
| Potential Slack Budgeting with Clock Skew Optimization / K. Wang |
| A New Statistical Optimization Algorithm for Gate Sizing / M. Mani ; M. Orshansky |
| Novel Processor Design / Session 4.3： |
| An Architecture for Fast Processing of Large Unstructured Data Sets / R. Chamberlain ; M. Henrichs ; B. Shands ; J. White |
| In-System FPGA Prototyping of an Itanium Microarchitecture / R. Wunderlich ; J. Hoe |
| Adaptive Selection of an Index in a Texture Cache / C.-H. Kim ; L.-S. Kim |
| Emerging Technologies Special Session / Session 5： |
| Using Circuits and Systems-Level Research to Drive Nanotechnology (Invited Paper) / M. Niemier ; R. Ravichandran ; P. Kogge |
| FPGA Emulation of Quantum Circuits / A. Khalid ; Z. Zilic ; K. Radecka |
| 3D Processing Technology and Its Impact on iA32 Microprocessors (Invited Paper) / B. Black ; D. Nelson ; C. Webb ; N. Samra |
| Cache Memory Design / Session 5.2： |
| Cache Array Architecture Optimization at Deep Submicron Technologies / A. Zeng ; K. Rose ; R. Gutmann |
| Implementation of Fine-Grained Cache Monitoring for Improved SMT Scheduling / J. Kihm ; D. Connors |
| Low Energy, Highly-Associative Cache Design for Embedded Processors / A. Veidenbaum ; D. Nicolaescu |
| Layout-Driven Circuit Optimization / Session 6： |
| The Magic of a Via-Configurable Regular Fabric / Y. Ran |
| A Fast Delay Analysis Algorithm for the Hybrid Structured Clock Network / Y. Zou ; Y. Cai ; Q. Zhou ; X. Hong ; S. Tan |
| Layout Driven Optimization of Datapath Circuits Using Arithmetic Reasoning / I. Neumann ; D. Stoffel ; K. Sulimma ; M. Berkelaar ; W. Kunz |
| Floorplan-Aware Low-Complexity Digital Filter Synthesis for Low-Power and High-Speed / D. Kang ; H. Choo |
| Instruction-Level Parallelism (1) / Session 6.2： |
| A Minimal Dual-Core Speculative Multi-Threading Architecture / S. Srinivasan ; H. Akkary ; T. Holman ; K. Lai |
| Exploiting Quiescent States in Register Lifetime / R. Sangireddy ; A. Somani |
| Evaluating Techniques for Exploiting Instruction Slack / Y. Chin ; J. Sheu ; D. Brooks |
| Power Estimation and Minimization / Session 6.3： |
| Static Transition Probability Analysis under Uncertainty / S. Garg ; S. Tata ; R. Arunachalam |
| Circuit-Based Preprocessing of ILP and Its Applications in Leakage Minimization and Power Estimation / D. Chai ; A. Kuehlmann |
| Analyzing Power Consumption of Message Passing Primitives in a Single-Chip Multiprocessor / M. Loghi ; L. Benini ; M. Poncino |
| An Architectural Power Estimator for Analog-to-Digital Converters / Z. Huang ; P. Zhong |
| Formal Verification Techniques / Session 7： |
| Formal Hardware Verification Based on Signal Correlation Properties--A PVS Library for Redundant Number Representation / N. Kikkeri ; P.-M. Seidel |
| Generating Monitor Circuits for Simulation-Friendly GSTE Assertion Graphs / K. Ng ; A. Hu ; J. Yang |
| Graph Automorphism-Based Algorithm for Determining Symmetric Inputs / C.-L. Chou ; C.-Y. Wang ; G.-W. Lee ; J.-Y. Jou |
| Networks on Chips / Session 7.2： |
| Linear Programming Based Techniques for Synthesis of Network-on-Chip Architectures / K. Srinivasan ; K. Chatha ; G. Konjevod |
| Thermal-Aware IP Virtualization and Placement for Networks-on-Chip Architecture / W. Hung ; C. Addo-Quaye ; T. Theocharides ; Y. Xie ; N. Vijaykrishnan ; M. Irwin |
| Many-to-Many Core-Switch Mapping in 2-D Mesh NoC Architectures / C.-E. Rhee ; H.-Y. Jeong ; S. Ha |
| Novel Processor Architecture / Session 7.3： |
| An Embedded Reconfigurable SIMD DSP with Capability of Dimension-Controllable Vector Processing / L. Han ; J. Chen ; C. Zhou ; X. Zhang ; Z. Liu ; X. Wei ; B. Li |
| Runtime Execution Monitoring (REM) to Detect and Prevent Malicious Code Execution / A. Fiskiran ; R. Lee |
| Dynamic Address Compression Schemes: A Performance, Energy, and Cost Study / J. Liu ; K. Sundaresan |
| Instruction-Level Parallelism (2) / Session 8： |
| Compiler-Based Frame Formation for Static Optimization / F. Shi ; S. Almukhaizam ; P.-C. Lin ; Y. Makris |
| IPC Driven Dynamic Associative Cache Architecture for Low Energy / S. Nadathur ; A. Tyagi |
| Increasing Processor Performance through Early Register Release / D. Balkan ; D. Ponomarev ; K. Ghose |
| Topics in Synthesis and Co-Simulation / Session 8.2： |
| Combined Channel Segmentation and Buffer Insertion for Routability and Performance Improvement of Field Programmable Analog Arrays / H. Huang ; J. Bernstein ; M. Peckerar ; J. Luo |
| Software/Network Co-Simulation of Heterogeneous Industrial Networks Architectures / F. Fummi ; S. Martini ; M. Monguzzi ; G. Perbellini |
| Hardware/Software Co-Modeling of SAT Solver Based on Distributed Computing Elements Using SystemC / J. Xi |
| Coping with the Variability of Combinational Logic Delays / J. Cortadella ; A. Kondratyev ; L. Lavagno ; C. Sotiriou |
| Low-Power Architecture / Session 8.3： |
| Design-Space Exploration of Power-Aware On/Off Interconnection Networks / V. Soteriou ; L.-S. Peh |
| Energy Characterization of Hardware-Based Data Prefetching / Y. Guo ; S. Chheda ; I. Koren ; C. Krishna ; C. Moritz |
| Design and Implementation of Scalable Low-Power Montgomery Multiplier / H.-K. Son ; S.-G. Oh |
| Test Generation / Session 9： |
| Compressed Embedded Diagnosis of Logic Cores / S. Ollivierre ; A. Kinsman |
| An Automatic Test Pattern Generation Framework for Combinational Threshold Logic Networks / P. Gupta ; R. Zhang ; N. Jha |
| An Efficient Algorithm for Reconfiguring Shared Spare RRAM / H.-Y. Lin ; H.-Z. Chou ; F.-M. Yeh ; I.-Y. Chen ; S.-Y. Kuo |
| Network Routing / Session 9.2： |
| An Accurate Combinatorial Model for Performance Prediction of Deterministic Wormhole Routing in Torus Multicomputer Systems / H. Najaf-abadi ; H. Sarbazi-azad |
| Technique to Eliminate Sorting in IP Packet Forwarding Devices / R. Baldwin ; E. Ng |
| Placement and Floorplanning / Session 9.3： |
| I/O Clustering in Design Cost and Performance Optimization for Flip-Chip Design / H.-M. Chen ; I.-M. Liu ; M. Shao ; L.-D. Huang |
| Placement with Alignment and Performance Constraints Using the B*-Tree Representation / M.-C. Wu ; Y.-W. Chang |
| ACG-Adjacent Constraint Graph for General Floorplans / J. Wang |
| Author Index |
| Welcome Letter |
| Organizing Committee |
| Program Committee |
| Additional Reviewers |
| Keynote Addresses |
| Gigascale System Design--Challenges and Opportunities / S. Borkar |
