| Message from the General Chair |
| Message from the Program Chair |
| Committees |
| Reviewers |
| Keynote 1 |
| Microarchitecture on the MOSFET Diet / Kerry Bernstein |
| Voltage Scaling and Transient Faults / Session 1： |
| Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation / D. Ernst ; N. S. Kim ; S. Das ; S. Pant ; R. Rao ; T. Pham ; C. Ziesler ; D. Blaauw ; T. Austin ; K. Flautner ; T. Mudge |
| VSV: L2-Miss-Driven Variable Supply-Voltage Scaling for Low Power / H. Li ; C.-Y. Cher ; T. N. Vijaykumar ; K. Roy |
| A Systematic Methodology to Compute the Architectural Vulnerability Factors for a High-Performance Microprocessor / S. S. Mukherjee ; C. Weaver ; J. Emer ; S. K. Reinhardt |
| Cache Design / Session 2： |
| TLC: Transmission Line Caches / B. M. Beckmann ; D. A. Wood |
| Distance Associativity for High-Performance Energy-Efficient Non-Uniform Cache Architectures / Z. Chishti ; M. D. Powell |
| Near-Optimal Precharging in High-Performance Nanoscale CMOS Caches / S.-H. Yang ; B. Falsafi |
| Power and Energy Efficient Architectures / Session 3： |
| Single-ISA Heterogeneous Multi-Core Architectures: The Potential for Processor Power Reduction / R. Kumar ; K. I. Farkas ; N. P. Jouppi ; P. Ranganathan ; D. M. Tullsen |
| Runtime Power Monitoring in High-End Processors: Methodology and Empirical Data / C. Isci ; M. Martonosi |
| Power-Driven Design of Router Microarchitectures in On-Chip Networks / H. Wang ; L.-S. Peh ; S. Malik |
| Optimum Power/Performance Pipeline Depth / A. Hartstein ; T. R. Puzak |
| Application Specific Optimization and Analysis / Session 4： |
| Processor Acceleration through Automated Instruction Set Customization / N. Clark ; H. Zhong ; S. Mahlke |
| The Reconfigurable Streaming Vector Processor (RSVP) / S. Ciricescu ; R. Essick ; B. Lucas ; P. May ; K. Moat ; J. Norris ; M. Schuette ; A. Saidi |
| Scaling and Characterizing Database Workloads: Bridging the Gap between Research and Practice / R. Hankins ; T. Diep ; M. Annavaram ; B. Hirano ; H. Eri ; H. Nueckel ; J. P. Shen |
| Keynote 2 |
| In Memory of Bob Rau / Michael Schlansker |
| Dynamic Optimization Systems / Session 5： |
| Generational Cache Management of Code Traces in Dynamic Optimization Systems / K. Hazelwood ; M. D. Smith |
| The Performance of Runtime Data Cache Prefetching in a Dynamic Optimization System / J. Lu ; H. Chen ; R. Fu ; W.-C. Hsu ; B. Othmer ; P.-C. Yew ; D.-Y. Chen |
| IA-32 Execution Layer: A Two-Phase Dynamic Translator Designed to Support IA-32 Applications on Itanium-Based Systems / L. Baraz ; T. Devor ; O. Etzion ; S. Goldenberg ; A. Skaletsky ; Y. Wang ; Y. Zemach |
| Dynamic Program Analysis and Optimization / Session 6： |
| LLVA: A Low-Level Virtual Instruction Set Architecture / V. Adve ; C. Lattner ; M. Brukman ; A. Shukla ; B. Gaeke |
| Comparing Program Phase Detection Techniques / A. S. Dhodapkar ; J. E. Smith |
| Using Interaction Costs for Microarchitectural Bottleneck Analysis / B. A. Fields ; R. Bodik ; M. D. Hill ; C. J. Newburn |
| Branch, Value and Scheduling Optimizations / Session 7： |
| Fast Path-Based Neural Branch Prediction / D. A. Jimenez |
| Hardware Support for Control Transfers in Code Caches / H.-S. Kim |
| Exploiting Value Locality in Physical Register Files / S. Balakrishnan ; G. S. Sohi |
| Macro-op Scheduling: Relaxing Scheduling Loop Constraints / I. Kim ; M. H. Lipasti |
| Dataflow, Data Parallel, and Clustered Architectures / Session 8： |
| WaveScalar / S. Swanson ; K. Michelson ; A. Schwerin ; M. Oskin |
| Universal Mechanisms for Data-Parallel Architectures / K. Sankaralingam ; S. W. Keckler ; W. R. Mark ; D. Burger |
| Flexible Compiler-Managed L0 Buffers for Clustered VLIW Processors / E. Gibert ; J. Sanchez ; A. Gonzalez |
| Instruction Replication for Clustered Microarchitectures / A. Aleta ; J. M. Codina ; D. Kaeli |
| Secure and Network Processors / Session 9： |
| Efficient Memory Integrity Verification and Encryption for Secure Processors / G. E. Suh ; D. Clarke ; B. Gassend ; M. van Dijk ; S. Devadas |
| Fast Secure Processor for Inhibiting Software Piracy and Tampering / J. Yang ; Y. Zhang ; L. Gao |
| IPStash: A Power-Efficient Memory Architecture for IP-Lookup / S. Kaxiras ; G. Keramidas |
| Design and Implementation of High-Performance Memory Systems for Future Packet Buffers / J. Garcia ; J. Corbal ; L. Cerda ; M. Valero |
| Scaling Design / Session 10： |
| Beating In-Order Stalls with "Flea-Flicker" Two-Pass Pipelining / R. D. Barnes ; E. M. Nystrom ; J. W. Sias ; S. J. Patel ; N. Navarro ; W. W. Hwu |
| Scalable Hardware Memory Disambiguation for High ILP Processors / S. Sethumadhavan ; R. Desikan ; C. R. Moore |
| Reducing Design Complexity of the Load/Store Queue / I. Park ; C. L. Ooi |
| Checkpoint Processing and Recovery: Towards Scalable Large Instruction Window Processors / H. Akkary ; R. Rajwar ; S. T. Srinivasan |
| Author Index |
| Message from the General Chair |
| Message from the Program Chair |
| Committees |
| Reviewers |
| Keynote 1 |
| Microarchitecture on the MOSFET Diet / Kerry Bernstein |
