Compilation Techniques for Reconfigurable Architectures

Compilation Techniques for Reconfigurable Architectures / João M.P Cardoso, João M.P Cardoso, Pedro C. Diniz, F. Melchers, M. Potter

資料種別:

電子ブック

出版情報:

SpringerLink Books - AutoHoldings
Springer US, 2009

著者名:

ISBN:

9780387096704 [0387096701]
9786611953812 [6611953817]
9781441935106 [144193510X]

書誌ID:

OB00489681

子書誌情報

フルテキスト

所蔵情報

書誌詳細

言語:

英語

目次情報:

Introduction / 1：

The Promise of Reconfigurable Architectures and Systems / 1.1：

The Challenge: How to Program and Compile for Reconfigurable Systems? / 1.2：

This Book: Key Techniques when Compiling to Reconfigurable Architecture / 1.3：

Organization of this Book / 1.4：

Overview of Reconfigurable Architectures / 2：

Evolution of Reconfigurable Architectures / 2.1：

Reconfigurable Architectures: Key Characteristics / 2.2：

Granularity / 2.3：

Fine-Grained Reconfigurable Architectures / 2.3.1：

Coarse-Grained Reconfigurable Architectures / 2.3.2：

Hybrid Reconfigurable Architectures / 2.3.3：

Granularity and Mapping / 2.3.4：

Interconnection Topologies / 2.4：

System-Level Integration / 2.5：

Dynamic Reconfiguration / 2.6：

Computational and Execution Models / 2.7：

Streaming Data Input and Output / 2.8：

Summary / 2.9：

Compilation and Synthesis Flows / 3：

Overview / 3.1：

Front-End / 3.1.1：

Middle-End / 3.1.2：

Back-End / 3.1.3：

Hardware Compilation and High-Level Synthesis / 3.2：

Generic High-Level Synthesis / 3.2.1：

Customized High-Level Synthesis for Fine-Grained Reconfigurable Architectures / 3.2.2：

High-Level Compilation for Coarse-Grained Reconfigurable Architectures / 3.2.4：

Placement and Routing / 3.2.5：

Illustrative Example / 3.3：

High-Level Source Code Example / 3.3.1：

Data-Flow Representation / 3.3.2：

Computation-Oriented Mapping and Scheduling / 3.3.3：

Data-Oriented Mapping and Transformations / 3.3.4：

Translation to Hardware / 3.3.5：

Reconfigurable Computing Issues and Their Impact on Compilation / 3.4：

Programming Languages and Execution Models / 3.4.1：

Intermediate Representations / 3.4.2：

Target Reconfigurable Architecture Features / 3.4.3：

Code Transformations / 3.5：

Bit-Level Transformations / 4.1：

Bit-Width Narrowing / 4.1.1：

Bit-Level Optimizations / 4.1.2：

Conversion from Floating- to Fixed-Point Representations / 4.1.3：

Nonstandard Floating-Point Formats / 4.1.4：

Instruction-Level Transformations / 4.2：

Operator Strength Reduction / 4.2.1：

Height Reduction / 4.2.2：

Code Motion / 4.2.3：

Loop-Level Transformations / 4.3：

Loop Unrolling / 4.3.1：

Loop Tiling and Loop Strip-Mining / 4.3.2：

Loop Merging and Loop Distribution / 4.3.3：

Data-Oriented Transformations / 4.4：

Data Distribution / 4.4.1：

Data Replication / 4.4.2：

Data Reuse and Scalar Replacement in Registers and Internal RAMs / 4.4.3：

Other Data-Oriented Transformations / 4.4.4：

Function-Oriented Transformations / 4.5：

Function Inlining and Outlining / 4.5.1：

Recursive Functions / 4.5.2：

Which Code Transformations to Choose? / 4.6：

Mapping and Execution Optimizations / 4.7：

Hardware Execution Techniques / 5.1：

Instruction-Level Parallelism / 5.1.1：

Speculative Execution / 5.1.2：

Predication and if-conversion / 5.1.3：

Multi Tasking / 5.1.4：

Partitioning / 5.2：

Temporal Partitioning / 5.2.1：

Spatial Partitioning / 5.2.2：

Mapping Program Constructs to Resources / 5.2.3：

Mapping Scalar Variables to Registers / 5.3.1：

Mapping of Operations to FUs / 5.3.2：

Mapping of Selection Structures / 5.3.3：

Sharing Functional Units FUs / 5.3.4：

Combining Instructions for RFUs / 5.3.5：

Pipelining / 5.4：

Pipelined Functional and Execution Units / 5.4.1：

Pipelining Memory Accesses / 5.4.2：

Loop Pipelining / 5.4.3：

Coarse-Grained Pipelining / 5.4.4：

Pipelining Configuration-Computation Sequences / 5.4.5：

Memory Accesses / 5.5：

Partitioning and Mapping of Arrays to Memory Resources / 5.5.1：

Improving Memory Accesses / 5.5.2：

Back-End Support / 5.6：

Allocation, Scheduling, and Binding / 5.6.1：

Module Generation / 5.6.2：

Mapping, Placement, and Routing / 5.6.3：

Compilers for Reconfigurable Architectures / 5.7：

Early Compilation Efforts / 6.1：

Compilers for FPGA-Based Systems / 6.2：

The SPC Compiler / 6.2.1：

A C to Fine-Grained Pipelining Compiler / 6.2.2：

The DeepC Silicon Compiler / 6.2.3：

The COBRA-ABS Tool / 6.2.4：

The DEFACTO Compiler / 6.2.5：

The Streams-C Compiler / 6.2.6：

The Cameron Compiler / 6.2.7：

The MATCH Compiler / 6.2.8：

The Galadriel and Nenya Compilers / 6.2.9：

The Sea Cucumber Compiler / 6.2.10：

The Abstract-Machines Compiler / 6.2.11：

The CHAMPION Software Design Environment / 6.2.12：

The SPARCS Tool / 6.2.13：

The ROCCC Compiler / 6.2.14：

The DWARV Compiler / 6.2.15：

Compilers for Coarse-Grained Reconfigurable Architectures / 6.3：

The DIL Compiler / 6.3.1：

The RaPiD-C Compiler / 6.3.2：

The CoDe-X Compiler / 6.3.3：

The XPP-VC Compiler / 6.3.4：

The DRESC Compiler / 6.3.5：

Compilers for Hybrid Reconfigurable Architectures / 6.4：

The Chimaera-C Compiler / 6.4.1：

The Garp and the Nimble C Compilers / 6.4.2：

The NAPA-C Compiler / 6.4.3：

Compilation Efforts Summary / 6.5：

Perspectives on Programming Reconfigurable Computing Platforms / 7：

How to Make Reconfigurable Computing a Reality? / 7.1：

Easy of Programming / 7.1.1：

Program Portability and Legacy Code Migration / 7.1.2：

Performance Portability / 7.1.3：

Research Directions in Compilation for Reconfigurable Architectures / 7.2：

Programming Language Design / 7.2.1：

Intermediate Representation / 7.2.2：

Mapping to Multiple Computing Engines / 7.2.3：

Design-Space Exploration and Compilation Time / 7.2.4：

Pipelined Execution / 7.2.6：

Memory Mapping Optimizations / 7.2.7：

Application-Specific Compilers and Cores / 7.2.8：

Resource Virtualization / 7.2.9：

Dynamic and Incremental Compilation / 7.2.10：

Tackling the Compilation Challenge for Reconfigurable Architectures / 7.3：

Reconfigurable Architectures and Nanotechnology / 7.4：

Final Remarks / 7.5：

References

List of Acronyms

Index

Introduction / 1：

The Promise of Reconfigurable Architectures and Systems / 1.1：

The Challenge: How to Program and Compile for Reconfigurable Systems? / 1.2：

This Book: Key Techniques when Compiling to Reconfigurable Architecture / 1.3：

Organization of this Book / 1.4：

Overview of Reconfigurable Architectures / 2：

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