| Architectures [Regular Papers] |
| Architectural Exploration of the ADRES Coarse-Grained Reconfigurable Array / Frank Bouwens ; Mladen Berekovic ; Andreas Kanstein ; Georgi Gaydadjiev |
| A Configurable Multi-ported Register File Architecture for Soft Processor Cores / Mazen A.R. Saghir ; Rawan Naous |
| MT-ADRES: Multithreading on Coarse-Grained Reconfigurable Architecture / Kehuai Wu ; Jan Madsen |
| Asynchronous ARM Processor Employing an Adaptive Pipeline Architecture / Je-Hoon Lee ; Seung-Sook Lee ; Kyoung-Rok Cho |
| Partially Reconfigurable Point-to-Point Interconnects in Virtex-II Pro FPGAs / Jae Young Hur ; Stephan Wong ; Stamatis Vassiliadis |
| Systematic Customization of On-Chip Crossbar Interconnects / Todor Stefanov |
| Authentication of FPGA Bitstreams: Why and How / Saar Drimer |
| Architectures [Short Papers] |
| Design of a Reversible PLD Architecture / Jae-Jin Lee ; Dong-Guk Hwang ; Gi-Yong Song |
| Designing Heterogeneous FPGAs with Multiple SBs / Kostas Siozios ; Stelios Mamagkakis ; Dimitrios Soudris ; Antonios Thanailakis |
| Mapping Techniques and Tools [Regular Papers] |
| Partial Data Reuse for Windowing Computations: Performance Modeling for FPGA Implementations / Joonseok Park ; Pedro C. Diniz |
| Optimized Generation of Memory Structure in Compiling Window Operations onto Reconfigurable Hardware / Yazhuo Dong ; Yong Dou ; Jie Zhou |
| Adapting and Automating XILINX's Partial Reconfiguration Flow for Multiple Module Implementations / Rainer Scholz |
| A Linear Complexity Algorithm for the Automatic Generation of Convex Multiple Input Multiple Output Instructions / Carlo Galuzzi ; Keen Bertels |
| Evaluating Variable-Grain Logic Cells Using Heterogeneous Technology Mapping / Kazunori Matsuyama ; Motoki Amagasaki ; Hideaki Nakayama ; Ryoichi Yamaguchi ; Masahiro Iida ; Toshinori Sueyoshi |
| The Implementation of a Coarse-Grained Reconfigurable Architecture with Loop Self-pipelining / Jinhui Xu ; Guiming Wu |
| Hardware/Software Codesign for Embedded Implementation of Neural Networks / Cesar Torres-Huitzil ; Bernard Girau ; Adrien Gauffriau |
| Synthesis of Regular Expressions Targeting FPGAs: Current Status and Open Issues / Joao Bispo ; Ioannis Sourdis ; Joao M.P. Cardoso |
| Mapping Techniques and Tools [Short Papers] |
| About the Importance of Operation Grouping Procedures for Multiple Word-Length Architecture Optimizations / Nicolas Herve ; Daniel Menard ; Olivier Sentieys |
| Arithmetic [Regular Papers] |
| Switching Activity Models for Power Estimation in FPGA Multipliers / Ruzica Jevtic ; Carlos Carreras ; Gabriel Caffarena |
| Multiplication over F[subscript p]m on FPGA: A Survey / Jean-Luc Beuchat ; Takanori Miyoshi ; Yoshihito Oyama ; Eiji Okamoto |
| A Parallel Version of the Itoh-Tsujii Multiplicative Inversion Algorithm / Francisco Rodriguez-Henriquez ; Guillermo Morales-Luna ; Nazar A. Saqib ; Nareli Cruz-Cortes |
| A Fast Finite Field Multiplier / Edgar Ferrer ; Dorothy Bollman ; Oscar Moreno |
| Applications [Regular Papers] |
| Combining Flash Memory and FPGAs to Efficiently Implement a Massively Parallel Algorithm for Content-Based Image Retrieval / Rayan Chikhi ; Steven Derrien ; Auguste Noumsi ; Patrice Quinton |
| Image Processing Architecture for Local Features Computation / Javier Diaz ; Eduardo Ros ; Sonia Mota ; Richard Carrillo |
| A Compact Shader for FPGA-Based Volume Rendering Accelerators / Guenter Knittel |
| Ubiquitous Evolvable Hardware System for Heart Disease Diagnosis Applications / Yong-Min Lee ; Chang-Seok Choi ; Seung-Gon Hwang ; Hyun Dong Kim ; Chul Hong Min ; Jae-Hyun Park ; Hanho Lee ; Tae Seon Kim ; Chong-Ho Lee |
| FPGA-Accelerated Molecular Dynamics Simulations: An Overview / Xiaodong Yang ; Shengmei Mou |
| Reconfigurable Hardware Acceleration of Canonical Graph Labelling / David B. Thomas ; Wayne Luk ; Michael Stumpf |
| Reconfigurable Computing for Accelerating Protein Folding Simulations / Nilton B. Armstrong Jr. ; Heitor S. Lopes ; Carlos R. Erig Lima |
| Reconfigurable Parallel Architecture for Genetic Algorithms: Application to the Synthesis of Digital Circuits / Edson P. Ferlin ; Ederson Cichaczewski |
| Applications [Short Papers] |
| A Space Variant Mapping Architecture for Reliable Car Segmentation / Rafael Rodriguez |
| A Hardware SAT Solver Using Non-chronological Backtracking and Clause Recording Without Overheads / Shinya Hiramoto ; Masaki Nakanishi ; Shigeru Yamashita ; Yasuhiko Nakashima |
| Searching the Web with an FPGA Based Search Engine / Seamas McGettrick ; Dermot Geraghty ; Ciaran McElroy |
| An Acceleration Method for Evolutionary Systems Based on Iterated Prisoner's Dilemma / Yoshiki Yamaguchi ; Kenji Kanazawa ; Yoshiharu Ohke ; Tsutomu Maruyama |
| Real Time Architectures for Moving-Objects Tracking / Matteo Tomasi |
| Reconfigurable Hardware Evolution Platform for a Spiking Neural Network Robotics Controller / Patrick Rocke ; Brian McGinley ; Fearghal Morgan ; John Maher |
| Multiple Sequence Alignment Using Reconfigurable Computing / Maiko R. Moroz ; Ramon M. Menezes |
| Simulation of the Dynamic Behavior of One-Dimensional Cellular Automata Using Reconfigurable Computing / Wagner R. Weinert ; Cesar Benitez |
| Author Index |
| Architectures [Regular Papers] |
| Architectural Exploration of the ADRES Coarse-Grained Reconfigurable Array / Frank Bouwens ; Mladen Berekovic ; Andreas Kanstein ; Georgi Gaydadjiev |
| A Configurable Multi-ported Register File Architecture for Soft Processor Cores / Mazen A.R. Saghir ; Rawan Naous |
| MT-ADRES: Multithreading on Coarse-Grained Reconfigurable Architecture / Kehuai Wu ; Jan Madsen |
| Asynchronous ARM Processor Employing an Adaptive Pipeline Architecture / Je-Hoon Lee ; Seung-Sook Lee ; Kyoung-Rok Cho |
| Partially Reconfigurable Point-to-Point Interconnects in Virtex-II Pro FPGAs / Jae Young Hur ; Stephan Wong ; Stamatis Vassiliadis |
