FinFETs and other multi-gate transistors

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FinFETs and other multi-gate transistors / Jean-Pierre Colinge, editor

資料種別:: 電子ブック
出版情報:: [New York] : Springer, [20--]
形態:: 1 online resource (xiii, 339 p.)
シリーズ名:: Series on Integrated Circuits and Systems <BA76437098>
著者名:: Colinge, Jean-Pierre <DA06046015>
ISBN:: 9780387717524 [0387717528] (: electronic bk)
書誌ID:: TT00017792

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注記:

原資料の出版事項: New York : Springer , c2008
Description based on online resource (viewed on December 3, 2019)
Includes bibliographical references and index

主題:

集積回路［IC］．LSI

言語:

英語

目次情報:

Preface

Table of Content

Contributors

The SOI MOSFET: from Single Gate to Multigate / 1：

MOSFET scaling and Moore's law / 1.1：

Short-Channel Effects / 1.2：

Gate Geometry and Electrostatic Integrity / 1.3：

A Brief History of Multiple-Gate MOSFETs / 1.4：

Single-gate SOI MOSFETs / 1.4.1：

Double-gate SOI MOSFETs / 1.4.2：

Triple-gate SOI MOSFETs / 1.4.3：

Surrounding-gate (quadruple-gate) SOI MOSFETs / 1.4.4：

Other multigate MOSFET structures / 1.4.5：

Multigate MOSFET memory devices / 1.4.6：

Multigate MOSFET Physics / 1.5：

Classical physics / 1.5.1：

Natural length and short-channel effects / 1.5.1.1：

Current drive / 1.5.1.2：

Corner effect / 1.5.1.3：

Quantum effects / 1.5.2：

Volume inversion / 1.5.2.1：

Mobility effects / 1.5.2.2：

Threshold voltage / 1.5.2.3：

Inter-subband scattering / 1.5.2.4：

References

Multigate MOSFET Technology / 2：

Introduction / 2.1：

Active Area: Fins / 2.2：

Fin Width / 2.2.1：

Fin Height and Fin Pitch / 2.2.2：

Fin Surface Crystal Orientation / 2.2.3：

Fin Surface Preparation / 2.2.4：

Fins on Bulk Silicon / 2.2.5：

Nano-wires and Self-Assembled Wires / 2.2.6：

Gate Stack / 2.3：

Gate Patterning / 2.3.1：

Threshold Voltage and Gate Workfunction Requirements / 2.3.2：

Polysilicon Gate / 2.3.2.1：

Metal Gate / 2.3.2.2：

Tunable Workfunction Metal Gate / 2.3.2.3：

Gate EWF and Gate Induced Drain Leakage (GIDL) / 2.3.3：

Independently Controlled Gates / 2.3.4：

Source/Drain Resistance and Capacitance / 2.4：

Doping the Thin Fins / 2.4.1：

Junction Depth / 2.4.2：

Parasitic Resistance/Capacitance and Raised Source and Drain Structure / 2.4.3：

Mobility and Strain Engineering / 2.5：

Wafer Bending Experiment / 2.5.1：

Nitride Stress Liners / 2.5.3：

Embedded SiGe and SiC Source and Drain / 2.5.4：

Local Strain from Gate Electrode / 2.5.5：

Substrate Strain: Strained Silicon on Insulator / 2.5.6：

Contacts to the Fins / 2.6：

Dumbbell source and drain contact / 2.6.1：

Saddle contact / 2.6.2：

Contact to merged fins / 2.6.3：

Acknowledgments

BSIM-CMG: A Compact Model for Multi-Gate Transistors / 3：

Framework for Multigate FET Modeling / 3.1：

Multigate Models: BSIM-CMG and BSIM-IMG / 3.3：

The BSIM-CMG Model / 3.3.1：

The BSIM-IMG Model / 3.3.2：

BSIM-CMG / 3.4：

Core Model / 3.4.1：

Surface Potential Model / 3.4.1.1：

I-V Model / 3.4.1.2：

C-V Model / 3.4.1.3：

Modeling Physical Effects of Real Devices / 3.4.2：

Quantum Mechanical Effects (QME) / 3.4.2.1：

Short-channel Effects (SCE) / 3.4.2.2：

Experimental Verification / 3.4.3：

Surface Potential of independent DG-FET / 3.5：

BSIM-IMG features / 3.5.2：

Summary / 3.6：

Physics of the Multigate MOS System / 4：

Device electrostatics / 4.1：

Double gate MOS system / 4.2：

Modeling assumptions / 4.2.1：

Gate voltage effect / 4.2.2：

Semiconductor thickness effect / 4.2.3：

Asymmetry effects / 4.2.4：

Oxide thickness effect / 4.2.5：

Electron tunnel current / 4.2.6：

Two-dimensional confinement / 4.3：

Mobility in Multigate MOSFETs / 5：

Double-Gate MOSFETs and FinFETs / 5.1：

Phonon-limited mobility / 5.2.1：

Confinement of acoustic phonons / 5.2.2：

Interface roughness scattering / 5.2.3：

Coulomb scattering / 5.2.4：

Temperature Dependence of Mobility / 5.2.5：

Symmetrical and Asymmetrical Operation of DGSOI FETs / 5.2.6：

Crystallographic orientation / 5.2.7：

High-k dielectrics / 5.2.8：

Strained DGSOI devices / 5.2.9：

Silicon multiple-gate nanowires / 5.2.10：

Electrostatic description of Si nanowires / 5.3.1：

Electron transport in Si nanowires / 5.3.3：

Surface roughness / 5.3.4：

Experimental results and conclusions / 5.3.5：

Radiation Effects in Advanced Single- and Multi-Gate SOI MOSFETs / 6：

A brief history of radiation effects in SOI / 6.1：

Total Ionizing Dose Effects / 6.2：

A brief overview of Total Ionizing Dose effects / 6.2.1：

Advanced Single-Gate FDSOI devices / 6.2.2：

Description of Advanced FDSOI Devices / 6.2.2.1：

Front-gate threshold voltage shift / 6.2.2.2：

Single-transistor latch / 6.2.2.3：

Advanced Multi-Gate devices / 6.2.3：

Devices and process description / 6.2.3.1：

Single-Event Effects / 6.2.3.2：

Background / 6.3.1：

Effect of ion track diameter in nanoscale devices / 6.3.2：

Transient measurements on single-gate and FinFET SOI transistors / 6.3.3：

Scaling effects / 6.3.4：

Multi-Gate MOSFET Circuit Design / 7：

Digital Circuit Design / 7.1：

Impact of device performance on digital circuit design / 7.2.1：

Large-scale digital circuits / 7.2.2：

Leakage-performance trade off and energy dissipation / 7.2.3：

Multi-V[subscript T] devices and mixed-V[subscript T] circuits / 7.2.4：

High-temperature circuit operation / 7.2.5：

SRAM design / 7.2.6：

Analog Circuit Design / 7.3：

Device figures of merit and technology related design issues / 7.3.1：

Transconductance / 7.3.1.1：

Intrinsic transistor gain / 7.3.1.2：

Matching behavior / 7.3.1.3：

Flicker noise / 7.3.1.4：

Transit and maximum oscillation frequency / 7.3.1.5：

Self-heating / 7.3.1.6：

Charge trapping in high-k dielectrics / 7.3.1.7：

Design of analog building blocks / 7.3.2：

V-[subscript T]-based current reference circuit / 7.3.2.1：

Bandgap voltage reference / 7.3.2.2：

Operational amplifier / 7.3.2.3：

Comparator / 7.3.2.4：

Mixed-signal aspects / 7.3.3：

Current steering DAC / 7.3.3.1：

Successive approximation ADC / 7.3.3.2：

RF circuit design / 7.3.4：

SoC Design and Technology Aspects / 7.4：

Index

Preface

Table of Content

Contributors

The SOI MOSFET: from Single Gate to Multigate / 1：

MOSFET scaling and Moore's law / 1.1：

Short-Channel Effects / 1.2：

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