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図書
図書
1. Structured computer organization. 2nd ed
Andrew S. Tanenbaum
出版情報: Englewood Cliffs ; London : Prentice-Hall, 1984  xiii, 465 p. ; 24 cm
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Preface
Introduction / 1：
Computer Systems Organization / 1.1：
Structured Computer Organization
The Digital Logic Level / 3：
Languages, Levels, and Virtual Machines / 4：
The Microarchitecture Level
The Instruction Set Architecture Level / 1.1.2：
Contemporary Multilevel Machines
The Operating System Machine Level / 6：
Evolution of Multilevel Machines / 7：
The Assembly Language Level
Parallel Computer Architectures / 1.2：
Milestones in Computer Architecture
Reading List and Bibliography / 9：
The Zeroth Generation-Mechanical Computers (1642-1945) / Appendix A：
Binary Numbers
Floating-Point Numbers / 1.2.2：
The First Generation-Vacuum Tubes (1945-1955)
The Second Generation-Transistors (1955-1965) / 1.2.3：
The Third Generation-Integrated Circuits (1965-1980) / 1.2.4：
The Fourth Generation-Very Large Scale Integration (1980-?) / 1.2.5：
The Fifth Generation-Invisible Computers / 1.2.6：
The Computer Zoo / 1.3：
Technological and Economic Forces / 1.3.1：
The Computer Spectrum / 1.3.2：
Disposable Computers / 1.3.3：
Microcontrollers / 1.3.4：
Game Computers / 1.3.5：
Personal Computers / 1.3.6：
Servers / 1.3.7：
Collections of Workstations / 1.3.8：
Mainframes / 1.3.9：
Example Computer Families / 1.4：
Introduction to the Pentium 4 / 1.4.1：
Introduction to the UltraSPARC III / 1.4.2：
Introduction to the 8051 / 1.4.3：
Metric Units / 1.5：
Outline of This Book / 1.6：
Processors / 2.1：
CPU Organization / 2.1.1：
Instruction Execution / 2.1.2：
RISC versus CISC / 2.1.3：
Design Principles for Modern Computers / 2.1.4：
Instruction-Level Parallelism / 2.1.5：
Processor-Level Parallelism / 2.1.6：
Primary Memory / 2.2：
Bits / 2.2.1：
Memory Addresses / 2.2.2：
Byte Ordering / 2.2.3：
Error-Correcting Codes / 2.2.4：
Cache Memory / 2.2.5：
Memory Packaging and Types / 2.2.6：
Secondary Memory / 2.3：
Memory Hierarchies / 2.3.1：
Magnetic Disks / 2.3.2：
Floppy Disks / 2.3.3：
IDE Disks / 2.3.4：
SCSI Disks / 2.3.5：
RAID / 2.3.6：
CD-ROMs / 2.3.7：
CD-Recordables / 2.3.8：
CD-Rewritables / 2.3.9：
DVD / 2.3.10：
Blu-Ray / 2.3.11：
Input/Output / 2.4：
Buses / 2.4.1：
Terminals / 2.4.2：
Mice / 2.4.3：
Printers / 2.4.4：
Telecommunications Equipment / 2.4.5：
Digital Cameras / 2.4.6：
Character Codes / 2.4.7：
Summary / 2.5：
Gates and Boolean Algebra / 3.1：
Gates / 3.1.1：
Boolean Algebra / 3.1.2：
Implementation of Boolean Functions / 3.1.3：
Circuit Equivalence / 3.1.4：
Basic Digital Logic Circuits / 3.2：
Integrated Circuits / 3.2.1：
Combinational Circuits / 3.2.2：
Arithmetic Circuits / 3.2.3：
Clocks / 3.2.4：
Memory / 3.3：
Latches / 3.3.1：
Flip-Flops / 3.3.2：
Registers / 3.3.3：
Memory Organization / 3.3.4：
Memory Chips / 3.3.5：
RAMs and ROMs / 3.3.6：
CPU Chips and Buses / 3.4：
CPU Chips / 3.4.1：
Computer Buses / 3.4.2：
Bus Width / 3.4.3：
Bus Clocking / 3.4.4：
Bus Arbitration / 3.4.5：
Bus Operations / 3.4.6：
Example CPU Chips / 3.5：
The Pentium 4 / 3.5.1：
The UltraSPARC III / 3.5.2：
The 8051 / 3.5.3：
Example Buses / 3.6：
The ISA Bus / 3.6.1：
The PCI Bus / 3.6.2：
PCI Express / 3.6.3：
The Universal Serial Bus / 3.6.4：
Interfacing / 3.7：
I/O Chips / 3.7.1：
Address Decoding / 3.7.2：
An Example Microarchitecture / 3.8：
The Data Path / 4.1.1：
Microinstructions / 4.1.2：
Microinstruction Control: The Mic-1 / 4.1.3：
An Example Isa: IJVM / 4.2：
Stacks / 4.2.1：
The IJVM Memory Model / 4.2.2：
The IJVM Instruction Set / 4.2.3：
Compiling Java to IJVM / 4.2.4：
An Example Implementation / 4.3：
Microinstructions and Notation / 4.3.1：
Implementation of IJVM Using the Mic-1 / 4.3.2：
Design of the Microarchitecture Level / 4.4：
Speed versus Cost / 4.4.1：
Reducing the Execution Path Length / 4.4.2：
A Design with Prefetching: The Mic-2 / 4.4.3：
A Pipelined Design: The Mic-3 / 4.4.4：
A Seven-Stage Pipeline: The Mic-4 / 4.4.5：
Improving Performance / 4.5：
Branch Prediction / 4.5.1：
Out-of-Order Execution and Register Renaming / 4.5.3：
Speculative Execution / 4.5.4：
Examples of the Microarchitecture Level / 4.6：
The Microarchitecture of the Pentium 4 CPU / 4.6.1：
The Microarchitecture of the UltraSPARC-III Cu CPU / 4.6.2：
The Microarchitecture of the 8051 CPU / 4.6.3：
Comparison of the Pentium, Ultrasparc, and 8051 / 4.7：
Overview of the ISA Level / 4.8：
Properties of the ISA Level / 5.1.1：
Memory Models / 5.1.2：
Instructions / 5.1.3：
Overview of the Pentium 4 ISA Level / 5.1.5：
Overview of the UltraSPARC III ISA Level / 5.1.6：
Overview of the 8051 ISA Level / 5.1.7：
Data Types / 5.2：
Numeric Data Types / 5.2.1：
Nonnumeric Data Types / 5.2.2：
Data Types on the Pentium 4 / 5.2.3：
Data Types on the UltraSPARC III / 5.2.4：
Data Types on the 8051 / 5.2.5：
Instruction Formats / 5.3：
Design Criteria for Instruction Formats / 5.3.1：
Expanding Opcodes / 5.3.2：
The Pentium 4 Instruction Formats / 5.3.3：
The UltraSPARC III Instruction Formats / 5.3.4：
The 8051 Instruction Formats / 5.3.5：
Addressing / 5.4：
Addressing Modes / 5.4.1：
Immediate Addressing / 5.4.2：
Direct Addressing / 5.4.3：
Register Addressing / 5.4.4：
Register Indirect Addressing / 5.4.5：
Indexed Addressing / 5.4.6：
Based-Indexed Addressing / 5.4.7：
Stack Addressing / 5.4.8：
Addressing Modes for Branch Instructions / 5.4.9：
Orthogonality of Opcodes and Addressing Modes / 5.4.10：
The Pentium 4 Addressing Modes / 5.4.11：
The UltraSPARC III Addressing Modes / 5.4.12：
The 8051 Addressing Modes / 5.4.13：
Discussion of Addressing Modes / 5.4.14：
Instruction Types / 5.5：
Data Movement Instructions / 5.5.1：
Dyadic Operations / 5.5.2：
Monadic Operations / 5.5.3：
Comparisons and Conditional Branches / 5.5.4：
Procedure Call Instructions / 5.5.5：
Loop Control / 5.5.6：
The Pentium 4 Instructions / 5.5.7：
The UltraSPARC III Instructions / 5.5.9：
The 8051 Instructions / 5.5.10：
Comparison of Instruction Sets / 5.5.11：
Flow of Control / 5.6：
Sequential Flow of Control and Branches / 5.6.1：
Procedures / 5.6.2：
Coroutines / 5.6.3：
Traps / 5.6.5：
Interrupts
A Detailed Example: The Towers of Hanoi / 5.7：
The Towers of Hanoi in Pentium 4 Assembly Language / 5.7.1：
The Towers of Hanoi in UltraSPARC III Assembly Language / 5.7.2：
The IA-64 Architecture and the Itanium 2 / 5.8：
The Problem with the Pentium 4 / 5.8.1：
The IA-64 Model: Explicitly Parallel Instruction Computing / 5.8.2：
Reducing Memory References / 5.8.3：
Instruction Scheduling / 5.8.4：
Reducing Conditional Branches: Predication / 5.8.5：
Speculative Loads / 5.8.6：
Virtual Memory / 5.9：
Paging / 6.1.1：
Implementation of Paging / 6.1.2：
Demand Paging and the Working Set Model / 6.1.3：
Page Replacement Policy / 6.1.4：
Page Size and Fragmentation / 6.1.5：
Segmentation / 6.1.6：
Implementation of Segmentation / 6.1.7：
Virtual Memory on the Pentium 4 / 6.1.8：
Virtual Memory on the UltraSPARC III / 6.1.9：
Virtual Memory and Caching / 6.1.10：
Virtual I/O Instructions / 6.2：
Files / 6.2.1：
Implementation of Virtual I/O Instructions / 6.2.2：
Directory Management Instructions / 6.2.3：
Virtual Instructions for Parallel Processing / 6.3：
Process Creation / 6.3.1：
Race Conditions / 6.3.2：
Process Synchronization Using Semaphores / 6.3.3：
Example Operating Systems / 6.4：
Examples of Virtual Memory / 6.4.1：
Examples of Virtual I/O / 6.4.3：
Examples of Process Management / 6.4.4：
Introduction to Assembly Language / 6.5：
What Is an Assembly Language? / 7.1.1：
Why Use Assembly Language? / 7.1.2：
Format of an Assembly Language Statement / 7.1.3：
Pseudoinstructions / 7.1.4：
Macros / 7.2：
Macro Definition, Call, and Expansion / 7.2.1：
Macros with Parameters / 7.2.2：
Advanced Features / 7.2.3：
Implementation of a Macro Facility in an Assembler / 7.2.4：
The Assembly Process / 7.3：
Two-Pass Assemblers / 7.3.1：
Pass One / 7.3.2：
Pass Two / 7.3.3：
The Symbol Table / 7.3.4：
Linking and Loading / 7.4：
Tasks Performed by the Linker / 7.4.1：
Structure of an Object Module / 7.4.2：
Binding Time and Dynamic Relocation / 7.4.3：
Dynamic Linking / 7.4.4：
On-Chip Paralellism / 7.5：
On-Chip Multithreading / 8.1.1：
Single-Chip Multiprocessors / 8.1.3：
Coprocessors / 8.2：
Network Processors / 8.2.1：
Media Processors / 8.2.2：
Cryptoprocessors / 8.2.3：
Shared-Memory Multiprocessors / 8.3：
Multiprocessors vs. Multicomputers / 8.3.1：
Memory Semantics / 8.3.2：
UMA Symmetric Multiprocessor Architectures / 8.3.3：
NUMA Multiprocessors / 8.3.4：
COMA Multiprocessors / 8.3.5：
Message-Passing Multicomputers / 8.4：
Interconnection Networks / 8.4.1：
MPPs-Massively Parallel Processors / 8.4.2：
Cluster Computing / 8.4.3：
Communication Software for Multicomputers / 8.4.4：
Scheduling / 8.4.5：
Application-Level Shared Memory / 8.4.6：
Performance / 8.4.7：
Grid Computing / 8.5：
Suggestions for Further Reading / 8.6：
Introduction and General Works / 9.1.1：
Binary and Floating-Point Numbers / 9.1.2：
Assembly Language Programming / 9.1.10：
Alphabetical Bibliography / 9.2：
Finte-Precision Numbers / A：
Radix Number Systems / A.2：
Conversion From One Radix to Another / A.3：
Negative Binary Numbers / A.4：
Binary Arithmetic / A.5：
Principles of Floating Point / B：
IEEE Floating-Point Standard 754 / B.2：
Overview / C：
Assembly Language / C.1.1：
A Small Assembly Language Program / C.1.2：
The 8088 Processor / C.2：
The Processor Cycle / C.2.1：
The General Registers / C.2.2：
Pointer Registers / C.2.3：
Memory and Addressing / C.3：
Memory Organization and Segments / C.3.1：
The 8088 Instruction Set / C.3.2：
Move, Copy and Arithmetic / C.4.1：
Logical, Bit and Shift Operations / C.4.2：
Loop and Repetitive String Operations / C.4.3：
Jump and Call Instructions / C.4.4：
Subroutine Calls / C.4.5：
System Calls and System Subroutines / C.4.6：
Final Remarks on the Instruction Set / C.4.7：
The Assembler / C.5：
The ACK-Based Tutorial Assembler as88 / C.5.1：
Some Differences with Other 8088 Assemblers / C.5.3：
The Tracer / C.6：
Tracer Commands / C.6.1：
Getting Started / C.7：
Examples / C.8：
Hello World Example / C.8.1：
General Registers Example / C.8.2：
Call Command and Pointer Registers / C.8.3：
Debugging an Array Print Program / C.8.4：
Preface
Introduction / 1：
Computer Systems Organization / 1.1：
2.

図書
図書
2. Formal description of programming concepts--III : proceedings of the IFIP TC2/WG 2.2 Working Conference on Formal Description of Programming Concepts , Ebberup, Denmark, 25-28 August, 1986
edited by Martin Wirsing
出版情報: Amsterdam ; Tokyo : North-Holland Pub. Co., 1987  xii, 453 p. ; 24 cm
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3.

図書
図書
3. Automata, languages and programming : sixth colloquium, Graz, Austria, July 16-20, 1979 (: gw ; : us)
edited by Hermann A. Maurer
出版情報: Berlin : Springer-Verlag, 1980  ix, 684 p. ; 25 cm
シリーズ名: Lecture notes in computer science ; 71
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Preface
Fabrication / Part I：
Introduction / Chapter 1：
What are MEMS? / 1.1：
Why MEMS? / 1.2：
Low cost, redundancy and disposability / 1.2.1：
Favorable scalings / 1.2.2：
How are MEMS made? / 1.3：
Roadmap and perspective / 1.4：
Essay: The Role of Surface to Volume Atoms as Magnetic Devices Miniaturize
The substrate and adding material to it / Chapter 2：
The silicon substrate / 2.1：
Silicon growth / 2.2.1：
It's a crystal / 2.2.2：
Miller indices / 2.2.3：
It's a semiconductor / 2.2.4：
Additive technique: Oxidation / 2.3：
Growing an oxide layer / 2.3.1：
Oxidation kinetics / 2.3.2：
Additive technique: Physical vapor deposition / 2.4：
Vacuum fundamentals / 2.4.1：
Thermal evaporation / 2.4.2：
Sputtering / 2.4.3：
Other additive techniques / 2.5：
Chemical vapor deposition / 2.5.1：
Electrodeposition / 2.5.2：
Spin casting / 2.5.3：
Wafer bonding / 2.5.4：
Essay: Silicon Ingot Manufacturing
Creating and transferring patterns-Photolithography / Chapter 3：
Keeping it clean / 3.1：
Photoresist / 3.3：
Positive resist / 3.3.1：
Negative resist / 3.3.2：
Working with resist / 3.4：
Applying photoresist / 3.4.1：
Exposure and pattern transfer / 3.4.2：
Development and post-treatment / 3.4.3：
Masks / 3.5：
Resolution / 3.6：
Resolution in contact and proximity printing / 3.6.1：
Resolution in projection printing / 3.6.2：
Sensitivity and resist profiles / 3.6.3：
Modeling of resist profiles / 3.6.4：
Photolithography resolution enhancement technology / 3.6.5：
Mask alignment / 3.6.6：
Permanent resists / 3.7：
Essay: Photolithography-Past, Present and Future
Creating structures-Micromachining / Chapter 4：
Bulk micromachining processes / 4.1：
Wet chemical etching / 4.2.1：
Dry etching / 4.2.2：
Surface micromachining / 4.3：
Surface micromachining processes / 4.3.1：
Problems with surface micromachining / 4.3.2：
Lift-off / 4.3.3：
Process integration / 4.4：
A surface micromachining example / 4.4.1：
Designing a good MEMS process flow / 4.4.2：
Last thoughts / 4.4.3：
Essay: Introduction to MEMS Packaging
Solid mechanics / Chapter 5：
Fundamentals of solid mechanics / 5.1：
Stress / 5.2.1：
Strain / 5.2.2：
Elasticity / 5.2.3：
Special cases / 5.2.4：
Non-isotropic materials / 5.2.5：
Thermal strain / 5.2.6：
Properties of thin films / 5.3：
Adhesion / 5.3.1：
Stress in thin films / 5.3.2：
Peel forces / 5.3.3：
Applications / Part II：
Thinking about modeling / Chapter 6：
What is modeling? / 6.1：
Units / 6.2：
The input-output concept / 6.3：
Physical variables and notation / 6.4：
Preface to the modeling chapters / 6.5：
MEMS transducers-An overview of how they work / Chapter 7：
What is a transducer? / 7.1：
Distinguishing between sensors and actuators / 7.2：
Response characteristics of transducers / 7.3：
Static response characteristics / 7.3.1：
Dynamic performance characteristics / 7.3.2：
MEMS sensors: principles of operation / 7.4：
Resistive sensing / 7.4.1：
Capacitive sensing / 7.4.2：
Piezoelectric sensing / 7.4.3：
Resonant sensing / 7.4.4：
Thermoelectric sensing / 7.4.5：
Magnetic sensing / 7.4.6：
MEMS actuators: principles of operation / 7.5：
Capacitive actuation / 7.5.1：
Piezoelectric actuation / 7.5.2：
Thermo-mechanical actuation / 7.5.3：
Thermo-electric cooling / 7.5.4：
Magnetic actuation / 7.5.5：
Signal conditioning / 7.6：
A quick look at two applications / 7.7：
RF applications / 7.7.1：
Optical applications / 7.7.2：
Piezoresistive transducers / Chapter 8：
Modeling piezoresistive transducers / 8.1：
Bridge analysis / 8.2.1：
Relating electrical resistance to mechanical strain / 8.2.2：
Device case study: Piezoresistive pressure sensor / 8.3：
Capacitive transducers / Chapter 9：
Capacitor fundamentals / 9.1：
Fixed-capacitance capacitor / 9.2.1：
Variable-capacitance capacitor / 9.2.2：
An overview of capacitive sensors and actuators / 9.2.3：
Modeling a capacitive sensor / 9.3：
Capacitive half-bridge / 9.3.1：
Conditioning the signal from the half-bridge / 9.3.2：
Mechanical subsystem / 9.3.3：
Device case study: Capacitive accelerometer / 9.4：
Piezoelectric transducers / Chapter 10：
Modeling piezoelectric materials / 10.1：
Mechanical modeling of beams and plates / 10.3：
Distributed parameter modeling / 10.3.1：
Statics / 10.3.2：
Bending in beams / 10.3.3：
Bending in plates / 10.3.4：
Case study: Cantilever piezoelectric actuator / 10.4：
Thermal transducers / Chapter 11：
Basic heat transfer / 11.1：
Conduction / 11.2.1：
Convection / 11.2.2：
Radiation / 11.2.3：
Case study: Hot-arm actuator / 11.3：
Lumped element model / 11.3.1：
Distributed parameter model / 11.3.2：
FEA model / 11.3.3：
Essay: Effect of Scale on Thermal Properties
Introduction to microfluidics / Chapter 12：
Basics of fluid mechanics / 12.1：
Viscosity and flow regimes / 12.2.1：
Entrance lengths / 12.2.2：
Basic equations of fluid mechanics / 12.3：
Conservation of mass / 12.3.1：
Conservation of linear momentum / 12.3.2：
Conservation equations at a point: Continuity and Navier-Stokes equations / 12.3.3：
Some solutions to the Navier-Stokes equations / 12.4：
Couette flow / 12.4.1：
Poiseuille flow / 12.4.2：
Electro-osmotic flow / 12.5：
Electrostatics / 12.5.1：
Ionic double layers / 12.5.2：
Navier-Stokes with a constant electric field / 12.5.3：
Electrophoretic separation / 12.6：
Essay: Detection Schemes Employed in Microfluidic Devices for Chemical Analysis
Microfabrication laboratories / Part III：
Hot-arm actuator as a hands-on case study / Chapter 13：
Overview of fabrication of hot-arm actuators / 13.2：
Cleanroom safety and etiquette / 13.3：
Experiments / 13.4：
Wet oxidation of a silicon wafer / Experiment 1：
Photolithography of sacrificial layer / Experiment 2：
Depositing metal contacts with evaporation / Experiment 3：
Wet chemical etching of aluminum / Experiment 4：
Plasma ash release / Experiment 5：
Characterization of hot-arm actuators / Experiment 6：
Notation / Appendix A：
Periodic table of the elements / Appendix B：
The complimentary error function / Appendix C：
Color chart for thermally grown silicon dioxide / Appendix D：
Glossary
Subject Index
Preface
Fabrication / Part I：
Introduction / Chapter 1：
4.

図書
図書
4. Stellar turbulence : proceedings of Colloquium 51 of the International Astronomical Union, held at the University of Western Ontario, London, Ontario, Canada, August 27-30, 1979 (: gw ; : us)
edited by D. F. Gray and J. L. Linsky
出版情報: Berlin ; New York : Springer-Verlag, 1980  viii, 308 p. ; 25 cm
シリーズ名: Lecture notes in physics ; vol. 114
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Introduction / 1：
Continuous-Rate Packet-Switched Networks / 1.1：
Tiered-Service Networks / 1.2：
Multi-Tiered Pricing Schemes / 1.3：
Theory / Part I：
The Directional p-Median Problem: Definition and Applications / 2：
The p-Median Problem / 2.1：
Continuous vs. Discrete Space / 2.1.1：
A New Notion of Distance: The Directional Distance Metric / 2.2：
Summary of Complexity Results / 2.3：
Applications / 2.4：
Bandwidth Tiered Service: Deterministic Demands / 3：
Bandwidth Tiered Service as a DPM1 Problem / 3.1：
A Linear Complexity Algorithm of DPM1 / 3.2：
Graph Representation of DPM1 / 3.2.1：
Monge Condition and Totally Monotone Matrices / 3.2.2：
Efficient Dynamic Programming Algorithm for DPM1 / 3.2.3：
Impact of Tiered Service on Network Resources / 3.3：
Joint Optimization of the Number and Magnitude of Service Tiers / 3.4：
Bandwidth Tiered Service: TDM Emulation / 4：
TDM Emulation As A Constrained DPM1 Problem / 4.1：
Optimal Solution to TDM-DPM1 for Fixed / 4.1.1：
The Behavior Of The TDM-DPM1 Objective Function / 4.1.2：
An Exhaustive Search Algorithm for TDM-DPM1 / 4.1.3：
Optimization Heuristics / 4.1.4：
Performance Evaluation / 4.2：
Algorithm Comparison / 4.2.1：
Impact on the Network Provider: Bandwidth Penalty Due to TDM Emulation / 4.2.2：
Impact on Users: Blocking Probability / 4.2.3：
Bandwidth Tiered Service: Stochastic Demands / 5：
The Stochastic Directional p-Median Problem / 5.1：
Optimal Solution Through Nonlinear Programming / 5.2：
Example: Solution for the Uniform Demand Distribution / 5.2.1：
Example: Solution for the Increasing Demand Distribution / 5.2.2：
An Efficient Approximate Solution / 5.3：
An Approximate Formulation of SDPM1 / 5.3.1：
Optimal Solution to Approximate-SDPM1 / 5.3.2：
Convergence of the Approximate Solution / 5.3.3：
Tiered Structures for Multiple Services / 6：
The Directional p-Median Problem on the Plane / 6.1：
Heuristic Algorithms for Discrete-PM2 / 6.2：
Effect of Distance Properties on Computational Effort / 6.2.1：
Teitz and Bart (TB) Vertex Substitution Heuristic / 6.2.2：
The Global/Regional Interchange Algorithm (GRIA) / 6.2.3：
Heuristic Concentration (HC) / 6.2.4：
A Decomposition Heuristic for DPM2 / 6.3：
Evaluation of the Decomposition Heuristic / 6.3.1：
The Class of Strictly Dominating Solutions for DPM2 / 6.4：
Economics / Part II：
Economic Model for Bandwidth Tiered Service / 7：
Pricing of Internet Services / 7.1：
The Network Context / 7.2：
Economic Model for Sizing of Service Tiers / 7.3：
Maximization of Expected Surplus / 7.3.1：
Solution Through Nonlinear Programming / 7.3.2：
Optimizing the Number of Service Tiers / 7.3.3：
Optimal Pricing Based on Nash Bargaining / 7.4：
The Single Tier Case / 7.4.1：
The Multiple Tier Case / 7.4.2：
Optimal Sizing of Service Tiers / 7.5：
Optimal Pricing of Service Tiers / 7.5.3：
Accounting for the Cost of Service Tiers / 7.5.4：
Service Tiering As A Market Segmentation Strategy / 8：
Economic Model of User Diversity / 8.1：
The Multiple Tier Case: Market Segmentation / 8.2：
The MAX-S Problem with Fixed Tiers / 8.3.1：
Approximate Solution to the MAX-S Problem / 8.3.2：
Tier Structure Comparison / 8.4：
Tiered Service Bundling Under Budget Constraints / 9：
Economic Model of Service Bundling / 9.1：
Approximate Solution to the MAX-ES-2D Problem / 9.2：
The Fixed Tier Case / 9.2.1：
Cost Minimization on an Indifference Curve / 9.2.2：
Joint Optimization of Service Tiers and Prices / 9.2.3：
Quality of Service (QoS) / 9.3：
Packet Scheduling / 10：
Scheduling Objectives and Requirements / 10.1：
Packet Scheduling Disciplines / 10.2：
Timestamp-Based Schedulers / 10.2.1：
Frame-Based Schedulers / 10.2.2：
Hybrid Schedulers / 10.2.3：
Tiered-Service Fair Queueing (TSFQ) / 11：
Logical Operation / 11.1：
Virtual Time Computation / 11.1.2：
Intra-Tier Scheduler: The Fixed-Size Packet Case / 11.2：
Queue Structure and Operation / 11.2.1：
Intra-Tier Scheduler: The Variable-Size Packet Case / 11.3：
Queue Structure and Operations / 11.3.1：
Packet Sorting Operations / 11.3.2：
Elimination of Packet Sorting Operations / 11.3.3：
Experimental Evaluation of TSFQ / 11.4：
Testbed and Experimental Setup / 11.4.1：
Performance Results / 11.4.2：
References
Index
Introduction / 1：
Continuous-Rate Packet-Switched Networks / 1.1：
Tiered-Service Networks / 1.2：
5.

図書
図書
5. Patañjali's Vyākaraṇa-Mahābhāṣya : Prātipadikārthaśeṣāhnika (p. 2.3.46-2.3.71). 1st ed
introduction, text, translation and notes by S.D. Joshi and J.A.F. Roodbergen
出版情報: Pune : University of Poona, 1981  xxiv, 40, 191 p. ; 25 cm
シリーズ名: Publications of the Centre of Advanced Study in Sanskrit ; class C ; no. 14
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6.

図書
図書
6. Patañjali's Vyākaraṇa-Mahābhāṣya : Vibhaktyāhnika (p. 2.3.18-2.3.45). 1st ed
introduction, text, translation and notes by S.D. Joshi and J.A.F. Roodbergen
出版情報: Pune : University of Poona, 1980  xxxiii, 26, 114 p. ; 25 cm
シリーズ名: Publications of the Centre of Advanced Study in Sanskrit ; class C ; no. 12
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7.

図書
図書
7. Combinatorial algorithms
T.C. Hu
出版情報: Reading, MA : Addison-Wesley Pub. Co., c1982  292 p. ; 24 cm
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目次情報: 続きを見る
Shortest Paths / Chapter 1：
Graph terminology / 1.1：
Shortest path / 1.2：
Multiterminal shortest paths / 1.3：
Decomposition algorithm / 1.4：
Acyclic network / 1.5：
Shortest paths in a general network / 1.6：
Minimum spanning tree / 1.7：
Breadth-first-search and depth-first-search / 1.8：
Maximum flows / Chapter 2：
Maximum flow / 2.1：
Algorithms for max flows / 2.2：
Ford and Fulkerson / 2.2.1：
Karzanov's algorithm / 2.2.2：
MPM algorithms / 2.2.3：
Analysis of algorithms / 2.2.4：
Multi-terminal maximum flows / 2.3：
Realization / 2.3.1：
Analysis / 2.3.2：
Synthesis / 2.3.3：
Multi-commodity flows / 2.3.4：
Minimum cost flows / 2.4：
Applications / 2.5：
Sets of distinct representatives / 2.5.1：
PERT / 2.5.2：
Optimum communication spanning tree / 2.5.3：
Dynamic programming / Chapter 3：
Introduction / 3.1：
Knapsack problem / 3.2：
Two-dimensional knapsack problem / 3.3：
Minimum-cost alphabetic tree / 3.4：
Summary / 3.5：
Backtracking / Chapter 4：
Estimating the efficiency of backtracking / 4.1：
Branch and bound / 4.3：
Game-tree / 4.4：
Binary tree / Chapter 5：
Huffman's tree / 5.1：
Alphabetic tree / 5.3：
Hu-Tucker algorithm / 5.4：
Feasibility and optimality / 5.5：
Garsia and Wachs' algorithm / 5.6：
Regular cost function / 5.7：
T-ary tree and other results / 5.8：
Heuristic and near optimum / Chapter 6：
Greedy algorithm / 6.1：
Bin-packing / 6.2：
Job-scheduling / 6.3：
Job-scheduling (tree-constraints) / 6.4：
Matrix multiplication / Chapter 7：
Strassen's matrix multiplication / 7.1：
Optimum order of multiplying matrices / 7.2：
Partitioning a convex polygon / 7.3：
The heuristic algorithm / 7.4：
NP-complete / Chapter 8：
Polynomial algorithms / 8.1：
Nondeterministic algorithms / 8.3：
NP-complete problems / 8.4：
Facing a new problem / 8.5：
Local indexing algorithms / Chapter 9：
Mergers of algorithms / 9.1：
Maximum flows and minimum cuts / 9.2：
Maximum adjacency and minimum separation / 9.3：
Gomory-Hu tree / Chapter 10：
Tree edges and tree links / 10.1：
Contraction / 10.2：
Domination / 10.3：
Equivalent formulations / 10.4：
Optimum mergers of companies / 10.4.1：
Optimum circle partition / 10.4.2：
Extreme stars and host-feasible circles / 10.5：
The high-level approach / 10.6：
Chop-stick method / 10.7：
Relationship between phases / 10.8：
The staircase diagram / 10.9：
Complexity issues / 10.10：
Comments on Chapters 2, 5 & 6 / Appendix A：
Ancestor trees / A.1：
Minimum surface or plateau problem / A.2：
Comments on binary trees in chapter 5 / A.3：
A simple proof of the Hu-Tucker algorithm / A.3.1：
Binary search trees / A.3.2：
Binary search on a tape / A.3.3：
Comments on §6.2, bin-packing / A.4：
Network algebra / Appendix B：
Shortest Paths / Chapter 1：
Graph terminology / 1.1：
Shortest path / 1.2：
8.

図書
図書
8. Очерки русской литературы Сибири : в 2-х томах (т. 1 ; т. 2)
[ред. Ю. С. Постнов ... [и др.]]
出版情報: Новосибирск : Изд-во "Наука" Сибирское отд-ние, 1982  2 v. ; 25 cm
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1. Дореволюционный период
1. Dorevoli︠u︡t︠s︡ionnyĭ period
2. Советский период
2. Sovetskiĭ period
1. Дореволюционный период
1. Dorevoli︠u︡t︠s︡ionnyĭ period
2. Советский период
9.

図書
図書
9. Structure and interpretation of computer programs (: MIT Press ; : MIT Press : pbk ; : McGraw-Hill)
Harold Abelson and Gerald Jay Sussman, with Julie Sussman ; foreword by Alan J. Perlis
出版情報: Cambridge, Mass. : MIT Press , New York : McGraw-Hill, c1985  xx, 542 p. ; 24 cm
シリーズ名: The MIT electrical engineering and computer science series
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目次情報: 続きを見る
Contents
Foreword
Preface to the Second Edition
Preface to the First Edition
Acknowledgments
Building Abstractions with Procedures / 1：
The Elements of Programming / 1.1：
Procedures and the Processes They Generate / 1.2：
Formulating Abstractions with Higher-Order Procedures / 1.3：
Building Abstractions with Data / 2：
Introduction to Data Abstraction / 2.1：
Hierarchical Data and the Closure Property / 2.2：
Symbolic Data / 2.3：
Multiple Representations for Abstract Data / 2.4：
Systems with Generic Operations / 2.5：
Modularity, Objects and State / 3：
Assignment and Local State / 3.1：
The Environmental Model of Evaluation / 3.2：
Modeling with Mutable Data / 3.3：
Concurrency: Time Is of the Essence / 3.4：
Streams / 3.5：
Metalinguistic Abstraction / 4：
The Metaciricular Evaluator / 4.1：
Variations on a Scheme--Lazy Evaluation / 4.2：
Variations on a Scheme--Nondeterministic Computing / 4.3：
Logic Programming / 4.4：
Computing with Register Machines / 5：
Designing Register Machines / 5.1：
A Register-Machine Simulator / 5.2：
Storage Allocation and Garbage Collection / 5.3：
The Explicit Control Evaluator / 5.4：
Compilation / 5.5：
References
List of Exercises
Index
Contents
Foreword
Preface to the Second Edition
10.

図書
図書
10. Data base techniques for pictorial applications, Florence, June 20-22, 1979 (: gw ; : us)
edited by A. Blaser
出版情報: Berlin ; New York : Springer-Verlag, 1980  xi, 599 p. ; 24 cm
シリーズ名: Lecture notes in computer science ; 81
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目次情報: 続きを見る
The International Landscape of Cyber Security / 1：
A Brief History of Global Responses to Cyber Threats / 2：
World Summit on the Information Society (WSIS) / 2.1：
Council of Europe Convention on Cybercrime / 2.2：
International Intergovernmental Organizations / 3：
United Nations (UN) / 3.1：
International Telecommunication Union (ITU) / 3.1.1：
ITU Telecommunication Standardization Sector (ITU-T) / 3.1.1.1：
ITU Telecommunication Development Sector (ITU-D) / 3.1.1.2：
ITU Radiocommunication Sector (ITU-R) / 3.1.1.3：
ITU Corporate Strategy Division (CSD) / 3.1.1.4：
WSIS Thematic Meeting on Countering Spam / 3.1.1.5：
World Trust Signatories Association (WTSA) / 3.1.1.6：
United Nations Office on Drugs and Crime (UNODC) / 3.1.2：
United Nations Office for Disarmament Affairs (UNODA) / 3.1.3：
Organisation for Economic Co-operation and Development (OECD) / 3.2：
North Atlantic Treaty Organization (NATO) / 3.3：
Group of Eight (G8) / 3.4：
World Customs Organization (WCO) / 3.5：
International Incident Response / 3.6：
G8 24/7 Network of Contacts for High-Tech Crime / 3.6.1：
International Law Enforcement Cooperation / 3.7：
International Criminal Police Organization (INTERPOL) / 3.7.1：
International Law Enforcement Telecommunications Seminar (ILETS) / 3.7.2：
Regional Intergovernmental Organizations / 4：
Europe / 4.1：
European Union (EU) / 4.1.1：
Council of Europe (COE) / 4.1.2：
Organization for Security and Co-operation in Europe (OSCE) / 4.1.3：
European Telecommunications Standards Institute (ETSI) / 4.1.4：
European Committee for Standardization (CEN) / 4.1.5：
ICTStandards Board (ICTSB) / 4.1.6：
European Network and Information Security Agency (ENISA) / 4.1.7：
European Incident Response / 4.1.8：
European Task Force on Computer Security Incident Response Teams (TF-CSIRT) / 4.1.8.1：
European Law Enforcement Cooperation / 4.1.9：
European Law Enforcement Organisation (Europol) / 4.1.9.1：
National Policing Improvement Agency (NPIA) / 4.1.9.2：
Asia-Pacific / 4.2：
Asia-Pacific Economic Cooperation (APEC) / 4.2.1：
Association of Southeast Asian Nations (ASEAN) / 4.2.2：
ASEAN Regional Forum (ARF) / 4.2.2.1：
ASEAN Telecommunications and IT Ministers (TELMIN) / 4.2.2.2：
Asia-Pacific Telecommunity (APT) / 4.2.3：
United Nations Economic and Social Commission for Asia and the Pacific (ESCAP) / 4.2.4：
China-Japan-Korea (CJK) / 4.2.5：
Asia-Pacific Incident Response / 4.2.6：
Asia Pacific Computer Emergency Response Team (APCERT) / 4.2.6.1：
Asia-Pacific Law Enforcement Cooperation / 4.2.7：
Americas / 4.3：
Organization of American States (OAS) / 4.3.1：
Inter-American Telecommunication Commission (CITEL) / 4.3.1.1：
Latin American Cooperation of Advanced Networks (CLARA) / 4.3.2：
CLARA Security Task Force (GT-Seg) / 4.3.2.1：
Americas Incident Response / 4.3.3：
Inter-American Committee Against Terrorism (CICTE) / 4.3.3.1：
CLARA Computer Security Incident Response Team (GT-CSIRT) / 4.3.3.2：
Americas Law Enforcement Cooperation / 4.3.4：
Group of Governmental Experts on Cyber-Crime / 4.3.4.1：
Private-Public and Non-Governmental Organizations (NGOs) / 5：
Advocacy Groups / 5.1：
Anti-Spam / 5.1.1：
Coalition Against Unsolicited Commercial Email (CAUCE) / 5.1.1.1：
London Action Plan (LAP) / 5.1.1.2：
Messaging Anti-Abuse Working Group (MAAWG) / 5.1.1.3：
Spamhaus Project / 5.1.1.4：
StopSpamAlliance (SSA) / 5.1.1.5：
The European Spambox Project (SPOTSPAM) / 5.1.1.6：
Anti-Phishing / 5.1.2：
Anti-Phishing Working Group (APWG) / 5.1.2.1：
Anti-Spyware / 5.1.3：
Anti-Spyware Coalition (ASC) / 5.1.3.1：
Anti-Botnets / 5.1.4：
International Botnet Task Force (BTF) / 5.1.4.1：
Incident Response / 5.2：
ComputerSecurity Incident Response Teams (CSIRTs) / 5.2.1：
Forum of Incident Response and Security Teams (FIRST) / 5.2.2：
Policy, Education, & Public Awareness / 5.3：
Authentication and Online Trust Alliance (AOTA) / 5.3.1：
Global Information Infrastructure Commission (GIIC) / 5.3.2：
International Chamber of Commerce (ICC) / 5.3.3：
International Federation for Information Processing (IFIP) / 5.3.4：
Open Information Systems Security Group (OISSG) / 5.3.5：
Society for the Policing of Cyberspace (POLCYB) / 5.3.6：
SysAdmin, Audit, Network, Security (SANS) Institute / 5.3.7：
World Information Technology and Services Alliance (WITSA) / 5.3.8：
Global Internet Project (GIP) / 5.3.8.1：
Research, Development, & Standardization / 5.4：
3rd Generation Partnership Project (3GPP) / 5.4.1：
Central and Eastern European Networking Association (CEENet) / 5.4.2：
Cooperative Association for Internet Data Analysis (CAIDA) / 5.4.3：
GSM Association (GSMA) / 5.4.4：
Institute of Electrical and Electronics Engineers (IEEE) / 5.4.5：
International Organization for Standardization (ISO) / 5.4.6：
Internet Engineering Task Force (IETF) / 5.4.7：
Internet Research Task Force (IRTF) / 5.4.8：
Internet Society (ISOC) / 5.4.9：
Organization for the Advancement of Structured Information Standards (OASIS) / 5.4.10：
Trans-European Research and Education and Education Networking Association (TERENA) / 5.4.11：
World Wide Web Consortium (W3C) / 5.4.12：
Making global cyberspace more secure...? / 6：
Further Analysis of Recent Advances in Cyber Security / 6.1：
Opportunities for Further Research / 6.2：
Abbreviations / Appendix A：
Convention on Cybercrime CETS No.: 185 / Appendix B：
Index
References
The International Landscape of Cyber Security / 1：
A Brief History of Global Responses to Cyber Threats / 2：
World Summit on the Information Society (WSIS) / 2.1：
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