Keynote Speech |
Architectural Challenges for the Next Decade Integrated Platforms / A. Cuomo |
Gate-Level Modeling and Design |
Analysis of High-Speed Logic Families / G. Privitera ; F. Pessolano |
Low-Voltage, Double-Edge-Triggered Flip Flop / P. Varma ; A. Chakraborty |
A Genetic Bus Encoding Technique for Power Optimization of Embedded Systems / G. Ascia ; V. Catania ; M. Palesi |
State Encoding for Low-Power FSMs in FPGA / L. Mengibar ; L. Entrena ; M.G. Lorenz ; R. Sánchez-Reillo |
Low Level Modeling and Characterization |
Reduced Leverage of Dual Supply Voltages in Ultra Deep Submicron Technologies / T. Schoenauer ; J. Berthold ; C. Heer |
A Compact Charge-Based Crosstalk Induced Delay Model for Submicronic CMOS Gates / J.L. Rosselló ; J. Segura |
CMOS Gate Sizing under Delay Constraint / A. Verle ; X. Michel ; P. Maurine ; N. Azémard ; D. Auvergne |
Process Characterization for Low VTH and Low Power Design / E. Seebacher ; G. Rappitsch ; H. Höller |
Power and Energy Consumption of CMOS Circuits: Measurement Methods and Experimental Results / J. Rius ; A. Peidro ; S. Manich ; R. Rodriguez |
Interconnect Modeling and Optimization |
Effects of Temperature in Deep-Submicron Global Interconnect Optimization / M.R. Casu ; M. Graziano ; G. Piccinini ; G. Masera ; M. Zamboni |
Interconnect Parasitic Extraction Tool for Radio-Frequency Integrated Circuits / J. Lescot ; F.J.R. Clément |
Estimation of Crosstalk Noise for On-Chip Buses / S. Tuuna ; J. Isoaho |
A Block-Based Approach for SoC Global Interconnect Electrical Parameters Characterization / M. Addino |
Interconnect Driven Low Power High-Level Synthesis / A. Stammermann ; D. Helms ; M. Schulte ; A. Schulz ; W. Nebel |
Asynchronous Techniques |
Bridging Clock Domains by Synchronizing the Mice in the Mousetrap / J. Kessel ; A. Peeters ; S.-J. Kim |
Power-Consumption Reduction in Asynchronous Circuits Using Delay Path Unequalization / S. López ; O. Garnica ; J.I. Hidalgo ; J. Lanchares ; R. Hermida |
New GALS Technique for Datapath Architectures / M. Krstić ; E. Grass |
Power/Area Tradeoffs in 1-of-M Parallel-Prefix Asynchronous Adders / J.L. Fragoso ; G. Sicard ; M. Renaudin |
Statistic Implementation of QDI Asynchronous Primitives / J.B. Rigaud ; F. Bouesse |
The Emergency of Design for Energy Efficiency: An EDA Perspective / A. Domic |
Industrial Session |
The Most Complete Mixed-Signal Simulation Solution with ADVance MS / J. Oudinot |
Signal Integrity and Power Supply Network Analysis of Deep SubMicron Chips / L.K. Scheffer |
Power Management in Synopsys Galaxy Design Platform |
Open Multimedia Platform for Next-Generation Mobile Devices |
RTL Power Modeling and Memory Optimisation |
Statistical Power Estimation of Behavioral Descriptions / B. Arts ; N. van der Eng ; M. Heijligers ; H. Munk ; F. Theeuwen ; L. Benini ; E. Macii ; A. Milia ; R. Maro ; A. Bellu |
A Statistic Power Model for Non-synthetic RTL Operators / M. Bruno ; A. Macii ; M. Poncino |
Energy Efficient Register Renaming / G. Kucuk ; O. Ergin ; D. Ponomarev ; K. Ghose |
Stand-by Power Reduction for Storage Circuits / S. Cservany ; J.-M. Masgonty ; C. Piguet |
A Unified Framework for Power-Aware Design of Embedded Systems / J.L. Ayala ; M. Lopez-Vallejo |
High-Level Modeling |
A Flexible Framework for Fast Multi-objective Design Space Exploration of Embedded Systems / G. Palermo ; C. Silvano ; V. Zaccaria |
High Level Area and Current Estimation / Fei Li ; Lei He ; Joe Basile ; Rakesh J. Patel ; Hema Ramamurthy |
Switching Activity Estimation in Non-linear Architectures / A. García-Ortiz ; L. Kabulepa ; M. Glesner |
Instruction Level Energy Modeling for Pipelined Processors / S. Nikolaidis ; N. Kavvadias ; T. Laopoulos ; L. Bisdounis ; S. Blionas |
Power Estimation Approach of Dynamic Data Storage on a Hardware Software Boundary Level / M. Leeman ; D. Atienza ; F. Catthoor ; V. De Florio ; G. Deconinck ; J.M. Mendias ; R. Lauwereins |
Power Efficient Technologies and Designs |
An Adiabatic Charge Pump Based Charge Recycling Design Style / V. Manne ; A. Tyagi |
Reduction of the Energy Consumption in Adiabatic Gates by Optimal Transistor Sizing / J. Fischer ; E. Amirante ; F. Randazzo ; G. Iannaccone ; D. Schmitt-Landsiedel |
Low Power Response Time Accelerator with Full Resolution for LCD Panel / Tae-Chan Kim ; Meejoung Kim ; Chulwoo Kim ; Bong-Young Chung ; Soo-Won Kim |
Memory Compaction and Power Optimization for Wavelet-Based Coders / V. Ferentinos ; M. Milia ; G. Lafruit ; J. Bormans |
Design Space Exploration and Trade-Offs in Analog Amplifier Design / E. Hjalmarson ; R. Hägglund ; L. Wanhammar |
Power and Timing Driven Physical Design Automation / R. Reis |
Communication Modeling and Design |
Analysis of Energy Consumed by Secure Session Negotiation Protocols in Wireless Networks / R. Karri ; P. Mishra |
Remote Power Control of Wireless Network Interfaces / A. Acquaviva ; T. Simunic ; V. Deolalikar ; S. Roy |
Architecture-Driven Voltage Scaling for High-Throughput Turbo-Decoders / F. Gilbert ; N. When |
A Fully Digital Numerical-Controlled-Oscillator / Seyed Reza Abdollahi ; B. Bakkaloglu ; S.K. Hosseini |
Low Power Issues in Processors and Multimedia |
Energy Optimization of High-Performance Circuits / Hoang Q. Dao ; Bart R. Zeydel ; Vojin G. Oklobdzija |
Instruction Buffering Exploration for Low Energy Embedded Processors / T. Vander Aa ; M. Jayapala ; F. Barat ; H. Corporaal |
Power-Aware Branch Predictor Update for High-Performance Processors / A. Baniasadi |
Power Optimization Methodology for Multimedia Applications Implementation on Reconfigurable Platforms / K. Tatas ; K. Siozios ; D.J. Soudris ; A. Thanailakis ; K. Masselos ; K. Potamianos |
High-Level Algorithmic Complexity Analysis for the Implementation of a Motion-JPEG2000 Encoder / M. Ravasi ; M. Mattavelli ; P. Schumacher ; R. Turney |
Poster Session 1 |
Metric Definition for Circuit Speed Optimization |
Optical versus Electrical Interconnections for Clock Distribution Networks in New VLSI Technologies / G. Tosik ; F. Gaffiot ; Z. Lisik ; I. O'Connor ; F. Tissafi-Drissi |
An Asynchronous Viterbi Decoder for Low-Power Applications / B. Javadi ; M. Naderi ; H. Pedram ; A. Afzali-Kusha ; M.K. Akbari |
Analysis of the Contribution of Interconnect Effects in the Energy Dissipation of VLSI Circuits / E. Isern ; M. Roca ; F. Moll |
A New Hybrid CBL-CMOS Cell for Optimum Noise/Power Application / R. Jiménez ; P. Parra ; P. Sanmartín ; A.J. Acosta |
Computational Delay Models to Estimate the Delay of Floating Cubes in CMOS Circuits / D. Guerrero ; G. Wilke ; J.L. Güntzel ; M.J. Bellido ; J.J. Chico ; P. Ruiz-de-Clavijo ; A. Millan |
Poster Session 2 |
A Pratical ASIC Methodology for Flexible Clock Tree Synthesis with Routing Blockages / Dongsheng Wang ; P. Suaris ; Nan-chi Chou |
Frequent Value Cache for Low-Power Asynchronous Dual-Rail Bus / Byung-Soo Choi ; Dong-Ik Lee |
Reducing Static Energy of Cache Memories via Prediction-Table-Less Way Prediction / Akihito Sakanaka ; Toshinori Sato |
A Bottom-Up Approach to On-Chip Signal Integrity / A. Bogliolo |
Advanced Cell Modeling Techniques Based on Polynomial Expressions / Wen-Tsong Shiue ; Weetit Wanalertlak |
RTL-Based Signal Statistics Calculation Facilitates Low Power Design Approaches / P. Fugger |
Poster Session 3 |
Data Dependences Critical Path Evaluation at C/C++ System Level Description / A. Prihozhy ; D. Mlynek |
A Hardware/Sofware Partitioning and Scheduling Approach for Embedded Systems with Low-Power and High Performance Requirements / J. Resano ; D. Mozos ; E. Pérez ; H. Mecha ; J. Septién |
Consideration of Control System and Memory Contributions in Pratical Resource-Constrained Scheduling for Low Power / Chee Lee |
Low Power Cache with Successive Tag Comparison Algorithm |
FPGA Architecture Design and Toolset for Logic Implementation / N. Vasiliadis ; S. Siskos |
Bit-Level Allocation for Low Power in Behavioural High-Level Synthesis / M.C. Molina ; R. Ruiz-Sautua |
Author Index |
Keynote Speech |
Architectural Challenges for the Next Decade Integrated Platforms / A. Cuomo |
Gate-Level Modeling and Design |
Analysis of High-Speed Logic Families / G. Privitera ; F. Pessolano |
Low-Voltage, Double-Edge-Triggered Flip Flop / P. Varma ; A. Chakraborty |
A Genetic Bus Encoding Technique for Power Optimization of Embedded Systems / G. Ascia ; V. Catania ; M. Palesi |