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Wolfgang Nebel, Association for Computing Machinery-Digital Library.
出版情報: IEEE/IET Electronic Library (IEL) Conference Proceedings , 2001
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目次情報: 続きを見る
DATE Executive Committee
Technical Program Chairs
Vendors Committee
DATE Sponsor Committee
Technical Program Committee
Reviewers
Welcome to DATE 2001
Best Paper Awards
Tutorials
Call for Papers DATE 2002
Plenary: Keynote Session
The Semiconductor Dynamic in the Information Age--Driving New Technologies, Trends and Markets / U. Schumacher, CEO
Complementary Approaches to Designing Correct Circuits / 1A:
Abstraction of Word-Level Linear Arithmetic Functions from Bit-Level Component Descriptions / P. Dasgupta ; P. Chakrabarti ; A. Nandi ; S. Krishna ; A. Chakrabarti
Biaising Symbolic Research by Means of Dynamic Activity Profiles / G. Cabodi ; P. Camurati ; S. Quer
New Design Methods with SystemC / 1B:
A Methodology for Interfacing Open Source SystemC with a Third Party Software / L. Charest ; M. Reid ; E. Aboulhamid ; G. Bois
Behavioral Synthesis with SystemC / G. Economakos ; P. Oikonomakos ; I. Panagopoulos ; I. Poulakis ; G. Papakonstantiou
SystemC[superscript SV]--An Extension of SystemC for Mixed Multi-Level Communication Modeling and Interface-Based System Design / R. Siegmund ; D. Muller
Embedded Tutorial--TRP: Integrating Embedded Test and ATE / 1C:
Test Resource Partitioning: A Design and Test Issue
Embedded Tutorial--Current Trends in the Design of Automotive Electronic Systems / 1E:
Current Trends in the Design of Automotive Electronic Systems
Platforms and IP-Based Design / 2A:
Component Selection and Matching for IP-Based Design / T. Zhang ; G. De Micheli ; L. Benini
A Universal Communication Model for an Automotive System Integration Platform / T. Demmeler ; P. Giusto
An Efficient Architecture Model for Systematic Design of Application-Specific Multiprocessor SoC / A. Baghdadi ; D. Lyonnard ; N. Zergainoh ; A. Jerraya
Approaching Semantics of Design Languages / 2B:
The Simulation Semantics of SystemC / J. Ruf ; D. Hoffmann ; J. Gerlach ; T. Kropf ; W. Rosenstiel ; W. Mueller
MetaRTL: Raising the Abstraction Level of RTL Design / J. Zhu
A Model for Describing Communication between Aggregate Objects in the Specification and Design of Embedded Systems / K. Svarstad ; G. Nicolescu
BIST and Diagnosis / 2C:
Circuit Partitioning for Efficient Logic BIST Synthesis / A. Irion ; G. Kiefer ; H. Vranken ; H. Wunderlich
Deterministic Software-Based Self-Testing of Embedded Processor Cores / A. Paschalis ; D. Gizopoulos ; N. Kranitis ; M. Psarakis ; Y. Zorian
Memory Fault Diagnosis by Syndrome Compression / J. Li ; C. Wu
Diagnosis for Scan-Based BIST: Reaching Deep into the Signatures / I. Bayraktaroglu ; A. Orailoglu
Hot Topic--EUCAR Session / 2E:
Vehicle Electric/Electronic Architecture--One of the Most Important Challenges for OEM's / G. Hettich ; T. Thurner
SAT Based Verification Techniques / 3A:
Using SAT for Combinational Equivalence Checking / E. Goldberg ; M. Prasad ; R. Brayton
Combinational Equivalence Checking Using Boolean Satisfiability and Binary Decision Diagrams / S. Reda ; A. Salem
An Efficient Learning Procedure for Multiple Implication Checks / Y. Novikov
Panel Session--C/C[superscript ++]: Progress or Deadlock in SLD Specification? / 3B:
C/C[superscript ++]: Progress or Deadlock in System-Level Specification
Advances in SoC Testing / 3C:
An Integrated System-On-Chip Test Framework / E. Larsson ; Z. Peng
Efficient Test Data Compression and Decompression for System-On-A-Chip Using Integral Scan Chains and Golomb Coding / A. Chandra ; K. Chakrabarty
Testing TAPed Cores and Wrapped Cores with the Same Test Access Mechanism / M. Benabdenbi ; W. Maroufi ; M. Marzouki
On Applying the Set Covering Model to Reseeding / S. Chiusano ; S. Di Carlo ; P. Prinetto
Panel Session--Data Management--Limiter or Accelerator for Electronic Design Creativity? / 3E:
Data Management--Limiter or Accelerator for Electronic Design Creativity
Analysis of Communication Systems / 4A:
Efficient Bit-Error-Rate Estimation of Multicarrier Transceivers / G. Vandersteen ; P. Wambacq ; S. Donnay ; M. Engels ; I. Bolsens ; Y. Rolain ; J. Schoukens
Efficient Time-Domain Simulation of Telecom Frontends Using a Complex Damped Exponential Signal Model / P. Vanassche ; G. Gielen ; W. Sansen
Simulation Method to Extract Characteristics for Digital Wireless Communication Systems / L. Nguyen ; V. Janicot
Design of Low Power Systems I / 4B:
Microprocessor Power Analysis by Labelled Simulation / C. Hsieh ; L. Chen ; M. Pedram
Power Aware Microarchitecture Resource Scaling / A. Iyer ; D. Marculescu
Extending Lifetime of Portable Systems by Battery Scheduling / G. Castelli ; A. Macii ; E. Macii ; M. Poncino ; R. Scarsi
Test Generation and Evaluation / 4C:
Efficient Spectral Techniques for Sequential ATPG / A. Giani ; S. Sheng ; M. Hsiao ; V. Agrawal
On the Test of Microprocessor IP Cores / F. Corno ; M. Sonza Reorda ; S. Squillero ; M. Violante
Sequence Reordering to Improve the Levels of Compaction Achievable by Static Compaction Procedures / I. Pomeranz ; S. Reddy
SEU Effect Analysis in an Open-Source Router via a Distributed Fault Injection Environment / A. Benso ; G. Di Natale
Panel Session--The Programmable Platform: Does One Size Fit All? / 4E:
The Programmable Platform: Does One Size Fit All?
Planning Support / 4F:
Slicing Tree is a Complete Floorplan Representation / M. Lai ; D. Wong
Further Improve Circuit Partitioning Using GBAW Logic Perturbation Techniques / C. Cheung ; Y. Wu ; D. Cheng
Clustering Based Fast Clock Scheduling for Light Clock-Tree / M. Saitoh ; M. Azuma ; A. Takahashi
Low-Power Channel Decoding and VLIW Architectures / 5A:
Power-Efficient Layered Turbo Decoder Processor / J. Dielissen ; J. van Meerbergen ; M. Bekooij ; F. Harmsze ; S. Sawitzki ; J. Huisken ; A. van der Werf
Exploiting Data Forwarding to Reduce the Power Budget of VLIW Embedded Processors / M. Sami ; D. Sciuto ; C. Silvano ; V. Zaccaria ; R. Zafalon
Design of Low-Power High-Speed Maximum a priori Decoder Architectures / A. Worm ; H. Lamm ; N. Wehn
Design of Low-Power Systems II / 5B:
Low Complexity FIR Filters Using Factorization of Perturbed Coefficients / C. Neau ; K. Muhammad ; K. Roy
An Adaptive Algorithm for Low-Power Streaming Multimedia Processing / A. Acquaviva ; B. Ricco
A Static Power Estimation Methodology for IP-Based Design / X. Liu ; C. Papaefthymiou
On-Line Testing Techniques / 5C:
Optimization of Error Detecting Codes for the Detection of Crosstalk Originated Errors / M. Favalli ; C. Metra
System Safety through Automatic High-Level Code Transformations: An Experimental Evaluation / P. Cheynet ; B. Nicolescu ; R. Velazco ; M. Rebaudengo
From DFT to Systems Test--A Model Based Cost Optimization Tool / M. Wahl ; M. Rahman ; C. Maass ; T. Ambler
Efficient On-Line Testing Method for a Floating-Point Adder / A. Drozd ; M. Lobachev
Design Methodology for PicoRadio Networks / 5E:
EMC on Chip and High Density Package Level / J. da Silva Jr. ; J. Shamberger ; M. Ammer ; C. Guo ; S. Li ; R. Shah ; T. Tuan ; M. Sheets ; J. Rabaey ; B. Nikolic ; A. Sangiovanni-Vincentelli ; P. Wright5F:
High-Level Simulation of Substrate Noise Generation from Large Digital Circuits with Multiple Supplies / M. Badaroglu ; H. De Man ; M. van Heijningen ; V. Gravot
Crosstalk Noise in Future Digital CMOS Circuits / C. Werner ; R. Gottsche ; A. Worner ; U. Ramacher
Modeling Electromagnetic Emission of Integrated Circuits for System Analysis / P. Kralicek ; W. John ; H. Garbe
Analysis of EME Produced by a Microcontroller Operation / F. Fiori ; F. Musolino
Design Methods for Analog and Mixed Signal Circuits / 6A:
Top-Down Design of a xDSL 14-bit 4MS/s [Sigma] [Delta] Modulator in Digital CMOS Technology / R. del Rio ; J. de la Rosa ; F. Medeiro ; B. Perez-Verdu ; A. Rodriguez-Vazquez
Analog Design for Reuse--Case Study: Very Low-Voltage [Sigma] [Delta] Modulator / M. Dessouky ; M. Louerat ; A. Greiner ; A. Kaiser
A Design Strategy for Low-Voltage Low-Power Continuous-Time [Sigma] [Delta] A/D Converters / F. Gerfers ; Y. Manoli
Issues in Synthesis and Power Optimization / 6B:
Minimizing Stand-By Leakage Power in Static CMOS Circuits / S. Naidu ; E. Jacobs
In-Place Delay Constrained Power Optmization Using Functional Symmetries / C. Chang ; B. Hu ; M. Marek-Sadowska
High-Quality Sub-Function Construction in Functional Decomposition Based on Information Relationship Measures / L. Jozwiak ; A. Chojnacki
Generalized Reasoning Scheme for Redundancy Addition and Removal Logic Optimization / J. Espejo ; L. Entrena ; E. San Millan ; E. Olias
High Level Validation / 6C:
LPSAT: A Unified Approach to RTL Satisfiability / Z. Zeng ; P. Kalla ; M. Ciesielski
Functional Test Generation for Behaviorally Sequential Models / F. Ferrandi ; G. Ferrara ; A. Fin ; F. Fummi
High Quality Behavioral Verification Using Statistical Stopping Criteria / A. Hajjar ; T. Chen ; I. Munn ; A. Andrews ; M. Bjorkman
Hot Topic--Network Processors: A Perspective on Market Requirements, Processor Architectures and Embedded S/W Tools / 6E:
Network Processors: A Perspective on Market Requirements, Processor Architectures and Embedded S/W Tools / P. Paulin ; F. Karim ; P. Bromley
Interconnect Extraction and Modelling / 6F:
Efficient Inductance Extraction via Windowing / M. Beattie ; L. Pileggi
Efficient and Passive Modeling of Transmission Lines by Using Differential Quadrature Method / Q. Xu ; P. Mazumder
Explicit Formulas and Efficient Algorithm for Moment Computation of Coupled RC Trees with Lumped and Distributed Elements / Q. Yu ; E. Kuh
On the Impact of On-Chip Inductance on Signal Nets under the Influence of Power Grid Noise
Timing and Parallel Simulation / 7A:
Timing Simulation of Digital Circuits with Binary Decision Diagrams / R. Ubar ; A. Jutman
HALOTIS: High Accuracy LOgic TIming Simulator with Inertial and Degradation Delay Model / P. Vazquez ; J. Juan-Chico ; M. Bellido ; A. Acosta ; M. Valencia
dlbSIM--A Parallel Functional Logic Simulator Allowing Dynamic Load Balancing / K. Hering ; J. Loser ; J. Markwardt
Architecture Driven Partitioning / J. Kuter ; E. Barke
Embedded Tutorial--Low-Power Issues for SOCs / 7B:
Low-Power Systems on Chips (SOCs) / C. Piguet ; M. Renaudin ; T. Omnes
Defect Oriented Testing / 7C:
Static and Dynamic Behavior of Memory Cell Array Opens and Shorts in Embedded DRAMs / Z. Al-Ars ; A. van de Goor
Definitions of the Numbers of Detections of Target Faults and their Effectiveness in Guiding Test Generation for High Defect Coverage
CMOS Open Defect Detection by Supply Current Test / M. Hashizume ; M. Ichimiya ; H. Yotsuyanagi ; T. Tamesada
Full Chip False Timing Path Identification: Applications to the PowerPC Microprocessors / J. Zeng ; M. Abadir ; J. Bhadra ; J. Abraham
Embedded Tutorial--CAD for RF Integrated Circuits and Systems / 7E:
CAD for RF Circuits / J. Phillips ; J. Roychowdhury ; W. Eberle ; B. Yang ; D. Long ; A. Demir
Routing Enhancements / 7F:
Modeling Crosstalk Noise for Deep Submicron Verification Tools / P. Bazargan-Sabet ; F. Ilponse
A Graph Based Algorithm for Optimal Buffer Insertion under Accurate Delay Models / Y. Gao
Repeater Block Planning under Simultaneous Delay and Transition Time Constraints / P. Sarkar ; C. Koh
Layout Generation / 8A:
On-The-Fly Layout Generation for PTL Macrocells / L. Macchiarulo
Automatic Datapath Tile Placement and Routing / T. Serdar ; C. Sechen
A Boolean Satisfiability-Based Incremental Rerouting Approach with Application to FPGAs / G. Nam ; K. Sakallah ; R. Rutenbar
Modelling and Performance Analysis of Embedded Systems / 8B:
Dual Transitions Petri Net Based Modelling Technique for Embedded Systems Specification / M. Varea ; B. Al-Hashimi
Probabilistic Application Modeling for System-Level Performance Analysis / R. Marculescu
Reliable Estimation of Execution Time of Embedded Software / G. Martin ; E. Harcourt
Analog and Mixed Signal Testing / 8C:
Implementation of a Linear Histogram BIST for ADCs / F. Azais ; S. Bernard ; Y. Bertrand ; M. Renovell
Test Generation Based Diagnosis of Device Parameters for Analog Circuits / S. Cherubal ; A. Chatterjee
Generation of Optimum Test Stimuli for Nonlinear Analog Circuits Using Nonlinear Programming and Time-Domain Sensitivities / B. Burdiek
Panel Session--Managing the SoC Design Challenge with 'Soft' Hardware / 8E:
Managing the SoC Design Challenge with "Soft" Hardware / R. Wilson
Hardware-Software Architectures and Synthesis / 8F:
Integrated Hardware-Software Co-Synthesis and High-Level Synthesis for Design of Embedded Systems under Power and Latency Constraints / A. Doboli
Allocation and Scheduling of Conditional Task Graph in Hardware/Software Co-Synthesis / Y. Xie ; W. Wolf
Code Placement in Hardware Software Co-Synthesis to Improve Performance and Reduce Cost / S. Parameswaran
System-On-A-Chip Processor Synchronization Support in Hardware / B. Saglam ; V. Mooney III
Reconfigurable Computing I / 9A:
A Decade of Reconfigurable Computing: A Visionary Retrospective / R. Hartenstein
Hierarchical Memory Mapping during Synthesis in FPGA-Based Reconfigurable Computers / I. Ouaiss ; R. Vemuri
Optimal FPGA Module Placement with Temporal Precedence Constraints / S. Fekete ; E. Kohler ; J. Teich
Embedded Software / 9B:
Generation of Minimal Size Code for Schedule Graphs / C. Passerone ; Y. Watanabe ; L. Lavagno
Generating Production Quality Software Development Tools Using a Machine Description Language / A. Hoffmann ; A. Nohl ; S. Pees ; G. Braun ; H. Meyr
Automatic Generation and Targeting of Application Specific Operating Systems and Embedded Systems Software / L. Gauthier ; S. Yoo
Cache Conscious Data Layout Organization for Embedded Multimedia Applications / C. Kulkarni ; C. Ghez ; M. Miranda ; F. Catthoor
Panel Session--Design Challenges and Emerging EDA Solutions in Mixed-Signal IC Design / 9C:
Design Challenges and Emerging EDA Solutions in Mixed-Signal IC Design
Hot Topic--Game Processors / 9E:
CPU for PlayStation2 / H. Tago ; K. Hashimoto ; N. Ikumi ; M. Nagamatsu ; M. Suzuoki ; Y. Yamamoto
Implementation of the ATI Flipper Chip / A. Mandapati
SH-4 RISC Microprocessor for Multimedia, Game Machine / S. Narita
Decision Diagrams / 9F:
Streaming BDD Manipulation for Large-Scale Combinatorial Problems / S. Minato ; S. Ishihara
Binary Decision Diagram with Minimum Expected Path Length / Y. Liu ; K. Wang ; T. Hwang ; C. Liu
Spectral Decision Diagrams Using Graph Transformations / M. Thornton ; R. Drechsler
Friday Keynote Session--Electronic System Design Methodology: Europe's Positioning / 9L:
Electronic System Design Methodology: Europe's Positioning
Reconfigurable Computing II / 10A:
Precision and Error Analysis of MATLAB Applications during Automated Hardware Synthesis for FPGAs / A. Nayak ; M. Haldar ; A. Choudhary ; P. Banerjee
A HW/SW Partitioning Algorithm for Dynamically Reconfigurable Architectures / J. Noguera ; R. Badia
Managing Dynamic Reconfiguration Overhead in Systems-On-A-Chip Design Using Reconfigurable Datapaths and Optimized Interconnection Networks / Z. Huang ; S. Malik
Co-Simulation and System Verification Techniques / 10B:
Simulation-Guided Property Checking Based on a Multi-Valued AR-Automata
Performance Improvement of Multi-Processor Systems Cosimulation Based on SW Analysis / J. Jung ; K. Choi
Mixed-Level Cosimulation for Fine Gradual Refinement of Communication in SoC Design
A Framework for Fast Hardware-Software Co-Simulation / T. Kogel
Embedded Tutorial - Analog Methods and Tools for SoC Integration / 10C:
Analog/Mixed-Signal IP Modeling for Design Reuse / N. Madrid ; E. Peralias ; A. Rueda
A Skill-Based Library for Retargetable Embedded Analog Cores / X. Jingnan ; J. Vital ; N. Horta
Modelling SoC Devices for Virtual Test Using VHDL / M. Rona ; G. Krampl
Retargeting of Mixed-Signal Blocks for SoCs / R. Castro-Lopez ; F. Fernandez ; M. Delgado-Restituto
Panel Session--Standard Bus vs. Bus Wrapper: What is the Best Solution for Future SoC Integration? / 10E:
Standard Bus vs. Bus Wrapper: What is the Best Solution for Future SoC Integration?
Architectural Level Synthesis / 10F:
Access Pattern Based Local Memory Customization for Low Power Embedded Systems / P. Grun ; N. Dutt ; A. Nicolau
Static Memory Allocation by Pointer Analysis and Coloring
Heuristic Datapath Allocation for Multiple Wordlength Systems / G. Constantinides ; P. Cheung ; W. Luk
Poster Session
On the Verification of Synthesized Designs Using Automatically Generated Transformational Witnesses / E. Teica ; R. Radhakrishnan
Property-Specific Witness Graph Generation for Guided Simulation / A. Gupta ; A. Casavant ; P. Ashar ; S. Liu ; A. Mukaiyama ; K. Wakabayashi
Two Approaches for Developing Generic Components in VHDL / V. Stuikys ; G. Ziberkas ; R. Damasevicius ; G. Majauskas
Annotated Data Types for Addressed Token Passing Networks / G. Cichon ; W. Brunnbauer
Testability Trade-Offs for BIST RTL Data Paths: The Case for Three Dimensional Design Space / N. Nicolici
Towards a Better Understanding of Failure Modes and Test Requirements of ADCs / A. Lechner ; A. Richardson ; B. Hermes
Exact Fault Simulation for Systems on Silicon that Protects Each Core's Intellectual Property (IP) / M. Quasem ; S. Gupta
Using Mission Logic for Embedded Testing / R. Dorsch
A Regularity-Based Hierarchical Symbolic Analysis Method for Large-Scale Analog Networks
An Improved Hierarchical Classification Algorithm for Structural Analysis of Integrated Circuits / M. Olbrich ; A. Rein
Automatic Nonlinear Memory Power Modelling / E. Schmidt ; G. Jochens ; L. Kruse ; W. Nebel ; F. Theeuwen
An Operation Rearrangement Technique for Power Optimization in VLIW Instruction Fetch / D. Shin ; J. Kim ; N. Chang
A Pseudo Delay-Insensitive Timing Model to Synthesizing Low-Power Asynchronous Circuits / O. Garnica ; J. Lanchares ; R. Hermida
A Register-Transfer-Level Fault Simulator for Permanent and Transient Faults in Embedded Processors / C. Rousselle ; M. Pflanz ; A. Behling ; T. Mohaupt ; H. Vierhaus
Efficient Finite Field Digit-Serial Multiplier Architecture for Cryptography Applications / G. Bertoni ; L. Breveglieri ; P. Fragneto
Task Concurrency Management Methodology Summary / C. Wong ; P. Marchal ; P. Yang ; A. Prayati ; N. Cossement ; R. Lauwereins ; D. Verkest
Susceptibility of Analog Cells to Substrate Interference
Order Determination for Frequency Compensation of Negative-Feedback Systems / A. van Staveren ; C. Verhoeven
Minimizing the Number of Floating Bias Voltage Sources with Integer Linear Programming / E. Yildiz
CMOS Sizing Rule for High Performance Long Interconnects / G. Cappuccino ; G. Cocorullo
On Automatic Analysis of Geometrically Proximate Nets in VLSI Layout / S. Koranne ; O. Gangwal
AnalogRouter: A New Approach of Current-Driven Routing for Analog Circuits / J. Lienig ; G. Jerke ; T. Adler
A Hardware-Software Operating System for Heterogeneous Designs / J. Moya ; F. Moya ; J. Lopez
PRMDL: A Machine Description Language for Clustered VLIW Architectures / A. Terechko ; E. Pol ; J. van Eijndhoven
Functional Units with Conditional Input/Output Behavior in VLIW Processors / L. Engels ; N. Busa
Adaptation of an Event-Driven Simulation Environment to Sequentially Propagated Concurrent Fault Simulation / M. Zolfy ; S. Mirkhani ; Z. Navabi
Constraint Satisfaction for Storage Files with Fifos or Stacks during Scheduling / C. Alba Pinto ; B. Mesman ; K. van Eijk ; J. Jess
Index of Authors
DATE Executive Committee
Technical Program Chairs
Vendors Committee
2.

電子ブック

EB
Wolfgang Nebel, Association for Computing Machinery-Digital Library.
出版情報: ACM Digital Library Proceedings , 2006
所蔵情報: loading…
3.

電子ブック

EB
Wolfgang Nebel, Association for Computing Machinery-Digital Library.
出版情報: ACM Digital Library Proceedings , 2001
所蔵情報: loading…
目次情報: 続きを見る
DATE Executive Committee
Technical Program Chairs
Vendors Committee
DATE Sponsor Committee
Technical Program Committee
Reviewers
Welcome to DATE 2001
Best Paper Awards
Tutorials
Call for Papers DATE 2002
Plenary: Keynote Session
The Semiconductor Dynamic in the Information Age--Driving New Technologies, Trends and Markets / U. Schumacher, CEO
Complementary Approaches to Designing Correct Circuits / 1A:
Abstraction of Word-Level Linear Arithmetic Functions from Bit-Level Component Descriptions / P. Dasgupta ; P. Chakrabarti ; A. Nandi ; S. Krishna ; A. Chakrabarti
Biaising Symbolic Research by Means of Dynamic Activity Profiles / G. Cabodi ; P. Camurati ; S. Quer
New Design Methods with SystemC / 1B:
A Methodology for Interfacing Open Source SystemC with a Third Party Software / L. Charest ; M. Reid ; E. Aboulhamid ; G. Bois
Behavioral Synthesis with SystemC / G. Economakos ; P. Oikonomakos ; I. Panagopoulos ; I. Poulakis ; G. Papakonstantiou
SystemC[superscript SV]--An Extension of SystemC for Mixed Multi-Level Communication Modeling and Interface-Based System Design / R. Siegmund ; D. Muller
Embedded Tutorial--TRP: Integrating Embedded Test and ATE / 1C:
Test Resource Partitioning: A Design and Test Issue
Embedded Tutorial--Current Trends in the Design of Automotive Electronic Systems / 1E:
Current Trends in the Design of Automotive Electronic Systems
Platforms and IP-Based Design / 2A:
Component Selection and Matching for IP-Based Design / T. Zhang ; G. De Micheli ; L. Benini
A Universal Communication Model for an Automotive System Integration Platform / T. Demmeler ; P. Giusto
An Efficient Architecture Model for Systematic Design of Application-Specific Multiprocessor SoC / A. Baghdadi ; D. Lyonnard ; N. Zergainoh ; A. Jerraya
Approaching Semantics of Design Languages / 2B:
The Simulation Semantics of SystemC / J. Ruf ; D. Hoffmann ; J. Gerlach ; T. Kropf ; W. Rosenstiel ; W. Mueller
MetaRTL: Raising the Abstraction Level of RTL Design / J. Zhu
A Model for Describing Communication between Aggregate Objects in the Specification and Design of Embedded Systems / K. Svarstad ; G. Nicolescu
BIST and Diagnosis / 2C:
Circuit Partitioning for Efficient Logic BIST Synthesis / A. Irion ; G. Kiefer ; H. Vranken ; H. Wunderlich
Deterministic Software-Based Self-Testing of Embedded Processor Cores / A. Paschalis ; D. Gizopoulos ; N. Kranitis ; M. Psarakis ; Y. Zorian
Memory Fault Diagnosis by Syndrome Compression / J. Li ; C. Wu
Diagnosis for Scan-Based BIST: Reaching Deep into the Signatures / I. Bayraktaroglu ; A. Orailoglu
Hot Topic--EUCAR Session / 2E:
Vehicle Electric/Electronic Architecture--One of the Most Important Challenges for OEM's / G. Hettich ; T. Thurner
SAT Based Verification Techniques / 3A:
Using SAT for Combinational Equivalence Checking / E. Goldberg ; M. Prasad ; R. Brayton
Combinational Equivalence Checking Using Boolean Satisfiability and Binary Decision Diagrams / S. Reda ; A. Salem
An Efficient Learning Procedure for Multiple Implication Checks / Y. Novikov
Panel Session--C/C[superscript ++]: Progress or Deadlock in SLD Specification? / 3B:
C/C[superscript ++]: Progress or Deadlock in System-Level Specification
Advances in SoC Testing / 3C:
An Integrated System-On-Chip Test Framework / E. Larsson ; Z. Peng
Efficient Test Data Compression and Decompression for System-On-A-Chip Using Integral Scan Chains and Golomb Coding / A. Chandra ; K. Chakrabarty
Testing TAPed Cores and Wrapped Cores with the Same Test Access Mechanism / M. Benabdenbi ; W. Maroufi ; M. Marzouki
On Applying the Set Covering Model to Reseeding / S. Chiusano ; S. Di Carlo ; P. Prinetto
Panel Session--Data Management--Limiter or Accelerator for Electronic Design Creativity? / 3E:
Data Management--Limiter or Accelerator for Electronic Design Creativity
Analysis of Communication Systems / 4A:
Efficient Bit-Error-Rate Estimation of Multicarrier Transceivers / G. Vandersteen ; P. Wambacq ; S. Donnay ; M. Engels ; I. Bolsens ; Y. Rolain ; J. Schoukens
Efficient Time-Domain Simulation of Telecom Frontends Using a Complex Damped Exponential Signal Model / P. Vanassche ; G. Gielen ; W. Sansen
Simulation Method to Extract Characteristics for Digital Wireless Communication Systems / L. Nguyen ; V. Janicot
Design of Low Power Systems I / 4B:
Microprocessor Power Analysis by Labelled Simulation / C. Hsieh ; L. Chen ; M. Pedram
Power Aware Microarchitecture Resource Scaling / A. Iyer ; D. Marculescu
Extending Lifetime of Portable Systems by Battery Scheduling / G. Castelli ; A. Macii ; E. Macii ; M. Poncino ; R. Scarsi
Test Generation and Evaluation / 4C:
Efficient Spectral Techniques for Sequential ATPG / A. Giani ; S. Sheng ; M. Hsiao ; V. Agrawal
On the Test of Microprocessor IP Cores / F. Corno ; M. Sonza Reorda ; S. Squillero ; M. Violante
Sequence Reordering to Improve the Levels of Compaction Achievable by Static Compaction Procedures / I. Pomeranz ; S. Reddy
SEU Effect Analysis in an Open-Source Router via a Distributed Fault Injection Environment / A. Benso ; G. Di Natale
Panel Session--The Programmable Platform: Does One Size Fit All? / 4E:
The Programmable Platform: Does One Size Fit All?
Planning Support / 4F:
Slicing Tree is a Complete Floorplan Representation / M. Lai ; D. Wong
Further Improve Circuit Partitioning Using GBAW Logic Perturbation Techniques / C. Cheung ; Y. Wu ; D. Cheng
Clustering Based Fast Clock Scheduling for Light Clock-Tree / M. Saitoh ; M. Azuma ; A. Takahashi
Low-Power Channel Decoding and VLIW Architectures / 5A:
Power-Efficient Layered Turbo Decoder Processor / J. Dielissen ; J. van Meerbergen ; M. Bekooij ; F. Harmsze ; S. Sawitzki ; J. Huisken ; A. van der Werf
Exploiting Data Forwarding to Reduce the Power Budget of VLIW Embedded Processors / M. Sami ; D. Sciuto ; C. Silvano ; V. Zaccaria ; R. Zafalon
Design of Low-Power High-Speed Maximum a priori Decoder Architectures / A. Worm ; H. Lamm ; N. Wehn
Design of Low-Power Systems II / 5B:
Low Complexity FIR Filters Using Factorization of Perturbed Coefficients / C. Neau ; K. Muhammad ; K. Roy
An Adaptive Algorithm for Low-Power Streaming Multimedia Processing / A. Acquaviva ; B. Ricco
A Static Power Estimation Methodology for IP-Based Design / X. Liu ; C. Papaefthymiou
On-Line Testing Techniques / 5C:
Optimization of Error Detecting Codes for the Detection of Crosstalk Originated Errors / M. Favalli ; C. Metra
System Safety through Automatic High-Level Code Transformations: An Experimental Evaluation / P. Cheynet ; B. Nicolescu ; R. Velazco ; M. Rebaudengo
From DFT to Systems Test--A Model Based Cost Optimization Tool / M. Wahl ; M. Rahman ; C. Maass ; T. Ambler
Efficient On-Line Testing Method for a Floating-Point Adder / A. Drozd ; M. Lobachev
Design Methodology for PicoRadio Networks / 5E:
EMC on Chip and High Density Package Level / J. da Silva Jr. ; J. Shamberger ; M. Ammer ; C. Guo ; S. Li ; R. Shah ; T. Tuan ; M. Sheets ; J. Rabaey ; B. Nikolic ; A. Sangiovanni-Vincentelli ; P. Wright5F:
High-Level Simulation of Substrate Noise Generation from Large Digital Circuits with Multiple Supplies / M. Badaroglu ; H. De Man ; M. van Heijningen ; V. Gravot
Crosstalk Noise in Future Digital CMOS Circuits / C. Werner ; R. Gottsche ; A. Worner ; U. Ramacher
Modeling Electromagnetic Emission of Integrated Circuits for System Analysis / P. Kralicek ; W. John ; H. Garbe
Analysis of EME Produced by a Microcontroller Operation / F. Fiori ; F. Musolino
Design Methods for Analog and Mixed Signal Circuits / 6A:
Top-Down Design of a xDSL 14-bit 4MS/s [Sigma] [Delta] Modulator in Digital CMOS Technology / R. del Rio ; J. de la Rosa ; F. Medeiro ; B. Perez-Verdu ; A. Rodriguez-Vazquez
Analog Design for Reuse--Case Study: Very Low-Voltage [Sigma] [Delta] Modulator / M. Dessouky ; M. Louerat ; A. Greiner ; A. Kaiser
A Design Strategy for Low-Voltage Low-Power Continuous-Time [Sigma] [Delta] A/D Converters / F. Gerfers ; Y. Manoli
Issues in Synthesis and Power Optimization / 6B:
Minimizing Stand-By Leakage Power in Static CMOS Circuits / S. Naidu ; E. Jacobs
In-Place Delay Constrained Power Optmization Using Functional Symmetries / C. Chang ; B. Hu ; M. Marek-Sadowska
High-Quality Sub-Function Construction in Functional Decomposition Based on Information Relationship Measures / L. Jozwiak ; A. Chojnacki
Generalized Reasoning Scheme for Redundancy Addition and Removal Logic Optimization / J. Espejo ; L. Entrena ; E. San Millan ; E. Olias
High Level Validation / 6C:
LPSAT: A Unified Approach to RTL Satisfiability / Z. Zeng ; P. Kalla ; M. Ciesielski
Functional Test Generation for Behaviorally Sequential Models / F. Ferrandi ; G. Ferrara ; A. Fin ; F. Fummi
High Quality Behavioral Verification Using Statistical Stopping Criteria / A. Hajjar ; T. Chen ; I. Munn ; A. Andrews ; M. Bjorkman
Hot Topic--Network Processors: A Perspective on Market Requirements, Processor Architectures and Embedded S/W Tools / 6E:
Network Processors: A Perspective on Market Requirements, Processor Architectures and Embedded S/W Tools / P. Paulin ; F. Karim ; P. Bromley
Interconnect Extraction and Modelling / 6F:
Efficient Inductance Extraction via Windowing / M. Beattie ; L. Pileggi
Efficient and Passive Modeling of Transmission Lines by Using Differential Quadrature Method / Q. Xu ; P. Mazumder
Explicit Formulas and Efficient Algorithm for Moment Computation of Coupled RC Trees with Lumped and Distributed Elements / Q. Yu ; E. Kuh
On the Impact of On-Chip Inductance on Signal Nets under the Influence of Power Grid Noise
Timing and Parallel Simulation / 7A:
Timing Simulation of Digital Circuits with Binary Decision Diagrams / R. Ubar ; A. Jutman
HALOTIS: High Accuracy LOgic TIming Simulator with Inertial and Degradation Delay Model / P. Vazquez ; J. Juan-Chico ; M. Bellido ; A. Acosta ; M. Valencia
dlbSIM--A Parallel Functional Logic Simulator Allowing Dynamic Load Balancing / K. Hering ; J. Loser ; J. Markwardt
Architecture Driven Partitioning / J. Kuter ; E. Barke
Embedded Tutorial--Low-Power Issues for SOCs / 7B:
Low-Power Systems on Chips (SOCs) / C. Piguet ; M. Renaudin ; T. Omnes
Defect Oriented Testing / 7C:
Static and Dynamic Behavior of Memory Cell Array Opens and Shorts in Embedded DRAMs / Z. Al-Ars ; A. van de Goor
Definitions of the Numbers of Detections of Target Faults and their Effectiveness in Guiding Test Generation for High Defect Coverage
CMOS Open Defect Detection by Supply Current Test / M. Hashizume ; M. Ichimiya ; H. Yotsuyanagi ; T. Tamesada
Full Chip False Timing Path Identification: Applications to the PowerPC Microprocessors / J. Zeng ; M. Abadir ; J. Bhadra ; J. Abraham
Embedded Tutorial--CAD for RF Integrated Circuits and Systems / 7E:
CAD for RF Circuits / J. Phillips ; J. Roychowdhury ; W. Eberle ; B. Yang ; D. Long ; A. Demir
Routing Enhancements / 7F:
Modeling Crosstalk Noise for Deep Submicron Verification Tools / P. Bazargan-Sabet ; F. Ilponse
A Graph Based Algorithm for Optimal Buffer Insertion under Accurate Delay Models / Y. Gao
Repeater Block Planning under Simultaneous Delay and Transition Time Constraints / P. Sarkar ; C. Koh
Layout Generation / 8A:
On-The-Fly Layout Generation for PTL Macrocells / L. Macchiarulo
Automatic Datapath Tile Placement and Routing / T. Serdar ; C. Sechen
A Boolean Satisfiability-Based Incremental Rerouting Approach with Application to FPGAs / G. Nam ; K. Sakallah ; R. Rutenbar
Modelling and Performance Analysis of Embedded Systems / 8B:
Dual Transitions Petri Net Based Modelling Technique for Embedded Systems Specification / M. Varea ; B. Al-Hashimi
Probabilistic Application Modeling for System-Level Performance Analysis / R. Marculescu
Reliable Estimation of Execution Time of Embedded Software / G. Martin ; E. Harcourt
Analog and Mixed Signal Testing / 8C:
Implementation of a Linear Histogram BIST for ADCs / F. Azais ; S. Bernard ; Y. Bertrand ; M. Renovell
Test Generation Based Diagnosis of Device Parameters for Analog Circuits / S. Cherubal ; A. Chatterjee
Generation of Optimum Test Stimuli for Nonlinear Analog Circuits Using Nonlinear Programming and Time-Domain Sensitivities / B. Burdiek
Panel Session--Managing the SoC Design Challenge with 'Soft' Hardware / 8E:
Managing the SoC Design Challenge with "Soft" Hardware / R. Wilson
Hardware-Software Architectures and Synthesis / 8F:
Integrated Hardware-Software Co-Synthesis and High-Level Synthesis for Design of Embedded Systems under Power and Latency Constraints / A. Doboli
Allocation and Scheduling of Conditional Task Graph in Hardware/Software Co-Synthesis / Y. Xie ; W. Wolf
Code Placement in Hardware Software Co-Synthesis to Improve Performance and Reduce Cost / S. Parameswaran
System-On-A-Chip Processor Synchronization Support in Hardware / B. Saglam ; V. Mooney III
Reconfigurable Computing I / 9A:
A Decade of Reconfigurable Computing: A Visionary Retrospective / R. Hartenstein
Hierarchical Memory Mapping during Synthesis in FPGA-Based Reconfigurable Computers / I. Ouaiss ; R. Vemuri
Optimal FPGA Module Placement with Temporal Precedence Constraints / S. Fekete ; E. Kohler ; J. Teich
Embedded Software / 9B:
Generation of Minimal Size Code for Schedule Graphs / C. Passerone ; Y. Watanabe ; L. Lavagno
Generating Production Quality Software Development Tools Using a Machine Description Language / A. Hoffmann ; A. Nohl ; S. Pees ; G. Braun ; H. Meyr
Automatic Generation and Targeting of Application Specific Operating Systems and Embedded Systems Software / L. Gauthier ; S. Yoo
Cache Conscious Data Layout Organization for Embedded Multimedia Applications / C. Kulkarni ; C. Ghez ; M. Miranda ; F. Catthoor
Panel Session--Design Challenges and Emerging EDA Solutions in Mixed-Signal IC Design / 9C:
Design Challenges and Emerging EDA Solutions in Mixed-Signal IC Design
Hot Topic--Game Processors / 9E:
CPU for PlayStation2 / H. Tago ; K. Hashimoto ; N. Ikumi ; M. Nagamatsu ; M. Suzuoki ; Y. Yamamoto
Implementation of the ATI Flipper Chip / A. Mandapati
SH-4 RISC Microprocessor for Multimedia, Game Machine / S. Narita
Decision Diagrams / 9F:
Streaming BDD Manipulation for Large-Scale Combinatorial Problems / S. Minato ; S. Ishihara
Binary Decision Diagram with Minimum Expected Path Length / Y. Liu ; K. Wang ; T. Hwang ; C. Liu
Spectral Decision Diagrams Using Graph Transformations / M. Thornton ; R. Drechsler
Friday Keynote Session--Electronic System Design Methodology: Europe's Positioning / 9L:
Electronic System Design Methodology: Europe's Positioning
Reconfigurable Computing II / 10A:
Precision and Error Analysis of MATLAB Applications during Automated Hardware Synthesis for FPGAs / A. Nayak ; M. Haldar ; A. Choudhary ; P. Banerjee
A HW/SW Partitioning Algorithm for Dynamically Reconfigurable Architectures / J. Noguera ; R. Badia
Managing Dynamic Reconfiguration Overhead in Systems-On-A-Chip Design Using Reconfigurable Datapaths and Optimized Interconnection Networks / Z. Huang ; S. Malik
Co-Simulation and System Verification Techniques / 10B:
Simulation-Guided Property Checking Based on a Multi-Valued AR-Automata
Performance Improvement of Multi-Processor Systems Cosimulation Based on SW Analysis / J. Jung ; K. Choi
Mixed-Level Cosimulation for Fine Gradual Refinement of Communication in SoC Design
A Framework for Fast Hardware-Software Co-Simulation / T. Kogel
Embedded Tutorial - Analog Methods and Tools for SoC Integration / 10C:
Analog/Mixed-Signal IP Modeling for Design Reuse / N. Madrid ; E. Peralias ; A. Rueda
A Skill-Based Library for Retargetable Embedded Analog Cores / X. Jingnan ; J. Vital ; N. Horta
Modelling SoC Devices for Virtual Test Using VHDL / M. Rona ; G. Krampl
Retargeting of Mixed-Signal Blocks for SoCs / R. Castro-Lopez ; F. Fernandez ; M. Delgado-Restituto
Panel Session--Standard Bus vs. Bus Wrapper: What is the Best Solution for Future SoC Integration? / 10E:
Standard Bus vs. Bus Wrapper: What is the Best Solution for Future SoC Integration?
Architectural Level Synthesis / 10F:
Access Pattern Based Local Memory Customization for Low Power Embedded Systems / P. Grun ; N. Dutt ; A. Nicolau
Static Memory Allocation by Pointer Analysis and Coloring
Heuristic Datapath Allocation for Multiple Wordlength Systems / G. Constantinides ; P. Cheung ; W. Luk
Poster Session
On the Verification of Synthesized Designs Using Automatically Generated Transformational Witnesses / E. Teica ; R. Radhakrishnan
Property-Specific Witness Graph Generation for Guided Simulation / A. Gupta ; A. Casavant ; P. Ashar ; S. Liu ; A. Mukaiyama ; K. Wakabayashi
Two Approaches for Developing Generic Components in VHDL / V. Stuikys ; G. Ziberkas ; R. Damasevicius ; G. Majauskas
Annotated Data Types for Addressed Token Passing Networks / G. Cichon ; W. Brunnbauer
Testability Trade-Offs for BIST RTL Data Paths: The Case for Three Dimensional Design Space / N. Nicolici
Towards a Better Understanding of Failure Modes and Test Requirements of ADCs / A. Lechner ; A. Richardson ; B. Hermes
Exact Fault Simulation for Systems on Silicon that Protects Each Core's Intellectual Property (IP) / M. Quasem ; S. Gupta
Using Mission Logic for Embedded Testing / R. Dorsch
A Regularity-Based Hierarchical Symbolic Analysis Method for Large-Scale Analog Networks
An Improved Hierarchical Classification Algorithm for Structural Analysis of Integrated Circuits / M. Olbrich ; A. Rein
Automatic Nonlinear Memory Power Modelling / E. Schmidt ; G. Jochens ; L. Kruse ; W. Nebel ; F. Theeuwen
An Operation Rearrangement Technique for Power Optimization in VLIW Instruction Fetch / D. Shin ; J. Kim ; N. Chang
A Pseudo Delay-Insensitive Timing Model to Synthesizing Low-Power Asynchronous Circuits / O. Garnica ; J. Lanchares ; R. Hermida
A Register-Transfer-Level Fault Simulator for Permanent and Transient Faults in Embedded Processors / C. Rousselle ; M. Pflanz ; A. Behling ; T. Mohaupt ; H. Vierhaus
Efficient Finite Field Digit-Serial Multiplier Architecture for Cryptography Applications / G. Bertoni ; L. Breveglieri ; P. Fragneto
Task Concurrency Management Methodology Summary / C. Wong ; P. Marchal ; P. Yang ; A. Prayati ; N. Cossement ; R. Lauwereins ; D. Verkest
Susceptibility of Analog Cells to Substrate Interference
Order Determination for Frequency Compensation of Negative-Feedback Systems / A. van Staveren ; C. Verhoeven
Minimizing the Number of Floating Bias Voltage Sources with Integer Linear Programming / E. Yildiz
CMOS Sizing Rule for High Performance Long Interconnects / G. Cappuccino ; G. Cocorullo
On Automatic Analysis of Geometrically Proximate Nets in VLSI Layout / S. Koranne ; O. Gangwal
AnalogRouter: A New Approach of Current-Driven Routing for Analog Circuits / J. Lienig ; G. Jerke ; T. Adler
A Hardware-Software Operating System for Heterogeneous Designs / J. Moya ; F. Moya ; J. Lopez
PRMDL: A Machine Description Language for Clustered VLIW Architectures / A. Terechko ; E. Pol ; J. van Eijndhoven
Functional Units with Conditional Input/Output Behavior in VLIW Processors / L. Engels ; N. Busa
Adaptation of an Event-Driven Simulation Environment to Sequentially Propagated Concurrent Fault Simulation / M. Zolfy ; S. Mirkhani ; Z. Navabi
Constraint Satisfaction for Storage Files with Fifos or Stacks during Scheduling / C. Alba Pinto ; B. Mesman ; K. van Eijk ; J. Jess
Index of Authors
DATE Executive Committee
Technical Program Chairs
Vendors Committee
4.

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Wolfgang Nebel, Association for Computing Machinery-Digital Library.
出版情報: IEEE/IET Electronic Library (IEL) Conference Proceedings , 2006
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