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電子ブック

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Yale Patt, Association for Computing Machinery-Digital Library.
出版情報: IEEE/IET Electronic Library (IEL) Conference Proceedings , 2002
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目次情報: 続きを見る
Message from the General Chair
Message from the Program Chair
Organizing Committee
Steering Committee
Program Committee
Reviewers
Welcoming Remarks
Keynote Address / Burton J. Smith
Processor Pipelines / Session 1:
The Optimum Pipeline Depth for a Microprocessor / A. Hartstein ; T. Puzak
The Optimal Logic Depth per Pipeline Stage Is 6 to 8 FO4 Inverter Delays / M. Hrishikesh ; N. Jouppi ; K. Farkas ; D. Burger ; S. Keckler ; P. Shivakumar
Increasing Processor Performance by Implementing Deeper Pipelines / E. Sprangle ; D. Carmean
Processor Scheduling / Session 2:
Efficient Dynamic Scheduling through Tag Elimination / D. Ernst ; T. Austin
Slack: Maximizing Performance under Technological Constraints / B. Fields ; R. Bodik ; M. Hill
A Large, Fast Instruction Window for Tolerating Cache Misses / A. Lebeck ; J. Koppanalil ; T. Li ; J. Patwardhan ; E. Rotenberg
An Instruction Set and Microarchitecture for Instruction Level Distributed Processing / H.-S. Kim ; J. Smith
Safety and Reliability / Robert P. ColwellSession 3:
Transient-Fault Recovery Using Simultaneous Multithreading / T. Vijaykumar ; I. Pomeranz ; K. Cheng
Detailed Design and Evaluation of Redundant Multithreading Alternatives / S. Mukherjee ; M. Kontz ; S. Reinhardt
ReVive: Cost-Effective Architectural Support for Rollback Recovery in Shared-Memory Multiprocessors / M. Prvulovic ; Z. Zhang ; J. Torrellas
SafetyNet: Improving the Availability of Shared Memory Multiprocessors with Global Checkpoint/Recovery / D. Sorin ; M. Martin ; D. Wood
Power Aware Architecture / Session 4:
Dynamic Fine-Grain Leakage Reduction Using Leakage-Biased Bitlines / S. Heo ; K. Barr ; M. Hampton ; K. Asanovic
Drowsy Caches: Simple Techniques for Reducing Leakage Power / K. Flautner ; N. Kim ; S. Martin ; D. Blaauw ; T. Mudge
Power and Performance Evaluation of Globally Asynchronous Locally Synchronous Processors / A. Iyer ; D. Marculescu
Memory Systems / Session 5:
Using a User-Level Memory Thread for Correlation Prefetching / Y. Solihin ; J. Lee
Avoiding Initialization Misses to the Heap / J. Lewis ; B. Black ; M. Lipasti
Going the Distance for TLB Prefetching: An Application-Driven Study / G. Kandiraju ; A. Sivasubramaniam
Dynamic Optimization / Session 6:
Timekeeping in the Memory System: Predicting and Optimizing Memory Behavior / Z. Hu ; S. Kaxiras ; M. Martonosi
Implementing Optimizations at Decode Time / I. Kim
Managing Multi-configuration Hardware via Dynamic Working Set Analysis / A. Dhodapkar
Data and Storage Networks / Session 7:
Queue Pair IP: A Hybrid Architecture for System Area Networks / P. Buonadonna ; D. Culler
Experiences with VI Communication for Database Storage / Y. Zhou ; A. Bilas ; S. Jagannathan ; C. Dubnicki ; J. Philbin ; K. Li
Vector Architectures / Session 8:
Speculative Dynamic Vectorization / A. Pajuelo ; A. Gonzalez ; M. Valero
Tarantula: A Vector Extension to the Alpha Architecture / R. Espasa ; F. Ardanaz ; J. Emer ; S. Felix ; J. Gago ; R. Gramunt ; I. Hernandez ; T. Juan ; G. Lowney ; M. Mattina ; A. Seznec
Supporting Deep Speculation / Session 9:
Design Tradeoffs for the Alpha EV8 Conditional Branch Predictor / V. Krishnan ; Y. Sazeides
Difficult-Path Branch Prediction Using Subordinate Microthreads / R. Chappell ; F. Tseng ; A. Yoaz ; Y. Patt
A Scalable Instruction Queue Design Using Dependence Chains / S. Raasch ; N. Binkert
Author Index
Message from the General Chair
Message from the Program Chair
Organizing Committee
2.

電子ブック

EB
Yale Patt, Association for Computing Machinery-Digital Library.
出版情報: ACM Digital Library Proceedings , 2001
所蔵情報: loading…
目次情報: 続きを見る
Message from the General Chair
Message from the Program Chairs
Committees
Reviewers
Keynote
Fifty Years of Microarchitecture / H. Cragon
Novel Ideas / Session 1:
Skipper: A Microarchitecture for Exploiting Control-Flow Independence / C. Cher ; T. Vijaykumar
Performance Characterization of a Hardware Mechanism for Dynamic Optimization / B. Fahs ; S. Bose ; M. Crum ; B. Slechta ; F. Spadini ; T. Tung ; S. Patel ; S. Lumetta
Using Variable-MHz Microprocessors to Efficiently Handle Uncertainty in Real-Time Systems / E. Rotenberg
A Design Space Evaluation of Grid Processor Architectures / R. Nagarajan ; K. Sankaralingam ; D. Burger ; S. Keckler
Memory Hierarchies / Session 2:
Reducing Set-Associative Cache Energy via Way-Prediction and Selective Direct-Mapping / M. Powell ; A. Agrawal ; B. Falsafi ; K. Roy
A Code Decompression Architecture for VLIW Processors / Y. Xie ; W. Wolf ; H. Lekatsas
Direct Load: Dependence-Linked Dataflow Resolution of Load Address and Cache Coordinate / B. Chung ; J. Zhang ; J. Peir ; S. Lai ; K. Lai
Energy Efficient Architectures / Session 3:
Reducing Power Requirements of Instruction Scheduling through Dynamic Allocation of Multiple Datapath Resources / D. Ponomarev ; G. Kucuk ; K. Ghose
Exploiting VLIW Schedule Slacks for Dynamic and Leakage Energy Reduction / W. Zhang ; N. Vijaykrishnan ; M. Kandemir ; M. Irwin ; D. Duarte ; Y. Tsai
Reducing Power with Dynamic Critical Path Information / J. Seng ; E. Tune ; D. Tullsen
Direct Addressed Caches for Reduced Power Consumption / E. Witchel ; S. Larsen ; C. Ananian ; K. Asanovic
Emerging Applications for the Connected Home / A. Wolfe
Modulo Scheduling / Session 4:
Modulo Schedule Buffers / M. Merten ; W. Hwu
Graph-Partitioning Based Instruction Scheduling for Clustered Processors / A. Aleta ; J. Codina ; J. Sanchez ; A. Gonzalez
Modulo Scheduling with Integrated Register Spilling for Clustered VLIW Architectures / J. Zalamea ; J. Llosa ; E. Ayguade ; M. Valero
Compilation / Session 5:
Efficient Static Single Assignment Form for Predication / A. Stoutchinin ; F. de Ferriere
The Impact of If-Conversion and Branch Prediction on Program Execution on the Intel Itanium Processor / Y. Choi ; A. Knies ; L. Gerke ; T. Ngai
Mapping Reference Code to Irregular DSPs within the Retargetable, Optimizing Compiler COGEN(T) / G. Grewal ; C. Wilson
Superscalar Architectures / Session 6:
Select-Free Instruction Scheduling Logic / M. Brown ; J. Stark ; Y. Patt
Dual Use of Superscalar Datapath for Transient-Fault Detection and Recovery / J. Ray ; J. Hoe
A High-Speed Dynamic Instruction Scheduling Scheme for Superscalar Processors / M. Goshima ; K. Nishino ; Y. Nakashima ; S. Mori ; T. Kitamura ; S. Tomita
Reducing the Complexity of the Register File in Dynamic Superscalar Processors / R. Balasubramonian ; S. Dwarkadas ; D. Albonesi
Multimedia and Graphics / Session 7:
Saving Energy with Architectural and Frequency Adaptations for Multimedia Applications / C. Hughes ; J. Srinivasan ; S. Adve
Enhancing Loop Buffering of Media and Telecommunications Applications using Low-Overhead Predication / J. Sias ; H. Hunter
Cool-Cache for Hot Multimedia / O. Unsal ; R. Ashok ; I. Koren ; C. Krishna ; C. Moritz
ZR: A 3D API Transparent Technology for Chunk Rendering / E. Hsieh ; V. Pentkovski ; T. Piazza
Multithreading and Value Prediction / Session 8:
Speculative Lock Elision: Enabling Highly Concurrent Multithreaded Execution / R. Rajwar ; J. Goodman
Dynamic Speculative Precomputation / J. Collins ; H. Wang ; J. Shen
Handling Long-latency Loads in a Simultaneous Multithreading Processor / J. Brown
Correctly Implementing Value Prediction in Microprocessors that Support Multithreading or Multiprocessing / M. Martin ; D. Sorin ; H. Cain ; M. Hill ; M. Lipasti
Index of Authors
Message from the General Chair
Message from the Program Chairs
Committees
3.

電子ブック

EB
Yale Patt, Association for Computing Machinery-Digital Library.
出版情報: ACM Digital Library Proceedings , 2002
所蔵情報: loading…
目次情報: 続きを見る
Message from the General Chair
Message from the Program Chair
Organizing Committee
Steering Committee
Program Committee
Reviewers
Welcoming Remarks
Keynote Address / Burton J. Smith
Processor Pipelines / Session 1:
The Optimum Pipeline Depth for a Microprocessor / A. Hartstein ; T. Puzak
The Optimal Logic Depth per Pipeline Stage Is 6 to 8 FO4 Inverter Delays / M. Hrishikesh ; N. Jouppi ; K. Farkas ; D. Burger ; S. Keckler ; P. Shivakumar
Increasing Processor Performance by Implementing Deeper Pipelines / E. Sprangle ; D. Carmean
Processor Scheduling / Session 2:
Efficient Dynamic Scheduling through Tag Elimination / D. Ernst ; T. Austin
Slack: Maximizing Performance under Technological Constraints / B. Fields ; R. Bodik ; M. Hill
A Large, Fast Instruction Window for Tolerating Cache Misses / A. Lebeck ; J. Koppanalil ; T. Li ; J. Patwardhan ; E. Rotenberg
An Instruction Set and Microarchitecture for Instruction Level Distributed Processing / H.-S. Kim ; J. Smith
Safety and Reliability / Robert P. ColwellSession 3:
Transient-Fault Recovery Using Simultaneous Multithreading / T. Vijaykumar ; I. Pomeranz ; K. Cheng
Detailed Design and Evaluation of Redundant Multithreading Alternatives / S. Mukherjee ; M. Kontz ; S. Reinhardt
ReVive: Cost-Effective Architectural Support for Rollback Recovery in Shared-Memory Multiprocessors / M. Prvulovic ; Z. Zhang ; J. Torrellas
SafetyNet: Improving the Availability of Shared Memory Multiprocessors with Global Checkpoint/Recovery / D. Sorin ; M. Martin ; D. Wood
Power Aware Architecture / Session 4:
Dynamic Fine-Grain Leakage Reduction Using Leakage-Biased Bitlines / S. Heo ; K. Barr ; M. Hampton ; K. Asanovic
Drowsy Caches: Simple Techniques for Reducing Leakage Power / K. Flautner ; N. Kim ; S. Martin ; D. Blaauw ; T. Mudge
Power and Performance Evaluation of Globally Asynchronous Locally Synchronous Processors / A. Iyer ; D. Marculescu
Memory Systems / Session 5:
Using a User-Level Memory Thread for Correlation Prefetching / Y. Solihin ; J. Lee
Avoiding Initialization Misses to the Heap / J. Lewis ; B. Black ; M. Lipasti
Going the Distance for TLB Prefetching: An Application-Driven Study / G. Kandiraju ; A. Sivasubramaniam
Dynamic Optimization / Session 6:
Timekeeping in the Memory System: Predicting and Optimizing Memory Behavior / Z. Hu ; S. Kaxiras ; M. Martonosi
Implementing Optimizations at Decode Time / I. Kim
Managing Multi-configuration Hardware via Dynamic Working Set Analysis / A. Dhodapkar
Data and Storage Networks / Session 7:
Queue Pair IP: A Hybrid Architecture for System Area Networks / P. Buonadonna ; D. Culler
Experiences with VI Communication for Database Storage / Y. Zhou ; A. Bilas ; S. Jagannathan ; C. Dubnicki ; J. Philbin ; K. Li
Vector Architectures / Session 8:
Speculative Dynamic Vectorization / A. Pajuelo ; A. Gonzalez ; M. Valero
Tarantula: A Vector Extension to the Alpha Architecture / R. Espasa ; F. Ardanaz ; J. Emer ; S. Felix ; J. Gago ; R. Gramunt ; I. Hernandez ; T. Juan ; G. Lowney ; M. Mattina ; A. Seznec
Supporting Deep Speculation / Session 9:
Design Tradeoffs for the Alpha EV8 Conditional Branch Predictor / V. Krishnan ; Y. Sazeides
Difficult-Path Branch Prediction Using Subordinate Microthreads / R. Chappell ; F. Tseng ; A. Yoaz ; Y. Patt
A Scalable Instruction Queue Design Using Dependence Chains / S. Raasch ; N. Binkert
Author Index
Message from the General Chair
Message from the Program Chair
Organizing Committee
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