| Symposium Chairman's Welcome |
| Message from the Program Chair |
| Committee Members |
| Thermal and Energy-Aware Microarchitectures / Session 1： |
| Temperature-Aware Microarchitecture / K. Skadron ; M. Stan ; W. Huang ; S. Velusamy ; K. Sankaranarayanan ; D. Tarjan |
| Profile-Based Dynamic Voltage and Frequency Scaling for a Multiple Clock Domain Microprocessor / G. Magklis ; M. Scott ; G. Semeraro ; D. Albonesi ; S. Dropsho |
| Processor Architecture / Session 2： |
| Half-Price Architecture / I. Kim ; M. Lipasti |
| Implicitly-Multithreaded Processors / I. Park ; B. Falsafi ; T. Vijaykumar |
| Panel: Subsetting SPEC When Measuring Results: Valid or Manipulative? |
| MisSPECulation: Partial and Misleading Use of SPEC CPU2000 in Computer Architecture Conferences / D. Citron |
| Microarchitecture Techniques / Session 3a： |
| Banked Multiported Register Files for High-Frequency Superscalar Microprocessors / J. Tseng ; K. Asanovic |
| Pipeline Damping: A Microarchitectural Technique to Reduce Inductive Noise in Supply Voltage / M. Powell |
| Smarts: Accelerating Microarchitecture Simulation via Rigorous Statistical Sampling / R. Wunderlich ; T. Wenisch ; J. Hoe |
| Recovery and Replay / Session 3b： |
| Transient-Fault Recovery for Chip Multiprocessors / M. Gomaa ; C. Scarbrough ; I. Pomeranz |
| ReEnact: Using Thread-Level Speculation Mechanisms to Debug Data Races in Multithreaded Codes / M. Prvulovic ; J. Torrellas |
| A "Flight Data Recorder" for Enabling Full-System Multiprocessor Deterministic Replay / M. Xu ; R. Bodik ; M. Hill |
| Energy-Saving Designs / Session 4a： |
| A Highly-Configurable Cache Architecture for Embedded Systems / C. Zhang ; F. Vahid ; W. Najjar |
| Energy Efficient Co-Adaptive Instruction Fetch and Issue / A. Buyuktosunoglu ; T. Karkhanis ; P. Bose |
| Positional Adaptation of Processors: Application to Energy Reduction / M. Huang ; J. Renau |
| DRPM: Dynamic Speed Control for Power Management in Server Class Disks / S. Gurumurthi ; A. Sivasubramaniam ; M. Kandemir ; H. Franke |
| Interconnects and Multiprocessors / Session 4b： |
| Token Coherence: Decoupling Performance and Correctness / M. Martin ; D. Wood |
| GOAL: A Load-Balanced Adaptive Routing Algorithm for Torus Networks / A. Singh ; W. Dally ; A. Gupta ; B. Towles |
| Using Destination-Set Prediction to Improve the Latency/Bandwidth Tradeoff in Shared-Memory Multiprocessors / P. Harper ; D. Sorin |
| Performance Analysis of the Alpha 21364-Based HP GS1280 Multiprocessor / Z. Cvetanovic |
| Front-End Scheduling / Session 5： |
| Parallelism in the Front-End / P. Oberoi ; G. Sohi |
| Effective ahead Pipelining of Instruction Block Address Generation / A. Seznec ; A. Fraboulet |
| Cyclone: A Broadcast-Free Dynamic Instruction Scheduler with Selective Replay / D. Ernst ; A. Hamel ; T. Austin |
| Clustered Processors / Session 6a： |
| Improving Dynamic Cluster Assignment for Clustered Trace Cache Processors / R. Bhargava ; L. John |
| Dynamically Managing the Communication-Parallelism Trade-off in Future Clustered Processors / R. Balasubramonian ; S. Dwarkadas |
| A Pipelined Memory Architecture for High Throughput Network Processors / T. Sherwood ; G. Varghese ; B. Calder |
| Efficient Use of Memory Bandwidth to Improve Network Processor Throughput / J. Hasan ; S. Chandra |
| Prediction / Session 7a： |
| Improving Branch Prediction by Dynamic Dataflow-Based Identification of Correlated Branches from a Large Global History / R. Thomas ; M. Franklin ; C. Wilkerson ; J. Stark |
| Detecting Global Stride Locality in Value Streams / H. Zhou ; J. Flanagan ; T. Conte |
| Phase Tracking and Prediction / S. Sair |
| Mechanisms and Support / Session 7b： |
| Virtual Simple Architecture (VISA): Exceeding the Complexity Limit in Safe Real-Time Systems / A. Anantaraman ; K. Seth ; K. Patil ; E. Rotenberg ; F. Mueller |
| DISE: A Programmable Macro Engine for Customizing Applications / M. Corliss ; E. Lewis ; A. Roth |
| Building Quantum Wires: The Long and the Short of It / M. Oskin ; F. Chong ; I. Chuang ; J. Kubiatowicz |
| Memory Issues / Session 8： |
| Guided Region Prefetching: A Cooperative Hardware/Software Approach / Z. Wang ; D. Burger ; S. Reinhardt ; K. McKinley ; C. Weems |
| Overcoming the Limitations of Conventional Vector Processors / C. Kozyrakis ; D. Patterson |
| A Performance Analysis of PIM, Stream Processing, and Tiled Processing on Memory-Intensive Signal Processing Kernels / J. Suh ; E. Kim ; S. Crago ; L. Srinivasan ; M. French |
| Exploiting Parallelisms / Session 9： |
| Exploiting ILP, TLP and DLP with the Polymorphous TRIPS Architecture / K. Sankaralingam ; R. Nagarajan ; H. Liu ; C. Kim ; J. Huh ; S. Keckler ; C. Moore |
| The Jrpm System for Dynamically Parallelizing Java Programs / M. Chen ; K. Olukotun |
| Author Index |
| Symposium Chairman's Welcome |
| Message from the Program Chair |
| Committee Members |
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