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1.

図書
図書
1. Proceedings, 10th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM 2002, 22-24 April 2002, Napa, California
editors, Jeffrey Arnold, Kenneth L. Pocek ; sponsored by IEEE Computer Society Technical Committee on Computer Architecture
出版情報: Los Alamitos, Calif. : IEEE Computer Society, c2002  x, 322 p. ; 28 cm
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目次情報: 続きを見る
Conference Organizers
Applications I / Session 1：
Image Registration of Real-Time Video Data Using the SONIC Reconfigurable Computer Platform / W. J. C. Melis ; P. Y. K. Cheung ; W. Luk
A Massively Parallel RC4 Key Search Engine / K. H. Tsoi ; K. H. Lee ; P. H. W. Leong
An FPGA Implementation of Triangle Mesh Decompression / T. Mitra ; T. Chiueh
Networking I / Session 2：
Single-Chip Gigabit Mixed-Version IP Router on Virtex-II Pro / G. Brebner
Control and Configuration Software for a Reconfigurable Networking Hardware Platform / T. S. Sproull ; J. W. Lockwood ; D. E. Taylor
Tool I / Session 3：
Peer-to-Peer Hardware-Software Interfaces for Reconfigurable Fabrics / M. Budiu ; M. Mishra ; A. R. Bharambe ; S. C. Goldstein
Pam-Blox II: Design and Evaluation of C++ Module Generation for Computing with FPGAs / O. Mencer
Coarse-Grain Pipelining on Multiple FPGA Architectures / H. Ziegler ; B. So ; M. Hall ; P. C. Diniz
Template Matching / Session 4：
FPGA-Based Template Matching Using Distance Transforms / S. Hezel ; A. Kugel ; R. Manner ; D. M. Gavrila
Reconfigurable Shape-Adaptive Template Matching Architectures / J. Gause
Networking II / Session 5：
Assisting Network Intrusion Detection with Reconfigurable Hardware / B. L. Hutchings ; R. Franklin ; D. Carver
GRIP: A Reconfigurable Architecture for Host-Based Gigabit-Rate Packet Processing / P. Bellows ; J. Flidr ; T. Lehman ; B. Schott ; K. D. Underwood
Design and Analysis of a Layer Seven Network Processor Accelerator Using Reconfigurable Logic / G. Memik ; S. O. Memik ; W. H. Mangione-Smith
Architecture I / Session 6：
Using On-Chip Configurable Logic to Reduce Embedded System Software Energy / G. Stitt ; B. Grattan ; J. Villarreal ; F. Vahid
Queue Machines: Hardware Compilation in Hardware / H. Schmit ; B. Levine ; B. Ylvisaker
Applications II / Session 7：
Custom Computing Machines for the Set Covering Problem / C. Plessl ; M. Platzner
Analysis and Implementation of the Discrete Element Method Using a Dedicated Highly Parallel Architecture in Reconfigurable Computing / B. Carrion Schafer ; S. F. Quigley ; A. H. C. Chan
Using Floating-Point Arithmetic on FPGAs to Accelerate Scientific N-Body Simulations / G. Lienhart
Architecture II / Session 8：
Mobile Memory: Improving Memory Locality in Very Large Reconfigurable Fabrics / R. Yan
Hardware-Assisted Fast Routing / A. DeHon ; R. Huang ; J. Wawrzynek
Tools II / Session 9：
Optimum Wordlength Allocation / G. A. Constantinides
Precis: A Design-Time Precision Analysis Tool / M. L. Chang ; S. Hauck
Fast Area Estimation to Support Compiler Optimizations in FPGA-Based Reconfigurable Systems / D. Kulkarni ; W. A. Najjar ; R. Rinker ; F. J. Kurdahi
Image Compression / Session 10：
Hyperspectral Image Compression on Reconfigurable Platforms / T. W. Fry
MPEG-Compliant Entropy Decoding on FPGA-Augmented TriMedia/CPU64 / M. Sima ; S. Cotofana ; S. Vassiliadis ; J. T. J. van Eijndhoven ; K. Vissers
On Sparse Matrix-Vector Multiplication with FPGA-Based System / H. ElGindy ; Y.-L. ShuePoster Session 1：
Implementing a Simple Continuous Speech Recognition System on an FPGA / S. J. Melnikoff ; M. J. Russell
RACER--A Rapid Prototyping Accelerator for Pulsed Neural Networks / C. Grassmann ; J. K. Anlauf
Accelerating Radiosity Calculations Using Reconfigurable Platforms / H. Styles
On Implementing a Configware/Software SAT Solver / N. A. Reis ; J. T. de Sousa
Reconfigurable Object Detection in FLIR Image Sequences / J. E. Scalera ; C. F. Jones III ; M. Soni ; M. B. Bucciero ; P. M. Athanas ; A. L. Abbott ; A. Mishra
TCP-Stream Reassembly and State Tracking in Hardware / M. Necker ; D. Contis ; D. Schimmel
Fast and Guaranteed C Compilation onto the PACT-XPP Reconfigurable Computing Platform / J. M. P. Cardoso ; M. WeinhardtPoster Session 2：
Module Generators Driving the Compilation for Adaptive Computing Systems / A. Koch ; N. Kasprzyk
System-Level Modelling and Implementation Technique for Run-Time Reconfigurable Systems / T. Rissa ; M. Vasilko ; J. Niittylahti
Tabu Search with Intensification Strategy for Functional Partitioning in Hardware-Software Codesign / T. Wiangtong
Automatic Latency-Optimal Design of FPGA-Based Systolic Arrays / J. G. Nash
Compiling ATR Probing Codes for Execution on FPGA Hardware / W. Bohm ; R. Beveridge ; B. Draper ; C. Ross ; M. Chawathe ; W. Najjar
The Effects of Datapath Placement and C-Slow Retiming on Three Computational Benchmarks / N. Weaver
A Scalable FPGA-Based Custom Computing Machine for a Medical Image Processing / T. Yokota ; M. Nagafuchi ; Y. Mekada ; T. Yoshinaga ; K. Ootsu ; T. BabaPoster Session 3：
The Design of the Amalgam Reconfigurable Cluster / J. D. Walstrom ; J. J. Cook ; D. B. Gottlieb ; S. Ferrera ; C.-W. Wang ; N. P. Carter
Mapping Algorithms to the Amalgam Programmable-Reconfigurable Processor
Customising Floating-Point Designs / A. A. Gaffar ; N. ShiraziPoster Session 4：
Mapping Multi-Mode Circuits to LUT-Based FPGA Using Embedded MUXes / T. Courtney ; R. Turner ; R. Woods
Author Index
Conference Organizers
Applications I / Session 1：
Image Registration of Real-Time Video Data Using the SONIC Reconfigurable Computer Platform / W. J. C. Melis ; P. Y. K. Cheung ; W. Luk
2.

図書
図書
2. Proceedings, 10th International Symposium on Modeling, Analysis, and Simulation of Computer and Telecommunications Systems : MOSCOTS 2002, 11-16 October 2002, Fort Worth, Texas
edited by A. Boukerche, S. K. Das, and S. Majumdar ; sponsored by IEEE Computer Society Technical Committee on Computer Architecture, IEEE Computer Society Technical Committee on Simulation ; in cooperation with ACM SIGSIM, ACM SIGARCH ; supported by University of North Texas, University of Texas at Arlington
出版情報: Los Alamitos, Calif. : IEEE Computer Society, c2002  xvi, 521 p. ; 28 cm
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3.

図書
図書
3. Proceedings : Eighth International Symposium on High-Performance Computer Architecture, 2-6 February 2002, Cambridge, Massachusetts
sponsored by IEEE Computer Society Technical Committee on Computer Architecture
出版情報: Los Alamitos, Cailf. : IEEE Computer Society Press, c2002  xiii, 323 p. ; 28 cm
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4.

図書
図書
4. Proceedings : 29th Annual International Symposium on Computer Architecture, 25-29 May 2002, Anchorage, Alaska
sponsored by IEEE TCCA, ACM SIGARCH
出版情報: Los Alamitos, Calif. : IEEE Computer Society, c2002  xv, 331 p. ; 28 cm
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Message from the General Chair
Message from the Program Chair
Organizing Committee
Steering Committee
Program Committee
Reviewers
Welcoming Remarks
Keynote Address / Burton J. Smith
Processor Pipelines / Session 1：
The Optimum Pipeline Depth for a Microprocessor / A. Hartstein ; T. Puzak
The Optimal Logic Depth per Pipeline Stage Is 6 to 8 FO4 Inverter Delays / M. Hrishikesh ; N. Jouppi ; K. Farkas ; D. Burger ; S. Keckler ; P. Shivakumar
Increasing Processor Performance by Implementing Deeper Pipelines / E. Sprangle ; D. Carmean
Processor Scheduling / Session 2：
Efficient Dynamic Scheduling through Tag Elimination / D. Ernst ; T. Austin
Slack: Maximizing Performance under Technological Constraints / B. Fields ; R. Bodik ; M. Hill
A Large, Fast Instruction Window for Tolerating Cache Misses / A. Lebeck ; J. Koppanalil ; T. Li ; J. Patwardhan ; E. Rotenberg
An Instruction Set and Microarchitecture for Instruction Level Distributed Processing / H.-S. Kim ; J. Smith
Safety and Reliability / Robert P. ColwellSession 3：
Transient-Fault Recovery Using Simultaneous Multithreading / T. Vijaykumar ; I. Pomeranz ; K. Cheng
Detailed Design and Evaluation of Redundant Multithreading Alternatives / S. Mukherjee ; M. Kontz ; S. Reinhardt
ReVive: Cost-Effective Architectural Support for Rollback Recovery in Shared-Memory Multiprocessors / M. Prvulovic ; Z. Zhang ; J. Torrellas
SafetyNet: Improving the Availability of Shared Memory Multiprocessors with Global Checkpoint/Recovery / D. Sorin ; M. Martin ; D. Wood
Power Aware Architecture / Session 4：
Dynamic Fine-Grain Leakage Reduction Using Leakage-Biased Bitlines / S. Heo ; K. Barr ; M. Hampton ; K. Asanovic
Drowsy Caches: Simple Techniques for Reducing Leakage Power / K. Flautner ; N. Kim ; S. Martin ; D. Blaauw ; T. Mudge
Power and Performance Evaluation of Globally Asynchronous Locally Synchronous Processors / A. Iyer ; D. Marculescu
Memory Systems / Session 5：
Using a User-Level Memory Thread for Correlation Prefetching / Y. Solihin ; J. Lee
Avoiding Initialization Misses to the Heap / J. Lewis ; B. Black ; M. Lipasti
Going the Distance for TLB Prefetching: An Application-Driven Study / G. Kandiraju ; A. Sivasubramaniam
Dynamic Optimization / Session 6：
Timekeeping in the Memory System: Predicting and Optimizing Memory Behavior / Z. Hu ; S. Kaxiras ; M. Martonosi
Implementing Optimizations at Decode Time / I. Kim
Managing Multi-configuration Hardware via Dynamic Working Set Analysis / A. Dhodapkar
Data and Storage Networks / Session 7：
Queue Pair IP: A Hybrid Architecture for System Area Networks / P. Buonadonna ; D. Culler
Experiences with VI Communication for Database Storage / Y. Zhou ; A. Bilas ; S. Jagannathan ; C. Dubnicki ; J. Philbin ; K. Li
Vector Architectures / Session 8：
Speculative Dynamic Vectorization / A. Pajuelo ; A. Gonzalez ; M. Valero
Tarantula: A Vector Extension to the Alpha Architecture / R. Espasa ; F. Ardanaz ; J. Emer ; S. Felix ; J. Gago ; R. Gramunt ; I. Hernandez ; T. Juan ; G. Lowney ; M. Mattina ; A. Seznec
Supporting Deep Speculation / Session 9：
Design Tradeoffs for the Alpha EV8 Conditional Branch Predictor / V. Krishnan ; Y. Sazeides
Difficult-Path Branch Prediction Using Subordinate Microthreads / R. Chappell ; F. Tseng ; A. Yoaz ; Y. Patt
A Scalable Instruction Queue Design Using Dependence Chains / S. Raasch ; N. Binkert
Author Index
Message from the General Chair
Message from the Program Chair
Organizing Committee
5.

図書
図書
5. Proceedings, 2002 International Conference on Parallel Architectures and Compilatin Techniques, PACT2002, 22-25 September 2002, Charlottesville, Virginia, USA (: pbk)
sponsored by IEEE Computer Society Technical Committee on Computer Architecture, IEEE Computer Society Technical Commitee on Parallel Processing ... [et al.]
出版情報: Los Alamitos, Calif. : IEEE Computer Society, c2002  xviii, 305 p. ; 28 cm
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目次情報: 続きを見る
Message from the General Chairs
Message from the Program Chairs
Organizing Committee
Steering Committee
Program Committee
Reviewers
Keynote Address
Parallelism in Mainstream Enterprise Platforms of the Future / D. Bhandarkar
Data Parallelism and Threading / Session 1：
An Evaluation of Data-Parallel Compiler Support for Line-Sweep Applications / D. Chavarria-Miranda ; J. Mellor-Crummey
Increasing and Detecting Memory Address Congruence / S. Larsen ; E. Witchel ; S. Amarasinghe
Transparent Threads: Resource Sharing in SMT Processors for High Single-Thread Performance / G. K. Dorai ; D. Yeung
Compiler Support for Architecture / Session 2：
Compiler-Controlled Caching in Superword Register Files for Multimedia Extension Architectures / J. Shin ; J. Chame ; M. W. Hall
Effective Compilation Support for Variable Instruction Set Architecture / J. Liu ; T. Kong ; F. Chow
A Framework for Parallelizing Load/Stores on Embedded Processors / X. Zhuang ; S. Pande ; J. S. Greenland Jr.
Program Characterization / Session 3：
Workload Design: Selecting Representative Program-Input Pairs / L. Eeckhout ; H. Vandierendonck ; K. De Bosschere
Dataflow Frequency Analysis Based on Whole Program Paths / B. Scholz ; E. Mehofer
Quantifying Instruction Criticality / E. S. Tune ; D. M. Tullsen ; B. Calder
The Role of Computational Science in Energy Efficiency and Renewable Energy / S. Hammond
Power / Session 4：
Application Transformations for Energy and Performance-Aware Device Management / T. Heath ; E. Pinheiro ; J. Hom ; U. Kremer ; R. Bianchini
Leakage Energy Management in Cache Hierarchies / L. Li ; I. Kadayif ; Y-F. Tsai ; N. Vijaykrishnan ; M. Kandemir ; M. J. Irwin ; A. Sivasubramaniam
Integrating Adaptive On-Chip Storage Structures for Reduced Dynamic Power / S. Dropsho ; A. Buyuktosunoglu ; R. Balasubramonian ; D. H. Albonesi ; S. Dwarkadas ; G. Semeraro ; G. Magklis ; M. L. Scott
Prediction / Session 5：
The Use of Prediction for Accelerating Upgrade Misses in cc-NUMA Multiprocessors / M. E. Acacio ; J. Gonzalez ; J. M. Garcia ; J. Duato
Predicting Conditional Branches with Fusion-Based Hybrid Predictors / G. H. Loh ; D. S. Henry
Memory Performance / Session 6：
Speculative Sequential Consistency with Little Custom Storage / C. Gniady ; B. Falsafi
Cost-Effective Compiler Directed Memory Prefetching and Bypassing / D. Ortega ; E. Ayguade ; J.-L. Baer ; M. Valero
Using the Compiler to Improve Cache Replacement Decisions / Z. Wang ; K. S. McKinley ; A. L. Rosenberg ; C. C. Weems
Memory Aliasing / Session 7：
Software Bubbles: Using Predication to Compensate for Aliasing in Software Pipelines / B. Goldberg ; E. Crutcher ; C. Huneycutt ; K. Palem
Speculative Alias Analysis for Executable Code / M. Fernandez ; R. Espasa
Cost Effective Memory Dependence Prediction Using Speculation Levels and Color Sets / S. Onder
The Computational Grid: Aggregating Performance and Enhanced Capability from Federated Resources / R. Wolski
Java and IA-64 / Session 8：
Just-in-Time Java Compilation for the Itanium Processor / T. Shpeisman ; G.-Y. Lueh ; A.-R. Adl-Tabatabai
Eliminating Exception Constraints of Java Programs for IA-64 / K. Ishizaki ; T. Inagaki ; H. Komatsu ; T. Nakatani
Clustered Microarchitectures / Session 9：
Optimizing Loop Performance for Clustered VLIW Architectures / Y. Qian ; S. Carr ; P. Sweany
Exploiting Pseudo-Schedules to Guide Data Dependence Graph Partitioning / A. Aleta ; J. M. Codina ; J. Sanchez ; A. Gonzalez ; D. Kaeli
Efficient Interconnects for Clustered Microarchitectures / J.-M. Parcerisa ; J. Sahuquillo
Sigarch Conference Guidelines
Author Index
Message from the General Chairs
Message from the Program Chairs
Organizing Committee
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