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1.

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図書
1. ISLPED '02 : proceedings of the 2002 International Symposium on Low Power Electronics and Design, Monterey Beach Hotel Resort, Monterey, California, USA, August 12-14, 2002
sponsored by ACM SIGDA and IEEE Circuits and Systems Society ; with technical co-sponsorship from the IEEE Solid-State Circuits Society and the IEEE Electron Devices Society
出版情報: New York : Association for Computing Machinery, c2002  xii, 330 p. ; 28 cm
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2. Proceedings : 21st International Conference on Computer Design : October 13 to 15, 2003, San Jose, California (: softbound)
sponsored by IEEE Computer Society, IEEE Circuits and Systems Society ; in cooperation with IEEE Electron Devices Society
出版情報: Los Alamitos, Calif. : IEEE Computer Society, c2003  xxii, 563 p. ; 28 cm
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Welcome
Organizing Committee
Program Committee
Additional Reviewers
Keynotes
High-Speed Link Design, Then and Now / M. Horowitz
Terascale Computing and BlueGene / W. Pulley
Advanced EDA Tools for High-Performance Design / T. Vucurevich
Energy Efficiency / Session 1.1：
Energy Efficient Asymmetrically Ported Register Files / A. Aggarwal ; M. Franklin
Power Efficient Data Cache Designs / J. Abella ; A. Gonzalez
On Reducing Register Pressure and Energy in Multiple-Banked Register Files
Low Power Multiplication Algorithm for Switching Activity Reduction through Operand Decomposition / M. Ito ; D. Chinnery ; K. Keutzer
Timing Verification / Session 1.2：
Verification of Timed Circuits with Failure Directed Abstractions / H. Zheng ; C. Myers ; D. Walter ; S. Little ; T. Yoneda
Procedures for Identifying Untestable and Redundant Transition Faults in Synchronous Sequential Circuits / G. Chen ; S. Reddy ; I. Pomeranz
Event-Centric Simulation of Crosstalk Pulse Faults in Sequential Circuits / M. Phadoongsidhi ; K. Saluja
Specifying and Verifying Systems with Multiple Clocks / E. Clarke ; D. Kroening ; K. Yorav
Electrical Analysis for System LSI / Session 1.3：
Enhanced QMM-BEM Solver for 3-D Finite-Domain Capacitance Extraction with Multilayered Dielectrics / W. Yu ; Z. Wang ; X. Hong
An Improved Method for Fast Noise Estimation Based on Net Segmentation / C. Huang ; A. Dasgupta
Symbolic Failure Analysis of Custom Circuits due to Excessive Leakage Current / H. Song ; S. Bohidar ; I. Bahar ; J. Grodstein
An Efficient Algorithm for Calculating the Worst-case Delay due to Crosstalk / V. Rajappan ; S. Sapatnekar
Power Optimization / Session 2.1：
A Compact Model for Analysis and Design of On-chip Power Network with Decoupling Capacitors / P. Zarkesh-Ha ; K. Doniger ; W. Loh ; D. Sun ; R. Stephani ; G. Priebe
Precomputation-Based Guarding for Dynamic and Leakage Power Reduction / A. Abddollahi ; M. Pedram ; F. Fallah ; I. Ghosh
Charge-Recycling Voltage Domains for Energy-Efficient Low-Voltage Operation of Digital CMOS Circuits / S. Rajapandian ; Z. Xu ; K. Shepard
Low Power Adder with Adaptive Supply Voltage / H. Suzuki ; W. Jeong ; K. Roy
A Transparent Voltage Conversion Method and Its Application to a Dual-Supply-Voltage Register File / N. Tzartzanis ; W. Walker
Invited Session: Gene Chip Design / Session 2.2：
Detection of Biological Molecules: From Self-Assembled Films to Self-Integrated Devices / R. Levicky
Embedded Tutorial
Design Flow Enhancements for DNA Arrays / A. Kahng ; I. Mandoiu ; S. Reda ; X. Xu ; A. Zelikovsky
System Level Design / Session 2.3：
Bus Architecture Synthesis for Hardware-Software Co-Design of Deep Submicron Systems on Chip / N. Thepayasuwan ; V. Damle ; A. Doboli
Dynamically Optimized Synchronous Communication for Low Power System on Chip Designs / V. Chandra ; G. Carpenter ; J. Burns
Interface Synthesis Using Memory Mapping for an FPGA Platform / M. Luthra ; S. Gupta ; N. Dutt ; R. Gupta ; A. Nicolau
Efficient Synthesis of Networks On Chip / A. Pinto ; L. Carloni ; A. Sangiovanni-Vincentelli
Reducing Compilation Time Overhead in Compiled Simulators / M. Reshadi
Systems Performance / Session 3.1：
Profiling Interrupt Handler Performance through Kernel Instrumentation / B. Moore ; T. Slabach ; L. Schaelicke
Design and Performance of Compressed Interconnects for High Performance Servers / K. Kant ; R. Iyer
Routed Inter-ALU Networks for ILP Scalability and Performance / K. Sankaralingam ; V. Singh ; S. Keckler ; D. Burger
Micro Processor Test & Diagnosis / Session 3.2：
Automatic Generation of Critical-Path Tests for a Partial-Scan Microprocessor / D. Bhavsar ; V. Bettada ; R. Davies
Test Generation for Non-separable RTL Controller-datapath Circuits Using a Satisfiability Based Approach / L. Lingappan ; S. Ravi ; N. Jha
Cost-Effective Graceful Degradation in Speculative Processor Subsystems: The Branch Prediction Case / S. Almukhaizim ; T. Verdel ; Y. Makris
Multiple Fault Diagnosis Using n-Detection Tests / M. Marek-Sadowska ; K. Tsai ; J. Rajski
Physical Design / Session 3.3：
A Physical Design Methodology for 1.3GHz SPARC64 Microprocessor / N. Ito ; H. Komatsu ; Y. Tanamura ; R. Yamashita ; H. Sugiyama ; Y. Sugiyama ; H. Hamamura
Physical Design of the "2.5D" Stacked System / Y. Deng ; W. Maly
Flow-Based Cell Moving Algorithm for Desired Cell Distribution / B. Choi ; H. Xu ; M. Wang ; M. Sarrafzadeh
Performance Optimization / Session 4.1：
NpBench: A Benchmark Suite for Control plane and Data plane Applications for Network Processors / B. Lee ; L. John
Hardware-Only Compression of Underutilized Address Buses: Design and Performance, Power, and Cost Analysis / N. Mahapatra ; J. Liu ; K. Sundaresan
Pipelined Multiplicative Division with IEEE Rounding / G. Even ; P. Seidel
Clock & Signal Distribution / Session 4.2：
Design of Resonant Global Clock Distributions / S. Chan ; P. Restley
Modeling and Mitigation of Jitter in Multi-Gbps Source-Synchronous I/O Links / G. Balamurugan ; N. Shanbhag
A Mixed-Mode Delay-Locked Loop Architecture / D. Eckerbert ; L. Svensson ; P. Larsson-Edefors
Optimal Inductance for On-chip RLC Interconnections / S. Das ; K. Agarwal ; D. Blaauw ; D. Sylvester
Performance and Power-Driven Physical Design / Session 4.3：
Spec Based Flip-Flop and Buffer Insertion / N. Akkiraju ; M. Mohan
A Microeconomic Model for Simultaneous Gate Sizing and Voltage Scaling for Power Optimization / N. Ranganathan ; A. Murugavel
A Simple Yet Effective Merging Scheme for Prescribed-Skew Clock Routing / R. Chaturvedi ; J. Hu
Instruction Execution / Session 5.1：
Hardware-Based Pointer Data Prefetcher / S. Lai ; S. Lu
A Dependence Driven Efficient Dispatch Scheme / S. Nadathur ; A. Tyagi
An Efficient VLIW DSP Architecture for Baseband Processing / T. Lin ; C. Chang ; C. Lee ; C. Jen
Dynamic Thread Resizing for Speculative Multithreaded Processors / M. Zahran
Invited Session: Test Compression Technology / Session 5.2：
Care Bit Density and Test Cube Clusters: Multi-Level Compression Opportunities / B. Koenemann
XMAX: X-Tolerant Architecture for MAXimal Test Compression / S. Mitra ; K. Kim
Test Data Compression and Compaction for Embedded Test of Nanometer Technology Designs / J. Tyszer
Physical Design for Regular Fabrics and FPGA's / Session 5.3：
Non-Crossing OBDDs for Mapping to Regular Circuit Structures / A. Cao ; C. Koh
Interconnect Estimation for FPGAs under Timing Driven Domains / P. Kannan ; D. Bhatia
ROAD: An Order-Impervious Optimal Detailed Router for FPGAs / H. Arslan ; S. Dutt
Array Design Optimization / Session 6.1：
Reducing dTLB Energy through Dynamic Resizing / V. Delaluz ; M. Kandemir ; A. Sivasubramaniam ; M. Irwin ; N. Vijaykrishnan
Distributed Reorder Buffer Schemes for Low Power / G. Kucuk ; O. Ergin ; D. Ponomarev ; K. Ghose
Virtual Page Tag Reduction for Low-Power TLBs / P. Petrov ; A. Orailoglu
Dynamic Cluster Resizing / J. Gonzalez
Test Compaction / Session 6.2：
Independent Test Sequence Compaction through Integer Programming / P. Drineas
On Combining Pinpoint Test Set Relaxation and Run-Length Codes for Reducing Test Data Volume / S. Kajihara ; Y. Doi ; L. Li ; K. Chakrabarty
Static Test Compaction for Multiple Full-Scan Circuits
A Method to Find Don't Care Values in Test Sequences for Sequential Circuits / Y. Higami ; S. Kobayashi ; Y. Takamatsu
Invited Session: Techniques for Synthesizing into Fabrics / Session 6.3：
Simplifying SoC Design with the Customizable Control Processor Platform / C. Ogilvie ; R. Ray ; R. Devins ; M. Kautzman ; M. Hale ; R. Bergamaschi ; B. Lynch ; S. Gaur
Structured ASICs: Opportunities and Challenges / B. Zahiri
System LSI Implementation Fabrics for the Future / S. Kaptanoglu
Hardware Partitioning / Session 7.1：
Multiple-V[subscript dd] Scheduling/Allocation for Partitioned Floorplan / D. Kang ; M. Johnson
SCATOMi: Scheduling Driven Circuit Partitioning Algorithm for Multiple FPGAs Using Time-multiplexed, Off-chip, Multicasting Interconnection Architecture / Y. Kwon ; B. Park ; C. Kyung
A Study of Hardware Techniques that Dynamically Exploit Frequent Operands to Reduce Power Consumption in Integer Function Units / K. Gandhi
Energy-Aware Design and Application / Session 7.2：
KnapBind: An Area-Efficient Binding Algorithm for Low-leakage Datapaths / C. Gopalakrishnan ; S. Katkoori
A Novel Synthesis Strategy Driven by Partial Evaluation Based Circuit Reduction for Application Specific DSP Circuits / M. Mukherjee ; R. Vemuri
Power Fluctuation Minimization During Behavioral Synthesis Using ILP-Based Datapath Scheduling / S. Mohanty ; S. Chappidi
An Energy-Aware Simulation Model and Transaction Protocol for Dynamic Workload Distribution in Mobile Ad Hoc Networks / F. Ghasemi-Tari ; P. Rong
Invited Session: High-Speed Design Issues and Test Challenges / Session 7.3：
CMOS High-Speed Serial I/Os--Present and Future / M. Lee ; W. Dally ; R. Farjad-Rad ; H. Ng ; R. Senthinathan ; J. Edmondson ; J. Poulton
Fully Differential Receiver Chipset for 40 Gb/s Applications Using GaInAs/InP Single Heterojunction Bipolar Transistors / K. Kiziloglu ; S. Seetharaman ; K. Glass ; C. Bil ; H. Duong ; G. Asmanis
Paradigm Shift for Jitter and Noise in Design and Test [greater than sign]GB/s Data Communication Systems / M. Li ; J. Wilstrup
Efficiency and Reliability / Session 8.1：
Cost-Efficient Memory Architecture Design of NAND Flash Memory Embedded Systems / C. Park ; J. Seo ; D. Seo ; S. Kim ; B. Kim
Exploiting Microarchitectural Redundancy for Defect Tolerance / P. Shivakumar ; C. Moore
Reducing Multimedia Decode Power Using Feedback Control / Z. Lu ; J. Lach ; M. Stan ; K. Skadron
Novel Methods in Logic Synthesis / Session 8.2：
Structural Detection of Symmetries in Boolean Functions / G. Wang ; A. Kuehlmann
Boolean Decomposition Based on Cyclic Chains / E. Dubrova ; M. Teslenko ; J. Karlsson
SAT-Based Algorithms for Logic Minimization / S. Sapra ; M. Theobald
Communications and Context Management / Session 9.1：
Low-Density Parity-Check Decoder Architecture for High Throughput Optical Fiber Channels / A. Selvarathinam ; E. Kim ; G. Choi
Improving Branch Prediction Accuracy in Embedded Processors in the Presence of Coniext Switches / S. Pasricha ; A. Veidenbaum
Reducing Operand Transport Complexity of Superscalar Processors Using Distributed Register Files / S. Bunchua ; D. Wills ; L. Wills
xpipes: a Latency Insensitive Parameterized Network-on-chip Architecture for Multi-Processor SoCs / M. Dall'Osso ; G. Biccari ; L. Giovannini ; D. Bertozzi ; L. Benini
Board Test and Power-Aware Test / Session 9.2：
Aggressive Test Power Reduction through Test Stimuli Transformation / O. Sinanoglu
Power-Time Tradeoff in Test Scheduling for SoCs / M. Nourani ; J. Chin
Multiple Transition Model and Enhanced Boundary Scan Architecture to Test Interconnects for Signal Integrity / M. Tehranipour ; N. Ahmed
Author Index
Welcome
Organizing Committee
Program Committee
3.

図書
図書
3. 2001 International Symposium on VLSI Technology, Systems, and Applications : proceedings of technical papers, April 18-20, 2001, Lakeshore Hotel, Hsinchu, Taiwan, ROC
[sponsored by Industrial Technology Research Institute, ROC ; in cooperation with Chinese Institute of Engineers, ROC ... [et al.]
出版情報: [United States] : IEEE, ITRI, c2001  310, iii p. ; 30 cm
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4.

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4. Proceedings : 2000 International Conference on Computer Design, 17-20 September 2000, Austin, Texas (: case ; : pbk ; : microfiche)
sponsored by IEEE Computer Society, IEEE Circuits and Systems Society ; in cooperation with IEEE Electron Devices Society
出版情報: Los Alamitos, Calif. : IEEE Computer Society, c2000  xvii, 611 p. ; 28 cm
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Chairs' Message
Conference Organizers
Program Committee
Additional Reviewers
Keynote Address
On the Road to a Mobile Information Society / Dirk Friebel
New Architectures / Mauricio BreternitzSession 1.1：
Architectural Impact of Secure Socket Layer on Internet Servers / K. Kant ; R. Iyer ; P. Mohapatra
Fast Subword Permutation Instructions Using Omega and Flip Network Stages / X. Yang ; R. Lee
Sleipnir--An Instruction-Level Simulator Generator / T. Jeremiassen
Fault-Simulation and ATPG at Different Design Levels / Nur ToubaSession 1.2：
Analog Transient Concurrent Fault Simulation with Dynamic Fault Grouping / J. Hou ; A. Chatterjee
Pseudoexhaustive TPG with a Provably Low Number of LFSR Seeds / D. Kagaris ; S. Tragoudas
An Application of Genetic Algorithms and BDDs to Functional Testing / F. Ferrandi ; A. Fin ; F. Fummi ; D. Sciuto
Advanced Design Techniques / Ken ShepardSession 1.3：
High-Performance, Low-Power Skewed Static Logic in Very Deep-Submicron (VDSM) Technology / C. Kim ; J. Lee ; K.-H. Baek ; E. Martina ; S.-M. Kang
Estimation of Inductive and Resistive Switching Noise on Power Supply Network in Deep Sub-micron CMOS Circuits / S. Zhao ; K. Roy ; C.-K. Koh
Self-Calibrating Clocks for Globally Asynchronous Locally Synchronous Systems / S. Moore ; G. Taylor ; P. Cunningham ; R. Mullins ; P. Robinson
Improving CPU Performance / Brian GraysonSession 2.1：
Hybridizing and Coalescing Load Value Predictors / M. Burtscher ; B. Zorn
A 2-Way Thrashing-Avoidance Cache (TAC): An Efficient Instruction Cache Scheme for Object-Oriented Languages / Y. Chu ; M. Ito
Architectural Support for Dynamic Memory Management / J. Chang ; W. Srisa-an ; C.-T. Lo
SCIMA: Software Controlled Integrated Memory Architecture for High Performance Computing / M. Kondo ; H. Okawara ; H. Nakamura ; T. Boku
Parasitic Modeling, Analysis, and Optimization / Tom DillingerSession 2.2：
Worst Delay Estimation in Crosstalk Aware Static Timing Analysis / T. Xiao ; M. Marek-Sadowska
Analysis and Optimization of Ground Bounce in Digital CMOS Circuits / P. Heydari ; M. Pedram
An Efficient and Accurate Model for RF/Microwave Spiral Inductors Using Microstrip Lines Theory / N. Masoumi ; S. Safavi-Naeini ; M. Elmasry
Comparative Study of Parallel Algorithms for 3-D Capacitance Extraction on Distributed Memory Multiprocessors / Y. Yuan ; P. Banerjee
Low Power and Arithmetic / Margarida JacomeSession 2.3：
A Novel Low-Power Microprocessor Architecture / R. Hakenes ; Y. Manoli
A Power Perspective of Value Speculation for Superscalar Microprocessors / R. Moreno ; L. Pinuel ; S. del Pino ; F. Tirado
Multilevel Reverse-Carry Adder / J. Bruguera ; T. Lang
Evaluating Signal Processing and Multimedia Applications on SIMD, VLIW and Superscalar Architectures / D. Talla ; L. John ; V. Lapinskii ; B. Evans
Servers and Parallelism / Ruby LeeSession 3.1：
Unified Fine-Granularity Buffering of Index and Data: Approach and Implementation / Q. Cao ; J. Torrellas ; H. Jagadish
Analysis of Shared Memory Misses and Reference Patterns / J. Rothman ; A. Smith
Power-Sensitive Multithreaded Architecture / J. Seng ; D. Tullsen ; G. Cai
Circuit Optimization and Analysis / Shervin HojatSession 3.2：
Delay Constrained Optimization by Simultaneous Fanout Tree Construction, Buffer Insertion/Sizing and Gate Sizing / I-M. Liu ; A. Aziz
Application-Based, Transistor-Level Full-Chip Power Analysis for 700 MHz PowerPC Microprocessor / Y.-K. Cheng ; D. Bearden ; K. Suryadevara
Buffer Library Selection / C. Alpert ; R. Gandham ; J. Neves ; S. Quay
High-Performance Low-Power CMOS Circuits Using Multiple Channel Length and Multiple Oxide Thickness / N. Sirisantana ; L. Wei
Logic Circuit Families / Shyh-Jye JouSession 3.3：
Current-Mode Threshold Logic Gates / S. Bobba ; I. Hajj
Skewed CMOS: Noise-Immune High-Performance Low-Power Static Circuit Family / A. Solomatnikov ; D. Somasekhar
Output Prediction Logic: A High-Performance CMOS Design Technique / L. McMurchie ; S. Kio ; G. Yee ; T. Thorp ; C. Sechen
The Future of Populist Parallelism / Greg Pfister
Intelligent Memory / Steven ReinhardtSession 4.1：
A Study of Channeled DRAM Memory Architectures / L. Friebe ; Y. Yabe ; M. Motomura
DRAM-Page Based Prediction and Prefetching / H. Yu ; G. Kedem
Reducing Cost and Tolerating Defects in Page-Based Intelligent Memory / M. Oskin ; D. Keen ; J. Hensley ; L.-V. Lita ; F. Chong
Processor Microarchitecture / Steve FurberSession 4.2：
A Selective Temporal and Aggressive Spatial Cache System Based on Time Interval / J.-H. Lee ; J.-S. Lee ; S.-D. Kim
Design of Instruction Stream Buffer with Trace Support for X86 Processors / J.-C. Chiu ; I-H. Huang ; C.-P. Chung
A Trace Based Evaluation of Speculative Branch Decoupling / A. Nadkarni ; A. Tyagi
Digital Logic Techniques / Barbara ChappellSession 4.3：
An Adder Using Charge Sharing and Its Application in DRAMs / H.-S. Yu ; S. Lee ; J. Abraham
Fixed-Width Multiplier for DSP Application / S.-J. Jou ; H.-H. Wang
Dynamic Flip-Flop with Improved Power / N. Nedovic ; V. Oklobdzija
Embedded Processors: Architecture and System-Design Issues / Ricardo GonzalesSession 5.1：
Processors for Mobile Applications / F. Koushanfar ; V. Prabhu ; M. Potkonjak ; J. Rabaey
AMULET3: A 100 MIPS Asynchronous Embedded Processor / S. Furber ; D. Edwards ; J. Garside
Xtensa with User Defined DSP Coprocessor Microarchitectures / G. Ezer
Predictive Strategies for Low-Power RTOS Scheduling / P. Kumar ; M. Srivastava
Floorplanning and Partitioning / Tim BurksSession 5.2：
Rectilinear Block Placement Using B*-Trees / G.-M. Wu ; Y.-C. Chang ; Y.-W. Chang
Fast Hierarchical Floorplanning with Congestion and Timing Control / A. Ranjan ; K. Bazargan ; M. Sarrafzadeh
An Evaluation of Move-Based Multi-Way Partitioning Algorithms / E. Yarack ; J. Carletta
Assignment-Space Exploration Approach to Concurrent Data-Path/Floorplan Synthesis / K. Oohashi ; M. Kaneko ; S. Tayu
Basic Algorithms in Verification and Test / Yatin HoskoteSession 5.3：
On Solving Stack-Based Incremental Satisfiability Problems / J. Kim ; J. Whittemore ; K. Sakallah
Efficient Dynamic Minimization of World-Level DDs Based on Lower Bound Computation / W. Gunther ; R. Drechsler ; S. Horeth
Sensitivity Levels of Test Patterns and Their Usefulness in Simulation-Based Test Generation / I. Pomeranz ; S. Reddy
On Test Application Time and Defect Detection Capabilities of Test Sets for Scan Designs
Special Session: Advancements in DSP Architecture / Jim Bondi ; Nagaraj NSSession 6.1：
Effective Hardware-Based Two-Way Loop Cache for High Performance Low Power Processors / T. Anderson ; S. Agarwala
A Multi-Level Memory System Architecture for High-Performance DSP Applications / C. Fuoco ; D. Comisky ; C. Mobley
A Scalable High-Performance DMA Architecture for DSP Applications
Advanced Architectural Design and Synthesis / Edward GrochowskiSession 6.2：
Efficient Place and Route for Pipeline Reconfigurable Architectures / S. Cadambi ; S. Goldstein
PEAS-III: An ASIP Design Environment / M. Itoh ; S. Higaki ; J. Sato ; A. Shiomi ; Y. Takeuchi ; A. Kitajima ; M. Imai
Symbolic Binding for Clustered VLIW ASIPs / S. Pillai ; M. Jacome
Interfacing Hardware and Software Using C++ Class Libraries / D. Ramanathan ; R. Roth ; R. Gupta
Application and Case Studies in Test and Verification / Carl PixleySession 6.3：
Formal Verification of an Industrial System-on-a-Chip / H. Choi ; M.-K. Yim ; J.-Y. Lee ; B.-W. Yun ; Y.-T. Lee
Equivalence Checking Combining a Structural SAT-Solver, BDDs, and Simulation / V. Paruthi ; A. Kuehlmann
Efficient Design Error Correction of Digital Circuits / D. Hoffmann ; T. Kropf
An Automatic Validation Methodology for Logic BIST in High Performance VLSI Design / M. Cogswell ; D. Pearl ; J. Sage ; A. Troidl
Invited Paper
The Birth of the Baby / H. Kahn ; R. Napper
Logic Optimization / Chin-Long WeySession 7.1：
Efficient Logic Optimization Using Regularity Extraction / T. Kutzschebauch
Binary and Multi-Valued SPFD-Based Wire Removal in PLA Networks / S. Sinha ; S. Khatri ; R. Brayton ; A. Sangiovanni-Vincentelli
Minimization of Ordered Pseudo Kronecker Decision Diagrams / P. Lindgren ; B. Becker
High Level Specification and Synthesis / Pranav AsharSession 7.2：
Rethinking Behavioral Synthesis for a Better Integration within Existing Design Flows / W. Cesario ; A. Jerraya ; Z. Sugar ; I. Moussa
Synthesis and Optimization of Interface Hardware between IP's Operating at Different Clock Frequencies / B.-I. Park ; I.-C. Park ; C.-M. Kyung
Multi-Level Communication Synthesis of Heterogeneous Multilanguage Specification / F. Hessel ; P. Coste ; G. Nicolescu ; P. LeMarrec ; N. Zergainoh
Poster Sessions
Low Power Video Object Motion-Tracking Architecture for Very Low Bit Rate Online Video Applications / W. Badawy ; M. Bayoumi
An SEU Injection Tool to Evaluate DSP-Based Architectures for Space Applications / A. Benso ; S. Martinetto ; P. Prinetto ; R. Mariani
On Integrating a Proprietary and a Commercial Architecture for Optimal BIST Performances in SoCs / S. Di Carlo ; S. Chiusano ; F. Ricciato ; M. Bodoni ; M. Spadari
Static Timing Analysis with False Paths / H. Chen ; B. Lu ; D.-Z. Du
A Methodology and Tool for Automated Transformational High-Level Design Space Exploration / J. Gerlach ; W. Rosenstiel
Cheap Out-of-Order Execution Using Delayed Issue / J. Grossman
Representing and Scheduling Looping Behavior Symbolically / S. Haynal ; F. Brewer
Advanced Wiring RC Timing Design Techniques for Logic LSIs in Gigahertz Era and Beyond / Y. Ito ; S. Isomura ; T. Hiyama ; K. Nojiri
A Register File with Transposed Access Mode / Y. Jung ; S. Berg ; D. Kim ; Y. Kim
Leakage Power Analysis and Reduction during Behavioral Synthesis / K. Khouri ; N. Jha
An Advanced Instruction Folding Mechanism for a Stackless Java Processor / A. Kim ; M. Chang
OpenDesign: An Open User-Configurable Project Environment for Collaborative Design and Execution on the Internet / H. Lavana ; F. Brglez ; R. Reese ; G. Konduri ; A. Chandrakasan
A Decompression Architecture for Low Power Embedded Systems / H. Lekatsas ; J. Henkel ; W. Wolf
Optimal vs. Heuristic Approaches to Context Scheduling for Multi-Context Reconfigurable Architectures / R. Maestre ; F. Kurdahi ; M. Fernandez ; R. Hermida ; N. Bagherzadeh ; H. Singh
The M-CORE M340 Unified Cache Architecture / A. Malik ; B. Moyer ; D. Cermak
Crosstalk-Constrained Performance Optimization by Using Wire Sizing and Perturbation / S.-R. Pan
Hierarchical Simulation of a Multiprocessor Architecture / M. Pirvu ; L. Bhuyan ; R. Mahapatra
On Multiple Precision Based Montgomery Multiplication without Precomputation of N[subscript 0]' = -N[subscript 0 superscript -1] mod W / H. Ploog ; D. Timmerman
A Technique for Identifying RTL and Gate-Level Correspondences / S. Ravi ; I. Ghosh ; V. Boppana
A Direct Mapping FPGA Architecture for Industrial Process Control Applications / J. Welch
Source-Level Transformations for Improved Formal Verification / B. Winters ; A. Hu
Author Index
Chairs' Message
Conference Organizers
Program Committee
5.

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図書
5. Proceedings of the 2000 third IEEE International Caracas Conference on Devices, Circuits and Systems, Cancún, Mėxico, March 15-17, 2000 (:softbound)
[sponsored by IEEE Electrol Device Society, the IEEE Circuits and Systems Society]
出版情報: [New York] : Institute of Electrical and Electronics Engineers, c2000  1 v.(various paging) ; 27 cm
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6.

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6. 13th International Symposium on Low Power Electronics and Design : ISLPED'08 : August 11-13, 2008, Bangalore, India
International Symposium on Low Power Electronics and Design ; ACM Special Interest Group on Design Automation ; IEEE Circuits and Systems Society ; IEEE Solid-State Circuits Society ; IEEE Electron Devices Society ; Association for Computing Machinery
出版情報: New York, N.Y. : Association for Computing Machinery, c2008  367 p. ; 28 cm
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7.

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7. ISLPED'07 : proceedings of the 2007 International Symposium on Low Power Electronics and Design, Portland, Oregon, USA, August 27-29, 2007
sponsored by ACM SIGDA & IEEE Circuits and Systems Society ; with technical support from IEEE Solid-State Circuits Society and IEEE Electron Devices Society
出版情報: New York, N.Y. : Association for Computing Machinery, c2007  xvi, 416 p. ; 28 cm
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8.

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8. Program and technical digest, ICCDCS 2004 : fifth International Caracas Conference on Devices, Circuits, and Systems, 3-5 November 2004, Barceló Bávaro Convention Center, Punta Cana, Dominican Republic
[the technical co-sponsorship of IEEE's Electron Devices and Circuits and Systems Societies]
出版情報: Piscataway, N.J. : IEEE, c2004  [32], 357 p. ; 28 cm
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9.

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9. ISLPED '01 : proceedings of the 2001, International Symposium on Low Power Electronics and Design, Hilton Waterfront Beach Resort, Huntington Beach, California, USA, August 6-7, 2001
sponsored by ACM SIGDA and IEEE Circuits and Systems Society ; with technical co-sponsorship from the IEEE Solid-State Circuits Society and the IEEE Electron Devices Society
出版情報: New York : Association for Computing Machinery, c2001  xii, 395 p. ; 28 cm
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10.

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10. ISLPED'05 : proceedings of the 2005 International Symposium on Low Power Electronics and Design, Hotel Marriott del Mar, San Diego, California, USA, August 8-10, 2005
sponsored by ACM SIGDA and IEEE Circuits and Systems Society ; with technical support from the IEEE Solid-State Circuits Society and the IEEE Electron Devices Society
出版情報: New York, N.Y. : Association for Computing Machinery, c2005  xiv, 402 p. ; 28 cm
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