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1.

図書

図書
sponsored by IEEE Computer Society Technical Council on Software Engineering ; co-sponsored by the Netherlands Organisation for Scientific Research, the Royal Netherlands Academy of Arts and Sciences
出版情報: Los Alamitos, Calif. : IEEE Computer Society, c2003  x, 213 p. ; 27 cm
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目次情報: 続きを見る
Message from the Program Committee Chairs
Conference Organization
Program Committee
Reviewers
Static Analysis / Session I:
Online Cycle Detection and Difference Propagation for Pointer Analysis / D. J. Pearce ; P. H. J. Kelly ; C. Hankin
Improving the Static Analysis of Loops by Dynamic Partitioning Techniques / M. Martel
CPP Denotational Semantics / J.-M. Favre
Object Oriented Code / Session II:
Applying Meyer's Taxonomy to Object-Oriented Software Systems / M. English ; J. Buckley ; T. Cahill
Power Law Distributions in Class Relationships / R. Wheeldon ; S. Counsell
The Java System Dependence Graph / N. Walkinshaw ; M. Roper ; M. Wood
Design of the CodeBoost Transformation System for Domain-Specific Optimisation of C++ Programs / O. S. Bagge ; K. T. Kalleberg ; M. Haveraaen ; E. Visser
Keynote / Session III:
Managing Multi-Billion Dollar IT Budgets Using Source Code Analysis / C. Verhoef
Slicing / Session IV:
Barrier Slicing and Chopping / J. Krinke
Slicing the SCAM Mug: A Case Study in Semantic Slicing / M. P. Ward
Static Slicing of Reactive Programs / A. R. Kulkarni ; S. Ramesh
Design and Implementation of Bytecode-Based Java Slicing System / F. Umemori ; K. Konda ; R. Yokomori ; K. Inoue
Interprocedural Static Slicing of Binary Executables / A. Kiss ; J. Jasz ; G. Lehotai ; T. Gyimothy
Program Transformations / Session V:
Towards Managing Environment Dependence during Legacy Systems Renovation and Maintenance / M. Mossienko ; O. Khaschansky ; D. Antonov ; O. Smirnov ; A. Gubanov
Turning Dynamic Typing into Static Typing by Program Specialization in a Compiler Front-End for Octave / K. Olmos
Unique Renaming of Java Using Source Transformation / X. Guo ; J. R. Cordy ; T. R. Dean
Parse-Tree Annotations Meet Re-Engineering Concerns / J. Kort ; R. Lammel
Tools and Techniques / Session VI:
XOgastan: XML-Oriented gcc AST Analysis and Transformations / G. Antoniol ; M. Di Penta ; G. Masone ; U. Villano
Detection of Redundant Code Using R[superscript 2]D[superscript 2] / A. Menezes Leitao
Checking Program Profiles / P. Moseley ; S. Debray ; G. Andrews
Results from a Large-Scale Study of Performance Optimization Techniques for Source Code Analyses Based on Graph Reachability Algorithms / D. Binkley ; M. Harman
Author Index
Message from the Program Committee Chairs
Conference Organization
Program Committee
2.

図書

図書
sponsored by the Chilean Computer Science Society
出版情報: Los Alamitos, Calif. : IEEE Computer Society, c2003  x, 155 p. ; 28 cm
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3.

図書

図書
edited by Reinaldo A. Bergamaschi, Wilhelmus Van Noije, and Wolfgang Rosenstiel
出版情報: Los Alamitos, Calif. : IEEE Computer Society, c2003  xvi, 362 p. ; 28 cm
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目次情報: 続きを見る
Foreword
Organizing Committee
Program Committee
Reviewers
Contributing Organizations
Corporate Sponsors
Tutorials
SystemC: From Language to Applications, from Tools to Methodologies / Grant Martin
System-Level Design for FPGAs / Patrick Lysaght
High-Performance RF/Microwave Integrated Circuits in Advanced Logic CMOS Technology: The Coming of Age for RF/Digital Mixed-Signal System-on-a-Package / Luiz Franca-Neto
Advanced Amplifier Design / Session 1A:
Design of a Low Noise Amplifier for CDMA Transceivers at 900 MHz in CMOS 0.35 [mu]m / J. A. P. Azevedo ; T. C. Pimenta
A Methodology for CMOS Low Noise Amplifier Design / E. Roa ; J. N. Soares ; W. Van Noije
Design of a Reusable Rail-to-Rail Operational Amplifier / P. Aguirre ; F. Silveira
Design of Operational Transconductance Amplifiers with Improved Gain by Using Graded-Channel SOI nMOSFETs / S. P. Gimenez ; M. A. Pavanello ; J. A. Martino ; S. Adriaensen ; D. Flandre
Logic Synthesis Techniques / Session 1B:
Boolean Technology Mapping Based on Logic Decomposition / M. Damiani ; A. Y. Selchenko
Retiming Finite State Machines to Control Hardened Data Paths / I. Auge ; F. Donnet ; F. Petrot
Combining Retiming and Recycling to Optimize the Performance of Synchronous Circuits / L. P. Carloni ; A. L. Sangiovanni-Vincentelli
Simplification of Toffoli Networks via Templates / D. Maslov ; G. W. Dueck ; D. M. Miller
Invited Paper / Session 2:
SystemC and the Future of Design Languages: Opportunities for Users and Research / G. Martin
Digital Design Techniques / Session 3A:
A New Pipelined Array Architecture for Signed Multiplication / E. Costa ; S. Bampi ; J. Monteiro
Novel Design Methodology for High-Performance XOR-XNOR Circuit Design / S. Goel ; M. A. Elgamel ; M. A. Bayoumi
High-Level and Co-Design Approaches / Session 3B:
Towards a High-Level Synthesis of Reconfigurable Bit-Serial Architectures / A. Rettberg ; F. Dittmann ; M. Zanella ; T. Lehmann
DALI: A Methodology for the Co-Design of Dataflow Applications on Hardware/Software Architectures / M. P. Vestias ; H. C. Neto
Mapping Applications onto FPGAs / Session 4A:
ME64--A Highly Scalable Hardware Parallel Architecture for Motion Estimation in FPGA / D. Zandonai ; M. Bergerman
Hyperspectral Images Clustering on Reconfigurable Hardware Using the K-Means Algorithm / A. G. da S. Filho ; A. C. Frery ; C. C. de Araujo ; H. Alic ; J. Cerqueira ; J. A. Loureiro ; M. E. de Lima ; M. das G. S. Oliveira ; M. M. Horta
Design and Prototyping of Direct Torque Control of Induction Motors in FPGAs / S. Ferreira ; F. Haffner ; L. F. Pereira ; F. Moraes
FPGA-Based Hardware Architecture for Neural Network: Binary Radix vs. Stochastic / N. Nedjah ; L. de Macedo Mourelle
IP Integration Techniques / Session 4B:
An XML Format Based Integration Infrastructure for IP Based Design / M. Visarius ; J. Lessmann ; W. Hardt ; F. Kelso ; W. Thronicke
Tangram--Virtual Integration of Heterogeneous IP Components in a Distributed Co-Simulation Environment / U. R. F. Souza ; J. K. Sperb ; B. A. de Mello ; F. R. Wagner
A Fast IP-Core Integration Methodology for SoC Design / J. A. de Oliveira Filho ; P. R. Maciel ; J. Moura ; B. Celso
A Universal High-Performance Analog Interface for Signal Processing SOCs / E. E. Fabris ; L. Carro
Architecture and Implementation of Multi-Processor SoCs for Advanced Set-Top Box and Digital TV Systems / S. DuttaSession 5:
Asynchronous Design Techniques / Session 6A:
Automatic Generation of 1-of-M QDI Asynchronous Adders / J. Fragoso ; G. Sicard ; M. Renaudin
Exclusion Relation of k Out of n and the Synthesis of Speed-Independent Circuits / A. Pereira ; A. R. Borges ; A. Ferrari
Networks-on-Chip / Session 6B:
Algorithms and Tools for Network on Chip Based System Design / T. Lei ; S. Kumar
SoCIN: A Parametric and Scalable Network-on-Chip / C. A. Zeferino ; A. A. Susin
Application Specific RF and Analog Design / Session 7A:
A Low Ripple Fully Integrated Charge Pump Regulator / J. Soldera ; A. Vilas Boas ; A. Olmos
A Temperature Compensated Fully Trimmable On-Chip IC Oscillator
Bias Dependence of Noise Correlation in MAGFETs / F. C. Castaldo ; J. P. C. Cajueiro ; C. A. dos Reis
A Charge Correction Cell for FGMOS-Based Circuits / E. O. Rodriguez-Villegas ; A. Yufera ; A. Rueda
Applications of Formal Methods to Design / Session 7B:
Unified Theory to Build Cell-Level Transistor Networks from BDDs / R. E. B. Poli ; F. R. Schneider ; R. P. Ribas ; A. I. Reis
Modeling a Reconfigurable System for Computing the FFT in Place via Rewriting-Logic / M. Ayala-Rincon ; R. B. Nogueira ; C. H. Llanos ; R. P. Jacobi ; R. W. Hartenstein
Runtime Analysis of Synchronous Programs for Low-Level Real-Time Verification / G. Logothetis ; K. Schneider ; C. Metzler
A Consumer Report on BDD Packages / G. Janssen
Novel Architectures / Session 8A:
A New Hybrid Parallel/Reconfigurable Architecture: The X4CP32 / A. Azevedo ; R. Soares ; I. S. Silva
Control Development for Mechatronic Systems with a Fully Reconfigurable Pipeline Architecture / U. Dierkes ; C. Rustemeier
Efficient Processor Instruction Set Extension by Asynchronous Reconfigurable Datapath Integration / J. Becker ; A. Thomas ; M. Scheer
Situated Learning on FPGA for Superscalar Microprocessor Design Education / R. Takahashi ; H. Ohiwa
Noise Analysis and Layout / Session 8B:
On-Chip Decoupling Capacitor Optimization for Noise and Leakage Reduction / H. H. Chen ; J. S. Neely ; M. F. Wang ; G. Co
Minimum-Area Shield Insertion for Explicit Inductive Noise Reduction
A New Continuous Switching Window Computation with Crosstalk Noise / J. M. Wang ; P. Chen ; O. Hafiz
Improving Simulated Annealing Placement by Applying Random and Greedy Mixed Perturbations / R. F. Hentschke ; R. A. da L. Reis
Future Design Tools for Platform FPGAs / P. LysaghtSession 9:
Issues in Reconfigurable Architectures / Session 10A:
Power Estimation and Power Measurement of Xilinx Virtex FPGAs: Trade-Offs and Limitations / M. Huebner ; M. Ullmann
Dynamic Reconfiguration Behavior Using Generic FPGAs and FPIDs / R. L. Zuim ; C. J. N. Coelho, Jr. ; L. F. E. Moreira ; A. O. Fernandes ; J. M. da Mata ; D. C. da Silva, Jr.
Timing Analysis and Layout / Session 10B:
Improving Critical Path Identification in Functional Timing Analysis / D. Ferrao ; G. Wilke ; R. Reis ; J. L. Guntzel
A Transistor Sizing Method Applied to an Automatic Layout Generation Tool / C. Santos ; C. Lazzari
Innovative Approaches to RF and Analog Design Problems / Session 11A:
Analog IC Modules Design Using Trapezoidal Association of MOS Transistors in 0.35 [mu]m Technology / A. Girardi ; F. P. Cortes ; E. Fabris
Digital Background Calibration Technique for Pipeline ADCs with Multi-Bit Stages / A. J. Gines ; E. J. Peralias
Design Methodologies for High-Speed CMOS Photoreceiver Front-Ends / F. Tissafi-Drissi ; I. O'Connor ; F. Mieyeville ; F. Gaffiot
Testing RF Signal Paths Using Spectral Analysis and Subsampling / M. Negreiros ; E. Schuler
High-Level Validation and Modeling / Session 11B:
Accurate Dependability Analysis of CAN-Based Networked Systems / J. Perez ; M. S. Reorda ; M. Violante
ReCoNet: Modeling and Implemention of Fault-Tolerant Distributed Reconfigurable Hardware / C. Haubelt ; D. Koch ; J. Teich
CACO-PS: A General-Purpose Cycle-Accurate Configurable Power Simulator / A. C. S. Beck Filho ; J. C. B. Mattos
From VHDL Register Transfer Level to SystemC Transaction Level Modeling: A Comparative Case Study / N. Calazans ; E. Moreno ; F. Hessel ; V. Rosa ; E. Carara
Author Index
Foreword
Organizing Committee
Program Committee
4.

図書

図書
organized by Department of Computer Engineering, Faculty of Engineering, Chulalongkorn University, Department of Mathematics, Faculty of Science, Chulalongkorn University
出版情報: Los Alamitos, Calif. : IEEE Computer Society, c2003  xvi, 582 p. ; 28 cm
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5.

図書

図書
sponsored by the Pressure Vessels and Piping Division, ASME ; principal editors, Wing L. Cheng, Shigeru Itoh ; contributing editors, M'Hamed Souli ... [et al.]
出版情報: New York, N.Y. : American Society of Mechanical Engineers, c2003  viii, 327 p. ; 28 cm
シリーズ名: PVP ; v. 460
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6.

図書

図書
sponsored by the Pressure Vessels and Piping Division, ASME ; principal editor, Dominique Moinereau ; contributing editors, Kenneth K. Yoon, Jae-Boong Choi
出版情報: New York, N.Y. : American Society of Mechanical Engineers, c2003  viii, 137 p. ; 28 cm
シリーズ名: PVP ; v. 461
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7.

図書

図書
sponsored by the Pressure Vessels and Piping Division, ASME ; principal editor, Poh-Sang Lam ; contributing editors, David P.G. Lidbury ... [et al.]
出版情報: New York, N.Y. : American Society of Mechanical Engineers, c2003  xii, 177 p. ; 28 cm
シリーズ名: PVP ; v. 462
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8.

図書

図書
sponsored by the Pressure Vessels and Piping Division, ASME ; principal editor, Poh-Sang Lam ; contributing editors, Claud Faidy ... [et al.]
出版情報: New York, N.Y. : American Society of Mechanical Engineers, c2003  vi, 193 p. ; 28 cm
シリーズ名: PVP ; vol. 463
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9.

図書

図書
sponsored by the Pressure Vessels and Piping Division, ASME ; principal editor, Frederick W. Brust ; contributing editors, Pingsha Dong ... [et al.]
出版情報: New York, N.Y. : American Society of Mechanical Engineers, c2003  vii, 239 p. ; 28 cm
シリーズ名: PVP ; v. 464
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10.

図書

図書
sponsored by the Pressure Vessels and Piping Division, ASME ; principal editor, M.J. Pettigrew ; contributing editors, J. Antunes ... [et al.]
出版情報: New York, N.Y. : American Society of Mechanical Engineers, c2003  vii, 240 p. ; 28 cm
シリーズ名: PVP ; v. 465
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