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1.

図書

図書
sponsored by IEEE Computer Society Technical Committee on Computer Architecture ... [et al.]
出版情報: Los Alamitos, Calif. ; Tokyo : IEEE Computer Society, c2005  xv, 363 p. ; 28 cm.
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2.

図書

図書
sponsored by the IEEE Computer Society Technical Committee on Computer Architecture
出版情報: Los Alamitos, Cailf : IEEE Computer Society Press, c1998  xii, 352 p. ; 28 cm
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3.

図書

図書
sponsored by the IEEE Computer Society, Technical Committee on Computer Architecture
出版情報: Los Alamitos, Calif. ; Tokyo : IEEE Computer Society Press, c1996  xii, 335 p. ; 28 cm
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4.

図書

図書
sponsored by IEEE Computer Society Technical Committee on Computer Architecture ; with the support of Rgion Midi-Pyrénees ... [et.al.]
出版情報: Los Alamitos, Cailf. : IEEE Computer Society, c1999  xiii, 420 p. ; 28 cm
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目次情報: 続きを見る
Message from the General Co-Chairs
Message from the Program Chair
Organizing Committee
Program Committee
List of Referees
Keynote Address I
Relaxing Constraints: Thoughts on the Evolution of Computer Architecture / Joel Emer ; Compaq Computer Corporation
System Architecture Tradeoffs / Session 1:
Impact of Chip-Level Integration on Performance of OLTP Workloads / L. Barroso ; K. Gharachorloo ; A. Nowatzyk ; B. Verghese
Toward a Cost-Effective DSM Organization That Exploits Processor-Memory Integration / J. Torrellas ; L. Yang ; A-T. Nguyen
Impact of Heterogeneity on DSM Performance / R. Figueiredo ; J. Fortes
Memory and Cache / Session 2a:
Design of a Parallel Vector Access Unit for SDRAM Memory Systems / B. Mathew ; S. McKee ; J. Carter ; A. Davis
Modified LRU Policies for Improving Second-Level Cache Behavior / W. Wong ; J-L. Baer
eXtended Block Cache / S. Jourdan ; L. Rappoport ; Y. Almog ; M. Erez ; A. Yoaz ; R. Ronen
Networks / Session 2b:
Flit-Reservation Flow Control / L-S. Peh ; W. Dally
Performance Evaluation of Dynamic Reconfiguration in High-Speed Local Area Networks / R. Casado ; A. Bermudez ; F. Quiles ; J. Sanchez ; J. Duato
Investigating QoS Support for Traffic Mixes with the MediaWorm Router / K. Yum ; A. Vaidya ; C. Das ; A. Sivasubramaniam
Multithreading and Microarchitecture / Session 3a:
Quantifying the SMT Layout Overhead--Does SMT Pull Its Weight? / J. Burns ; J-L. Gaudiot
Software-Controlled Multithreading Using Informing Memory Operations / T. Mowry ; S. Ramkissoon
Dynamic Cluster Assignment Mechanisms / R. Canal ; J. Parcerisa ; A. Gonzalez
Shared Memory / Session 3b:
High-Throughput Coherence Controllers / A. Nanda ; M. Michael ; D. Joseph
Coherence Communication Prediction in Shared-Memory Multiprocessors / S. Kaxiras ; C. Young
Improving the Throughput of Synchronization by Insertion of Delays / R. Rajwar ; A. Kagi ; J. Goodman
Panel Session I
Impact of Interconnect on Computer Architecture / Bill Dally
Keynote Address II
2K Papers on Caches by Y2K: Do We Need More? / Jean-Loup Baer
Software Techniques / Session 4:
On the Performance of Hand vs. Automatically Optimized Numerical Codes / M. Jimenez ; J. Llaberia ; A. Fernandez
Cache-Efficient Matrix Transposition / S. Chatterjee ; S. Sen
A Prefetching Technique for Irregular Accesses to Linked Data Structures / M. Karlsson ; F. Dahlgren ; P. Stenstrom
Reducing Code Size with Run-Time Decompression / C. Lefurgy ; E. Piccininni ; T. Mudge
Prediction I / Session 5a:
Decoupled Value Prediction on Trace Processors / S-J. Lee ; Y. Wang ; P-C. Yew
Branch Transition Rate: A New Metric for Improved Branch Classification Analysis / M. Haungs ; P. Sallee ; M. Farrens
Combining Static and Dynamic Branch Prediction to Reduce Destructive Aliasing / H. Patil ; J. Emer
Parallel Systems / Session 5b:
The Effect of Network Total Order, Broadcast, and Remote-Write Capability on Network-Based Shared Memory Computing / R. Stets ; S. Dwarkadas ; L. Kontothanassis ; U. Rencuzogullari ; M. Scott
PowerMANNA: A Parallel Architecture Based on the PowerPC MPC620 / P. Behr ; S. Pletner ; A. Sodan
A DSM Architecture for a Parallel Computer Cenju-4 / T. Hosomi ; Y. Kanoh ; M. Nakamura ; T. Hirose
Prediction II / Session 6a:
Memory Dependence Speculation Tradeoffs in Centralized, Continuous-Window Superscalar Processors / A. Moshovos ; G. Sohi
A Technique for High Bandwidth and Deterministic Low Latency Load/Store Accesses to Multiple Cache Banks / H. Neefs ; H. Vandierendonck ; K. De Bosschere
Trace Cache Redundancy: Red and Blue Traces / A. Ramirez ; J. Larriba-Pey ; M. Valero
Parallel Systems Performance / Session 6b:
Evaluation of Active Disks for Decision Support Databases / M. Uysal ; A. Acharya ; J. Saltz
Investigating the Performance of Two Programming Models for Clusters of SMP PCs / F. Cappello ; O. Richard ; D. Etiemble
Performance Analysis and Visualization of Parallel Systems Using SimOS and Rivet: A Case Study / R. Bosch ; C. Stolte ; G. Stoll ; M. Rosenblum ; P. Hanrahan
Special Session
Work-in-progress / Sally McKee
Keynote Address III
Networking at Home--Directions in Connected Computing for the Consumer / Kevin Kahn
Novel Architecture Issues / Session 7:
Register Organization for Media Processing / S. Rixner ; B. Khailany ; P. Mattson ; U. Kapasi ; J. Owens
Architectural Issues in Java Runtime Systems / R. Radhakrishnan ; N. Vijaykrishnan ; L. John
The Best Distribution for a Parallel OpenGL 3D Engine with Texture Caches / A. Vartanian ; J-L. Bechennec ; N. Drach-Temam
Cache Memory Design for Network Processors / T-C. Chiueh ; P. Pradhan
Workshop Overviews
4th Workshop on Communication, Architecture, and Applications for Network-Based Parallel Computing (CANPC)
4th Workshop on Interaction between Compilers and Computer Architectures (INTERACT)
4th Workshop on Multithreaded Execution, Architecture, and Compilation (MTEAC)
2nd Workshop on Parallel Computing for Irregular Applications (WPCIA2)
3rd Workshop on Computer Architecture Evaluation Using Commercial Workloads (CAECW)
Tutorial on Performance Modeling Using Hardware Counters
Author Index
Message from the General Co-Chairs
Message from the Program Chair
Organizing Committee
5.

図書

図書
sponsored by the IEEE Computer Society Technical Committee on Computer Architecture
出版情報: Los Alamitos, Cailf. : IEEE Computer Society Press, c2001  xvi, 318 p. ; 28 cm
所蔵情報: loading…
目次情報: 続きを見る
Message from the Chairs
Organizing Committee
Program Committee
Reviewers
Microarchitecture I
Stack Value File: Custom Microarchitecture for the Stack / H.-H. S. Lee ; M. Smelyanskiy ; C. J. Newburn ; G. S. Tyson
Register Renaming and Scheduling for Dynamic Execution of Predicated Code / P. H. Wang ; H. Wang ; R. M. Kling ; K. Ramakrishnan ; J. P. Shen
Data-Flow Prescheduling for Large Instruction Windows in Out-of-Order Processors / P. Michaud ; A. Seznec
Speculative Data-Driven Multithreading / A. Roth ; G. S. Sohi
Memory Architectures
Towards Virtually-Addressed Memory Hierarchies / X. Qiu ; M. Dubois
Reevaluating Online Superpage Promotion with Hardware Support / Z. Fang ; L. Zhang ; J. B. Carter ; W. C. Hsieh ; S. A. McKee
Performance of Hardware Compressed Main Memory / B. Abali ; H. Franke ; X. Shen ; D. E. Poff ; T. B. Smith
Multiprocessor Systems
JETTY: Filtering Snoops for Reduced Energy Consumption in SMP Servers / A. Moshovos ; G. Memik ; B. Falsafi ; A. Choudhary
A New Scalable Directory Architecture for Large-Scale Multiprocessors / M. E. Acacio ; J. Gonzalez ; J. M. Garcia ; J. Duato
Self-Tuned Congestion Control for Multiprocessor Networks / M. Thottethodi ; A. R. Lebeck ; S. S. Mukherjee
Code Generation Techniques
Automatically Mapping Code on an Intelligent Memory Architecture / J. Lee ; Y. Solihin ; J. Torrellas
CARS: A New Code Generation Framework for Clustered ILP Processors / K. Kailas ; K. Ebcioglu ; A. Agrawala
Energy and Thermal Management
An Integrated Circuit/Architecture Approach to Reducing Leakage in Deep-Submicron High-Performance I-Caches / S.-H. Yang ; M. D. Powell ; K. Roy ; T. N. Vijaykumar
DRAM Energy Management Using Software and Hardware Directed Power Mode Control / V. Delaluz ; M. Kandemir ; N. Vijaykrishnan ; A. Sivasubramaniam ; M. J. Irwin
Dynamic Thermal Management for High-Performance Microprocessors / D. Brooks ; M. Martonosi
Prediction Techniques
Dynamic Prediction of Critical Path Instructions / E. Tune ; D. Liang ; D. M. Tullsen ; B. Calder
Dynamic Branch Prediction with Perceptrons / D. A. Jimenez ; C. Lin
Differential FCM: Increasing Value Prediction Accuracy by Improving Table Usage Efficiency / B. Goeman ; H. Vandierendonck ; K. De Bosschere
Application-Specific Designs
DLP + TLP Processors for the Next Generation of Media Workloads / J. Corbal ; R. Espasa ; M. Valero
An Architectural Evaluation of Java TPC-W / H. W. Cain ; R. Rajwar ; M. Marden ; M. H. Lipasti
A Programmable Co-Processor for Profiling / C. B. Zilles
Performance Modeling and Analysis
A Delay Model and Speculative Architecture for Pipelined Routers / L.-S. Peh ; W. J. Dally
Quantifying the Impact of Architectural Scaling on Communication / T. Heath ; S. Kaur ; R. P. Martin ; T. D. Nguyen
Latency Tolerance Techniques
Call Graph Prefetching for Database Applications / M. Annavaram ; J. M. Patel ; E. S. Davidson
Branch History Guided Instruction Prefetching / V. Srinivasan ; M. J. Charney ; T. R. Puzak
Reducing DRAM Latencies with an Integrated Memory Hierarchy Design / W. Lin ; S. K. Reinhardt ; D. Burger
Workshops
Interact-V: Workshop on Interaction between Compilers and Computer Architectures / G. Lee ; P.-C. Yew
Fourth Workshop on Computer Architecture Evaluation using Commercial Workloads / A. Nanda ; R. Clapp
Workshop on Microprocessors for Networks and Communications / I. Spillinger ; M. Nemirovsky
Tutorials
VIA and InfiniBand Communication Architecture / D. K. Panda
Power-Performance Modeling, Analyis and Validation / P. Bose
Author Index
Message from the Chairs
Organizing Committee
Program Committee
6.

図書

図書
sponsored by IEEE Computer Society Technical Committee on Computer Architecture
出版情報: Los Alamitos, Cailf : IEEE Computer Society Press, c1999  xiii, 324 p. ; 28 cm
所蔵情報: loading…
7.

図書

図書
sponsored by the IEEE Computer Society Technical Committee on Computer Architecture
出版情報: Los Alamitos, Cailf. : IEEE Computer Society Press, c2003  xiv, 390 p. ; 28 cm
所蔵情報: loading…
8.

図書

図書
sponsored by IEEE Computer Society Technical Committee on Computer Architecture
出版情報: Los Alamitos, Cailf. : IEEE Computer Society Press, c2002  xiii, 323 p. ; 28 cm
所蔵情報: loading…
9.

図書

図書
sponsored by the IEEE Computer Society Technical Committee on Computer Architecture
出版情報: Los Alamitos, Cailf : IEEE Computer Society Press, c1997  xi, 353 p. ; 28 cm
所蔵情報: loading…
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