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1.

図書

図書
sponsored by IEEE Computer Society Technical Council on Test Technology , IEEE Computer Society Technical Committee on Design Automation
出版情報: Los Alamitos, Calif. : IEEE Computer Society, c2003  viii, 178 p. ; 28 cm
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2.

図書

図書
IEEE Computer Society Test Technology Technical Council ; co-sponsored by National Tsing Hua University
出版情報: Los Alamitos, Calif. : IEEE Computer Society, c2005  xxv, 153 p. ; 27 cm
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図書

図書
sponsored by IEEE Computer Society Test Technology Technical Council ; Co-Sponsored by National Cheng-Kung University
出版情報: Los Alamitos, Calif. : IEEE Computer Society Press, c2000  xxiii, 495 p. ; 28 cm
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Message from General Chair
Message from Program Co-Chairs
TTTC Activities Board
Asian Test Committee
Organizing Committee
Program Committee
Reviewers
Testing in the Fourth Dimension / Keynote Address I:
Challenges for the Academic Test Community / Keynote Address II:
CAD Tools on Testing / Jing-Yang JouIndustry Session I:
DFT and BIST Techniques for the Future / H.-P. Wang ; J. Turino
DFT Closure / F. Hayat ; T. Williams ; R. Kapur ; D. Hsu
Current Status and Future Trend on CAD Tools for VLSI Testing / W.-T. Cheng
Taiwan Test Industry: Value Added Testing in the New Millennium / Chung-Len LeeIndustry Session II:
Mixed-Signal SoC Testing: Is Mixed-Signal Design-for-Test on Its Way? / Panel I:
Collaboration between Industry and Academia in Test Research / Panel II:
Analog and Mixed Signal Test I / Kiyoshi FuruyaSession A1:
Test Generation for Fault Isolation in Analog Circuits Using Behavioral Models / S. Cherubal ; A. Chatterjee
Fault Diagnosis for Linear Analog Circuits / J.-W. Lin ; C.-L. Lee ; C.-C. Su ; J.-E. Chen
Testing Mixed-Signal Cores: Practical Oscillation-Based Test in an Analog Macrocell / G. Huertas ; D. Vazquez ; E. Peralias ; A. Rueda ; J. Huertas
New Built-in Self-Test Technique Based on Addition/Subtraction of Selected Node Voltages / K. Ko ; M. Wong
Memory Built-in Self-Test and Self-Diagnosis / Ad J. van de GoorSession A2:
A Built-in Self-Test and Self-Diagnosis Scheme for Embedded SRAM / C.-W. Wang ; C.-F. Wu ; J.-F. Li ; C.-W. Wu ; T. Teng ; K. Chiu ; H.-P. Lin
An FPGA-Based Re-Configurable Functional Tester for Memory Chips / J.-R. Huang ; C. Ong ; K. Cheng
BIST TPG for SRAM Cluster Interconnect Testing at Board Level / C.-H. Chiang ; S. Gupta
Efficient Built-in Self-Test Algorithm for Memory / S.-J. Wang ; C.-J. Wei
Analog and Mixed Signal Test II / M.D. ShiehSession B1:
Optimal Test-Set Generation for Parametric Fault Detection in Switched Capacitor Filters / W. Choi ; R. Harjani ; B. Vinnakota
TI-BIST: A Temperature Independent Analog BIST for Switched-Capacitor Filters / L. Carro ; E. Cota ; M. Lubaszewski ; Y. Bertrand ; F. Azais ; M. Renovell
Analog Circuit Equivalent Faults in the D.C. Domain / M. Worsman ; Y. Lee
A Methodology for Fault Model Development for Hierarchical Linear Systems / Y.-C. Huang
Testing a PWM Circuit Using Functional Fault Models and Compact Test Vectors for Operational Amplifiers / J. Calvano ; V. Alves
Fault Simulation and Timing Simulation / Kazumi HatayamaSession B2:
A New Framework for Static Timing Analysis, Incremental Timing Refinement, and Timing Simulation / L.-C. Chen ; M. Breuer
On the Feasibility of Fault Simulation Using Partial Circuit Descriptions / I. Pomeranz ; S. Reddy
Fsimac: A Fault Simulator for Asynchronous Sequential Circuits / S. Sur-Kolay ; M. Roncken ; K. Stevens ; P. Chaudhuri ; R. Roy
Simulation of Resistive Bridging Fault to Minimize the Presence of Intermediate Voltage and Oscillation in CMOS Circuits / A. Keshk ; Y. Miura ; K. Kinoshita
Non-Invasive Timing Analysis of IBM G6 Microprocessor L1 Cache Using Picosecond Imaging Circuit Analysis / S. Polonsky ; M. Mc Manus ; D. Knebel ; S. Steen ; P. Sanda
Fringe Meeting: SoC Testing and P1500 Standard / Shianling Wu ; Yervant Zorian
Fault Analysis I / Shiyi XuSession C1:
An Experimental Analysis of Spot Defects in SRAMs: Realistic Fault Models and Tests / S. Hamdioui
Enhanced Untestable Path Analysis Using Edge Graphs / S. Kajihara ; T. Shimono
A Waveform Simulator Based on Boolean Process / L. Li ; X. Yu ; Y. Min
On the Superiority of DO-RE-ME/MPG-D over Stuck-at-Based Defective Part Level Prediction / J. Dworak ; M. Grimaila ; B. Cobb ; T-C. Wang ; Li-C. Wang ; M. Mercer
Test Generation I / Yukihiro IguchiSession C2:
Compaction-Based Test Generation Using State and Fault Information / A. Giani ; S. Sheng ; M. Hsiao ; V. Agrawal
Test Sequence Compaction for Sequential Circuits with Reset States / Y. Higami ; Y. Takamatsu
SPIRIT: Satisfiability Problem Implementation for Redundancy Identification and Test Generation / E. Gizdarski ; H. Fujiwara
Forecasting the Efficiency of Test Generation Algorithms for Digital Circuits / S. Xu ; W. Cen
Functional Testing / Tomoo InoueSession C3:
Fast Hierarchical Test Path Construction for DFT-Free Controller-Datapath Circuits / Y. Makris ; J. Collins ; A. Orailoglu
Faster Processing for Microprocessor Functional ATPG / J. Hirase ; S. Yoshimura
Verification of Deadlock Free Property of High Level Robot Control / H. Hiraishi
Functional Testing of Microprocessors with Graded Fault Coverage / R. Kannah ; C. Ravikumar
Built-in Self-Test I / Jacob SavirSession D1:
Single-Control Testability of RTL Data Paths for BIST / T. Masuzawa ; M. Izutsu ; H. Wada
A BIST Methodology for At-Speed Testing of Data Communications Transceivers / S. Lin ; S. Mourad ; S. Krishnan
High-Speed Generation of LFSR Signatures / M.-D. Shieh ; H.-F. Lo ; M.-H. Sheu
Software Testing and Test Synthesis / Wen-Ben JoneSession D2:
Strong Self-Testability for Data Paths High-Level Synthesis / X. Li
Generating Test Items for Checking Illegal Behaviors in Software Testing / M. Hirayama ; J. Okayasu ; T. Yamamoto ; O. Mizuno ; T. Kikuno
Using Genetic Algorithms for Test Case Generation in Path Testing / J.-C. Lin ; P.-L. Yeh
Embedded-Core Testing / Douglas KaySession D3:
A Hierarchical Test Control Architecture for Core Based Design / K.-J. Lee ; C.-I. Huang
Embedded Core Testing Using Genetic Algorithms / R. Xu
Functional Testing and Fault Analysis Based Fault Coverage Enhancement Techniques for Embedded Core Based Systems / A. Bagwe ; R. Parekhji
Memory Testing / Rubin A. ParekhjiSession E1:
Detection of SRAM Cell Stability by Lowering Array Supply Voltage / D.-M. Kwai ; H.-W. Chang ; H.-J. Liao ; C.-H. Chiao ; Y.-F. Chou
A Realistic Fault Model for Flash Memories / Y.-L. Horng ; T.-Y. Chang
Impact of Memory Cell Array Bridges on the Faulty Behavior in Embedded DRAMs / Z. Al-Ars
Memory Test Time Reduction by Interconnecting Test Items / W.-J. Wu ; C. Tang
An Efficient Parallel Transparent Diagnostic BIST / D. Huang ; W.-B. Jone
Test Generation II / Christian LandraultSession E2:
Test Generation for Crosstalk-Induced Faults: Framework and Computational Results / W.-Y. Chen
Testing Programmable Interconnect Systems: An Algorithmic Approach / B. Liu ; F. Lombardi ; W. Huang
Reducing Test Application Time for Full Scan Circuits by the Addition of Transfer Sequences
TOF: A Tool for Test Pattern Generation Optimization of an FPGA Application-Oriented Test / J. Portal ; P. Faure ; J. Figueras ; Y. Zorian
Formal Verification of Data-Path Circuits Based on Symbolic Simulation / Y. Morihiro ; T. Yoneda
I[subscript DDQ] Testing / Sying-Jyan WangSession E3:
Is I[subscript DDQ] Testing not Applicable for Deep Submicron VLSI in Year 2011? / C.-W. Lu
High Speed I[subscript DDQ] Test and Its Testability for Process Variation / M. Hashizume ; H. Yotsuyanagi ; M. Ichimiya ; T. Tamesada ; M. Takeda
Memory Reduction of I[subscript DDQ] Test Compaction for Internal and External Bridging Faults / T. Maeda
A High-Speed I[subscript DDQ] Sensor Implementation / Y. Antonioli ; T. Inufushi ; S. Nishikawa
Cyclic Greedy Generation Method for Limited Number of I[subscript DDQ] Tests / T. Shinogi ; M. Ushio ; T. Hayashi
Built-in Self-Test II / Session F1:
Accelerated Test Pattern Generators for Mixed-Mode BIST Environments / W.-L. Wang
Effective Parallel Processing Techniques for the Generation of Test Data for a Logic Built-in Self Test System / P. Chang ; B. Keller ; S. Paliwal
Design and Testing of Fast and Cost Effective Serial Seeding TPGs Based on One-Dimensional Linear Hybrid Cellular Automata / A. Hlawiczka ; M. Kopec
An Efficient BIST Design Using LFSR-ROM Architecture
Testability Analysis and Design for Testability / Xinghao ChenSession F2:
Novel Techniques for Improving Testability Analysis / Y.-H. Su ; C.-H. Cheng ; S.-C. Chang
A Class of Sequential Circuits with Combinational Test Generation Complexity under Single-Fault Assumption / M. Inoue
Design for Sequential Testability: An Internal State Reseeding Approach for 100% Fault Coverage / M. Flottes ; C. Landrault ; A. Petitqueux
Fault Tolerance / J.C. Frank LienSession F3:
Testing Approach within FPGA-Based Fault Tolerant Systems / A. Doumar ; H. Ito
Transient-Fault Tolerant VHDL Descriptions: A Case-Study for Area Overhead Analysis / F. Vargas ; A. Amory
Fault Tolerant Multistage Interconnection Networks with Widely Dispersed Paths / N. Kamiura ; T. Kodera ; N. Matsui
A Testable/Fault-Tolerant FFT Processor Design / S.-K. Lu ; J.-S. Shih
Fault Analysis II / Mike WongSession G1:
Charge Sharing Fault Analysis and Testing for CMOS Domino Logic Circuits / J.-S. Wang
Testing Domino Circuits in SOI Technology / E. MacDonald ; N. Touba
A Case Study of Failure Analysis and Guardband Determination for a 64M-Bit DRAM / C.-T. Kao ; S. Wu
Low-Power Testing / C.P. RavikumarSession G2:
Peak-Power Reduction for Multiple-Scan Circuits during Test Application / T.-C. Huang ; J.-J. Chen
An Adjacency-Based Test Pattern Generator for Low Power BIST Design / P. Girard ; L. Guiller ; S. Pravossoudovitch
Distribution-Graph Based Approach and Extended Tree Growing Technique in Power-Constrained Block-Test Scheduling / V. Muresan ; X. Wang ; M. Vladutiu
Self-Checking Circuits and Concurrent Fault Detection / Yinghua MinSession G3:
A Method for Determining Whether Asynchronous Circuits Are Self-Checking / M. Liebelt ; C.-C. Lim
On Testing Safety-Sensitive Digital Systems / J. Savir
Accumulation-Based Concurrent Fault Detection for Linear Digital State Variable Systems / I. Bayraktaroglu
High Performance/Delay Testing / Tutorial 1:
SoC Testing and P1500 Standard / Tutorial 2:
Author Index
Call for Papers of ATS 2001
Message from General Chair
Message from Program Co-Chairs
TTTC Activities Board
4.

図書

図書
sponsored by IEEE Computer Society Test Technology Technical Council
出版情報: Los Alamitos, Calif. ; Tokyo : IEEE Computer Society, c2000  xxxix, 478 p. ; 28 cm
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目次情報: 続きを見る
Foreword
Organizing Committee
Steering Committee
Program Committee
Reviewers
VTS '99 Best Paper Award
VTS '99 Best Panel Award
Test Technology Technical Council
Test Technology Education Program: Overview of Tutorials
Plenary Session
Welcome Message / Adit Singh
"Optical Internet: Industry Challenges" / Brian McFadden
Program Introduction / Joan Figueras ; Program Chair
"Wall Street Perspective on System-on-Chip and Test Technology" / Erach D. Desai
Microprocessor Test/Validation
At-speed Testing of Delay Faults for Motorola's MPC7400, a PowerPC Microprocessor / N. Tendolkar ; R. Molyneaux ; C. Pyron ; R. Raina
Validation of PowerPC Custom Memories using Symbolic Simulation / N. Krishnamurthy ; A K. Martin ; M. S. Abadir ; J. A. Abraham
On Testing the Path Delay Faults of a Microprocessor Using its Instruction Set / W-C. Lai ; A. Krstic ; K-T Cheng
Low Power BIST and Scan
Low Power/Energy BIST Scheme for Datapaths / D. Gizopoulos ; N. Kranitis ; A. Paschalis ; M. Psarakis ; Y. Zorian
Low Power BIST via Non-linear Hybrid Cellular Automata / F. Corno ; M. Rebaudengo ; M. Sonza Reorda ; G. Squillero ; M. Violante
Static Compaction Techniques to Control Scan Vector Power Dissipation / R. Sankaralingam ; R. R. Oruganti ; N. A. Touba
Technology Trends and Their Impact on Test
Silicon-on-insulator Technology Impacts on SRAM Testing / R. D. Adams ; P. Shephard III
Timing Analysis of Combinational Circuits Including Capacitive Coupling and Statistical Process Variation / B. Choi ; D. M. H. Walker
Self-checking Circuits versus Realistic Faults in Very Deep Submicron / L. Anghel ; M. Nicolaidis ; I. Alzaher-Noufal
Scan Related Approaches
BSM2: Next Generation Boundary-Scan Master / F. P. Higgins ; R. Srinivasan
Virtual Scan Chains: A Means for Reducing Scan Length in Cores / A. Jas ; B. Pouya
A Rapid and Scalable Diagnosis Scheme for BIST Environments with a Large Number of Scan Chains / J. Ghosh-Dastidar
Defect Driven Techniques
A Framework to Minimize Test Escape and Yield Loss during I[subscript DDQ] Testing: A Case Study / H. Cheung ; S. K. Gupta
Path Selection for Delay Testing of Deep Sub-micron Devices using Statistical Performance Sensitivity Analysis / J-J. Liou ; K-T. Cheng ; D. A. Mukherjee
PROBE: A PPSFP Simulator for Resistive Bridging Faults / C. Y. Lee
System-on-chip Test Techniques
Test Data Compression for System-on-a-Chip Using Golomb Codes / A. Chandra ; K. Chakrabarty
Test and Debug of Networking SoCs: A Case Study / A. Bommireddy ; J. Khare ; S. Shaikh ; S-T. Su
Design of System-on-a-Chip Test Access Architectures using Integer Linear Programming
Analog Test Techniques
Test Generation for Accurate Prediction of Analog Specifications / R. Voorakaranam ; A. Chatterjee
A Comprehensive TDM Comparator Scheme for Effective Analysis of Oscillation-based Test / J. Roh
Test Selection Based on High Level Fault Simulation for Mixed-signal Systems / S. Ozev ; A. Orailoglu
BIST: Arithmetic, Memories and ILAs
Integrating Logic BIST in VLSI Designs with Embedded Memories / V. Chickermane ; S. Richter ; C. Barnhart
Synthesis for Arithmetic Built-in Self-test / A. P. Stroele
A General BIST-amenable Method of Test Generation for Iterative Logic Arrays / K. O. Boateng ; H. Takahashi ; Y. Takamatsu
Emerging Test Technology Challenges: Discover the Analysis behind the New ITRS Roadmaps
RF/Analog Test of Circuits and Systems
Temperature and Process Drift Issues
Cold Delay Defect Screening / C.-W. Tseng ; E. J. McCluskey ; X. Shao ; D. M. Wu
Thermal Testing: Fault Location Strategies / J. Altet ; A. Rubio ; E. Schaub ; S. Dialhaire ; W. Claeys
Detection of CMOS Defects under Variable Processing Conditions / A. Germida ; J. Plusquellic
Test Compaction and Design Validation
SIFAR: Static Test Compaction for Synchronous Sequential Circuits Based on Single Fault Restoration / X. Lin ; W-T. Cheng ; I. Pomeranz ; S. M. Reddy
Space Compaction of Test Responses for IP Cores using Orthogonal Transmission Functions / M. Seuring
ESIM: A Multimodel Design Error and Fault Simulator for Logic Circuits / H. Al-Asaad ; J. P. Hayes
Analog BIST
An Effective Defect-oriented BIST Architecture for High-speed Phase-locked Loops / S. Kim ; M. Soma ; D. Risbud
Characterization of a Pseudo-random Testing Technique for Analog and Mixed-signal Built-in-self-test / J. A. Tofte ; C-K. Ong ; J-L. Huang
Hardware Resource Minimization for Histogram-based ADC BIST / M. Renovell ; F. Azais ; S. Bernard ; Y. Bertrand
Functional Test and Verification Issues
Defuse: A Deterministic Functional Self-test Methodology for Processors / L. Chen ; S. Dey
Testing, Verification, and Diagnosis in the Presence of Unknowns / A. Jain ; V. Boppana ; R. Mukherjee ; J. Jain ; M. Fujita ; M. Hsiao
Using Arithmetic Transform for Verification of Datapath Circuits via Error Modeling / K. Radecka ; Z. Zilic
Memory Test
Functional Memory Faults: A Formal Notation and a Taxonomy / A. J. van de Goor ; Z. Al-Ars
Simulation-based Test Algorithm Generation for Random Access Memories / C-F. Wu ; C-T. Huang ; K-L. Cheng ; C-W. Wu
Detection of Inter-port Faults in Multi-port Static RAMs / J. Zhao ; S. Irrinki ; M. Puri ; F. Lombardi
Open Defect Detection, Diagnosis and Analog BIST
Detectability Conditions for Interconnection Open Defects / V. H. Champac ; A. Zenteno
A Technique for Logic Fault Diagnosis of Interconnect Open Defects / S. Venkataraman ; S. B. Drummonds
Fault Detection Methodology and BIST Method for 2nd Order Butterworth, Chebyshev and Bessel Filter Approximations / J. V. Calvano ; V. C. Alves ; M. Lubaszewski
How Should Fault Coverage be Defined?
External and Embedded Resources: How to Optimize Test Resource Partitioning (TRP)?
Biomedical ICs: What is Different About Testing Those ICs?
Delay Test, Diagnosis and BIST
Bounding Circuit Delay by Testing a Very Small Subset of Paths / M. Sharma ; J. H. Patel
On Test Set Generation for Efficient Path Delay Fault Diagnosis / R. C. Tekumalla
A Low-speed BIST Framework for High-performance Circuit Testing / H. Speek ; H. G. Kerkhoff ; M. Shashaani ; M. Sachdev
BIST Issues
Hidden Markov and Independence Models with Patterns for Sequential BIST / L. Brehelin ; O. Gascuel ; G. Caraux ; P. Girard ; C. Landrault
Reducing Test Application Time for Built-in-self-test Test Pattern Generators / I. Hamzaoglu
Linear Independence as Evaluation Criterion for Two-dimensional Test Pattern Generators / G. Mrugalski ; J. Tyszer ; J. Rajski
P1450.1: STIL for the Simulation Environment / P. Wohl ; N. Biggs
Extraction of Peak-to-peak and RMS Sinusoidal Jitter using an Analytic Signal Method / T. J. Yamaguchi ; M. Ishida ; T. Watanabe ; T. Ohmi
Crosstalk Effect Removal for Analog Measurement in Analog Test Bus / C. Su ; Y-T. Chen
High Level ATPG and Test Scheduling
High-level Observability for Effective High-level ATPG
The Left Edge Algorithm and the Tree Growing Technique in Block-Test Scheduling under Power Constraints / V. Muresan ; X. Wang ; M. Vladutiu
Testability Alternatives Exploration through Functional Testing / F. Ferrandi ; G. Ferrara ; G. Fornara ; F. Fummi ; D. Sciuto
IDDQ Test
Efficient Diagnosis of Single/Double Bridging Faults with Delta lddq Probabilistic Signatures and Viterbi Algorithm / C. Thibeault
Delta lddq for Testing Reliability / T. J. Powell ; J. Pair ; M. St. John ; D. Counce
Clustering Based Evaluation of IDDQ Measurements: Applications in Testing and Classification of ICs / S. Jandhyala ; H. Balachandran ; M. Sengupta ; A. P. Jayasumana
On-line Testing and Fault Tolerance
Fault Escapes in Duplex Systems / S. Mitra ; N. R. Saxena
Invariance-based On-line Test for RTL Controller-datapath Circuits / Y. Makris ; I. Bayraktaroglu
Word Voter: A New Voter Design for Triple Modular Redundant Systems
Panel / Special Session 6:
SOC Test: Is P1500 All What You Need?
Do I Need This Tool for My Chips to Work?
High End and Low End Applications for Defective Chips: Enhanced Availability and Acceptability
Author Index
Foreword
Organizing Committee
Steering Committee
5.

図書

図書
sponsored by IEEE Computer Society Test Technology Technical Council, Tenth Anniversary Committee of Asian Test Symposium
出版情報: Los Alamitos, Calif. : IEEE Computer Society, c2001  xii, 374 p. ; 28 cm
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Preface
Editorial Board
ATS 1992
An Approach to Design-for-Testability for Memory Embedding Logic LSIs / K. Hatayama ; T. Hayashi ; M. Takakura ; T. Suzuki ; S. Michishita ; H. Satoh
Synthesis for Testability of PLA Based Finite State Machines / M. Avedillo ; J. Quintana ; J. Huertas
A Concurrent Fault Detection Method for Superscalar Processors / A. Pawlovsky ; M. Hanawa
A Method of Diagnosing Logical Faults in Combinational Circuits / K. Yamazaki ; T. Yamada
Reduction of Dynamic Memory Usage in Concurrent Fault Simulation for Synchronous Sequential Circuits / K. Kim ; K. Saluja
ATS 1993
Test Set Partitioning and Dynamic Fault Dictionaries for Sequential Circuits / P. Ryan ; W. Fuchs
A Two-Phase Fault Simulation Scheme for Sequential Circuits / W. Wu ; C. Lee ; J. Chen
GID-Testable Two-Dimensional Sequential Arrays for Self-Testing / W. Huang ; F. Lombardi ; M. Lu
A Global BIST Methodology / T. Gheewala ; H. Sucar ; P. Varma
On Properties and Implementations of Inverting ALSC for Use in Built-in Self-Testing / K. Furuya ; P. Koh ; E. McCluskey
ATS 1994
Efficient Test Sequence Generation for Localization of Multiple Faults in Communication Protocols / Y. Kakuda ; H. Yukitomo ; S. Kusumoto ; T. Kikuno
Design of Random Pattern Testable Floating Point Adders / J. Rajski ; J. Tyszer
Testability Considerations in Technology Mapping / I. Pomeranz ; S. Reddy
Analysis and Improvement of Testability Measure Approximation Algorithms / J. Bitner ; J. Jain ; J. Abraham ; D. Fussell
Efficiency Improvements for Multiple Fault Diagnosis of Combinational Circuits / N. Yanagida ; H. Takahashi ; Y. Takamatsu
Boolean Process--An Analytical Approach to Circuit Representation / Y. Min
ATS 1995
Software Transformations for Sequential Test Generation / A. Balakrishnan ; S. Chakradhar
DC Control and Observation Structures for Analog Circuits / Y.-R. Shieh ; C.-W. Wu
Universal Test Complexity of Field-Programmable Gate Arrays / T. Inoue ; H. Fujiwara ; H. Michinishi ; T. Yokohira ; T. Okamoto
A Design-for-Test Technique for Multi-stage Analog Circuits / M. Renovell ; F. Azais ; Y. Bertrand
Fanout Fault Analysis for Digital Logic Circuits / W. Shen ; B. Chen
Theory and Applications of Cellular Automata for Synthesis of Easily Testable Combinational Logic / S. Nandi ; P. Chaudhuri
Low Power Design and Its Testability / H. Ueda ; K. Kinoshita
ATS 1996
Redundancy Identification Using Transitive Closure / V. Agrawal ; M. Bushnell ; Q. Lin
A Consistent Scan Design System for Large-Scale ASICs / Y. Konno ; K. Nakamura ; T. Bitoh ; K. Saga ; S. Yano
Combination of Automatic Test Pattern Generation and Built-in Intermediate Voltage Sensing for Detecting CMOS Bridging Faults / K.-J. Lee ; J.-J. Tang ; T.-C. Huang ; C.-L. Tsai
Partially Parallel Scan Chain for Test Length Reduction by Using Retiming Technique / Y. Higami ; S. Kajihara
An Efficient Compact Test Generator for I[subscript DDQ] Testing / H. Kondo ; K.-T. Cheng
ATS 1997
FaultMaxx: A Perturbation Based Fault Modeling and Simulation for Mixed-Signal Circuits / N. Ben-Hamida ; K. Saab ; D. Marche ; B. Kaminska
On the Complexity of Universal Fault Diagnosis for Look-up Table FPGAs / S. Miyazaki
Testing for the Programming Circuit of LUT-Based FPGAs
Test Length for Random Testing of Sequential Machines Application to RAMs / R. David
A Genetic Algorithm for Computation of Initialization Sequences for Synchronous Sequential Circuits / F. Corno ; P. Prinetto ; M. Rebaudengo ; M. Reorda ; G. Squillero
On Chip Weighted Random Patterns / J. Savir
ATS 1998
Vector Restoration Using Accelerated Validation and Refinement / S. Bommu ; K. Doreswamy
March LA: A Test for All Linked Memory Faults / A. van de Goor ; G. Gaydadjiev ; V. Yarmolik ; V. Mikitjuk
Test Cycle Count Reduction in a Parallel Scan BIST Environment / B. Ayari
BIST TPG for Combinational Cluster (Glue Logic) Interconnect Testing at Board Level / C.-H. Chiang ; S. Gupta
False-Path Removal Using Delay Fault Simulation / M. Gharaybeh
A Ring Architecture Strategy for BIST Test Pattern Generation / C. Fagot ; O. Gascuel ; P. Girard ; C. Landrault
ATS 1999
High Resolution CD-SEM System / Y. Ose ; M. Ezumi ; H. Todokoro
An Evaluation of Test Generation Algorithms for Combinational Circuits / S. Xu ; T. Frank
An Effective Methodology for Mixed Scan and Reset Design Based on Test Generation and Structure of Sequential Circuits / H.-C. Liang
Circuit Partitioning for Low Power BIST Design with Minimized Peak Power Consumption / L. Guiller ; S. Pravossoudovitch
New DFT Techniques of Non-scan Sequential Circuits with Complete Fault Efficiency / D. Das ; S. Ohtake
ATS 2000
Test Generation for Crosstalk-Induced Faults: Framework and Computational Results / W.-Y. Chen ; M. Breuer
A Class of Sequential Circuits with Combinational Test Generation Complexity under Single-Fault Assumption / M. Inoue ; E. Gizdarski
Fast Hierarchical Test Path Construction for DFT-Free Controller-Datapath Circuits / Y. Makris ; J. Collins ; A. Orailoglu
A New Framework for Static Timing Analysis, Incremental Timing Refinement, and Timing Simulation / L.-C. Chen
Accelerated Test Pattern Generators for Mixed-Mode BIST Environments / W.-L. Wang
ATS 2001
Short Circuit Faults in State-of-the-Art ADCs--Are They Hard or Soft? / A. Lechner ; A. Richardson ; B. Hermes
EB-Testing-Pad Method and Its Evaluation by Actual Devices / N. Kuji ; T. Ishihara
Robust Self Concurrent Test of Linear Digital Systems / E. Simeu ; A. Abdelhay ; M. Naal
Resource Allocation and Test Scheduling for Concurrent Test of Core-Based SOC Design / Y. Huang ; W.-T. Cheng ; C.-C. Tsai ; N. Mukherjee ; O. Samman ; Y. Zaidan
Design for Hierarchical Two-Pattern Testability of Data Paths / Md. Altaf-Ul-Amin
Author Index
Preface
Editorial Board
ATS 1992
6.

図書

図書
sponsored by IEEE Computer Society Test Technology Technical Council ; in cooperation with Technical Group on Fault Tolerant Systems ... [et al.]
出版情報: Los Alamitos, Calif. : IEEE Computer Society, c2001  xxvi, 473 p. ; 28 cm
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Message from the Symposium Chair
Message from the Program Chair
Message from the 10th Anniversary Committee Chair
ATS 2000 Best Paper Award
Asian Test Committee
The 10th Asian Test Symposium Committee
Program Committee
Reviewers
TTTC Activities Board
Plenary Session: Keynote Address
DFT for High-Quality Low Cost Manufacturing Test / Janusz Rajski (Mentor Graphics Corporation, USA)
Design for Testability / Session 1A:
Design for Hierarchical Two-Pattern Testability of Data Paths / Md. Altaf-UI-Amin ; S. Ohtake ; H. Fujiwara
A Multiple Phase Partial Scan Design Method / D. Xiang ; Y. Xu
Sequential Redundancy Removal Using Test Generation and Multiple Unreachable States / H. Yotsuyanagi ; S. Hata ; M. Hashizume ; T. Tamesada
Fault Modeling for Memories / Session 1B:
Tests for Resistive and Capacitive Defects in Address Decoders / M. Klaus ; Ad J. van de Goor
Detecting Unique Faults in Multi-port SRAMs / S. Hamdioui ; D. Eastwick ; M. Rodgers
A Memory Specific Notation for Fault Modeling / Z. Al-Ars ; J. Braun ; D. Richter
Diagnosis / Session 1C:
On Pass/Fail Dictionaries for Scan Circuits / I. Pomeranz
Diagnosis by Repeated Application of Specific Test Inputs and by Output Monitoring of the MISA / M. Gossel ; V. Ocheretnij ; S. Chakrabarty
Simulation-Based Diagnosis for Crosstalk Faults in Sequential Circuits / H. Takahashi ; M. Phadoongsidhi ; Y. Higami ; K. Saluja ; Y. Takamatsu
ATPG / Session 2A:
Test Generation for Double Stuck-at Faults / N. Takahashi
Faulty Resistance Sectioning Technique for Resistive Bridging Fault ATPG Systems / T. Shinogi ; T. Kanbayashi ; T. Yoshikawa ; S. Tsuruoka ; T. Hayashi
On Improving a Fault Simulation Based Test Generator for Synchronous Sequential Circuits / R. Guo ; S. Reddy
Embedded Memory Test / Session 2B:
Automatic Generation of Memory Built-in Self-Test Cores for System-on-Chip / K.-L. Cheng ; C.-M. Hsueh ; J.-R. Huang ; J.-C. Yeh ; C.-T. Huang ; C.-W. Wu
A P1500 Compliant BIST-Based Approach to Embedded RAM Diagnosis / D. Appello ; F. Corno ; M. Giovinetto ; M. Rebaudengo ; M. Reorda
A Built-in Self-Test and Self-Diagnosis Scheme for Heterogeneous SRAM Clusters / C.-W. Wang ; R.-S. Tzeng ; C.-F. Wu ; S.-Y. Huang ; S.-H. Lin ; H.-P. Wang
I[subscript DDQ] Test and Diagnosis / Session 2C:
I[subscript DDQ] Sensing Technique for High Speed I[subscript DDQ] Testing / T. Takeda ; M. Ichimiya ; Y. Miura ; K. Kinoshita
CMOS Open Defect Detection Based on Supply Current in Time-Variable Electric Field and Supply Voltage Application
An Approach to Improve the Resolution of Defect-Based Diagnosis / I. Yamazaki ; H. Yamanaka ; T. Ikeda ; M. Takakura ; Y. Sato
Test Compaction / Session 3A:
A Postprocessing Procedure to Reduce the Number of Different Test Lengths in a Test Set for Scan Circuits
A Method of Static Compaction of Test Stimuli / K. Boateng ; H. Konishi ; T. Nakata
Dynamic Test Compression Using Statistical Coding / H. Ichihara ; A. Ogawa ; T. Inoue ; A. Tamura
Pattern Generation for Memory Test / Session 3B:
Guardband Determination for the Detection of Off-State and Junction Leakages in DRAM Testing / M.-J. Wang ; R.-L. Jiang ; J.-W. Hsia ; C.-H. Wang ; J. Chen
Memory Read Faults: Taxonomy and Automatic Test Generation / A. Benso ; S. Di Carlo ; G. Di Natale ; P. Prinetto
Simulation and Development of Short Transparent Tests for RAM / S. Demidenko ; A. van de Goor ; S. Henderson ; P. Knoppers
Virtual Tester and Beam Testing / Session 3C:
Test Time Reduction through Minimum Execution of Tester-Hardware Setting Instructions / J. Hirase
EB-Testing-Pad Method and Its Evaluation by Actual Devices / N. Kuji ; T. Ishihara
Benefits of Phase Interference Detection to IC Waveform Probing / J. Block ; W. Lo ; C. Shaw
SoC Test Access Mechanism / Session 4A:
A DFT Method for Core-Based Systems-on-a-Chip Based on Consecutive Testability / T. Yoneda
Compaction Schemes with Minimum Test Application Time / O. Sinanoglu ; A. Orailoglu
Design of an Optimal Test Access Architecture Using a Genetic Algorithm / Z. Ebadi ; A. Ivanov
RTL ATPG / Session 4B:
An RT-Level ATPG Based on Clustering of Circuit States / H. Li ; Y. Min ; Z. Li
An Approach to RTL Fault Extraction and Test Generation / Z. Yin ; X. Li
Effective Techniques for High-Level ATPG / G. Cumani ; G. Squillero
Delay Test / Session 4C:
An Efficient Method to Identify Untestable Path Delay Faults / Y. Shao ; S. Kajihara
SpeedGrade: An RTL Path Delay Fault Simulator / K. Kim ; R. Jayabharathi ; C. Carstens
Test Generation for Multiple-Threshold Gate-Delay Fault Model / M. Nakao ; Y. Kiyoshige ; K. Hatayama ; T. Nagumo
SoC Test Scheduling / Session 5A:
A Gated Clock Scheme for Low Power Scan Testing of Logic ICs or Embedded Cores / Y. Bonhomme ; P. Girard ; L. Guiller ; C. Landrault ; S. Pravossoudovitch
Test Scheduling and Scan-Chain Division under Power Constraint / E. Larsson ; Z. Peng
Resource Allocation and Test Scheduling for Concurrent Test of Core-Based SoC Design / Y. Huang ; W.-T. Cheng ; C.-C. Tsai ; N. Mukherjee ; O. Samman ; Y. Zaidan
FSM Test / Session 5B:
A Unified Scheme for Designing Testable State Machines / P. Lala ; A. Walker
Generation of an Ordered Sequence of Test Vectors for Single State Transition Faults in Large Sequential Machines / S. Goswami ; A. Chanda ; D. Choudhury
Enhancing BIST Quality of Sequential Machines through Degree-of-Freedom Analysis / B. Sikdar ; S. Roy ; D. Das
On-line Testing and Fault Injection / Session 5C:
Robust Self Concurrent Test of Linear Digital Systems / E. Simeu ; A. Abdelhay ; M. Naal
Control-Flow Checking via Regular Expressions / L. Tagliaferri
FPGA-Based Fault Injection for Microprocessor Systems / P. Civera ; L. Macchiarulo ; M. Violante
Advances in BIST / Session 6A:
A BIST Method Based on Concurrent Single-Control Testability of RTL Data Paths / K. Yamaguchi ; H. Wada ; T. Masuzawa
Faults in Processor Control Subsystems: Testing Correctness and Performance Faults in the Data Prefetching Unit / S. Almukhaizim ; P. Petrov
A SmartBIST Variant with Guaranteed Encoding / B. Koenemann ; C. Barnhart ; B. Keller ; T. Snethen ; O. Farnsworth ; D. Wheater
Analog Test / Session 6B:
MEMS Comb-Actuator Resonance Measurement Method Using the 2[superscript nd] Harmonics of the GND Current / Y. Takahashi
On Test and Characterization of Analog Linear Time-Invariant Circuits Using Neural Networks / Z. Guo ; X. Zhang ; J. Savir ; Y.-Q. Shi
Specification Based Digital Compatible Built-in Test of Embedded Analog Circuits / A. Halder ; A. Chatterjee
Fault Tolerance / Session 6C:
Yield Increase of VLSI after Redundancy-Repairing
An Improvement in Weight-Fault Tolerance of Feedforward Neural Networks / N. Kamiura ; Y. Taniguchi ; T. Isokawa ; N. Matsui
A New Code-Disjoint Sum-Bit Duplicated Carry Look-Ahead Adder for Parity Codes / E. Sogomonyan
Various Ideas for BIST / Session 7A:
Selecting a PRPG: Randomness, Primitiveness, or Sheer Luck? / I. Bayraktaroglu
Hybrid BIST Using Partially Rotational Scan / K. Ichino ; T. Asakawa ; S. Fukumoto ; K. Iwasaki
Multiple Attractor Cellular Automata for Hierarchical Diagnosis of VLSI Circuits / N. Ganguly ; A. Karmakar ; S. Chowdhury ; P. Chaudhuri
A Microcode-Based Memory BIST Implementing Modified March Algorithm / D. Youn ; T. Kim ; S. Park
Fault Simulation for VHDL Based Test Bench and BIST Evaluation / H. Farshbaf ; M. Zolfy ; S. Mirkhani ; Z. Navabi
Analog/Mixed Signal Test / Session 7B:
Automatic Test Generation for Analog Circuits Using Compact Test Transfer Function Models / B. Sahu
Distance Constrained Dimensionality Reduction for Parametric Fault Test Generator / A. Gomes
Short Circuit Faults in State-of-the-Art ADCs - Are They Hard or Soft? / A. Lechner ; A. Richardson ; B. Hermes
An Embedded Built-in-Self-Test Approach for Digital-to-Analog Converters / J.-H. Tsai ; M.-J. Hsiao ; T.-Y. Chang
Verification / Session 7C:
An Improved AVPG Algorithm for SoC Design Verification Using Port Order Fault Model / C.-Y. Wang ; S.-W. Tung ; J.-Y. Jou
Framework of Timed Trace Theoretic Verification Revisited / B. Zhou ; C. Myers
Efficient Pattern-Based Verification of Connections to IP Cores / I. Polian ; W. Gunther ; B. Becker
Design Verification and Robust Design Technique for Cross-Talk Faults / B. Paul ; S.-H. Choi ; Y. Im ; K. Roy
DFT Application to Real Chips / Poster Session 1:
A Practical Logic BIST for ASIC Designs / M. Sato ; K. Tsutsumida ; T. Ikeya ; M. Kawashima
TX7901 DFT / T. Kamada
An Application of Partial Scan Techniques to a High-End System LSI Design / T. Ono ; A. Kozawa ; T. Kimura ; Y. Konno ; K. Saga
Built-out Self-Test (BOST) for Analog Circuits in a System LSI: Test Solution to Reduce Test Costs / H. Hanai ; S. Yamada ; H. Mori ; E. Yamashita ; T. Funakura
High-Speed Interface Testing / M. Suzuki ; R. Shimizu ; N. Naka ; K. Nakamura
A New Inter-core Built-in-Self-Test Circuits for Tri-state Buffers in the System on a Chip / T. Kishi ; M. Ohta ; T. Taniguchi ; H. Kadota
A Flexible Logic BIST Scheme and Its Application to SoC Designs / X. Wen
Practical Ideas from Universities / Poster Session 2:
Experimental Results of Forward-Looking Reverse Order Fault Simulation on Industrial Circuits with Scan / X. Lin
Non-exhaustive Parity Testing / S. Xu
Built-in Self-Test for State Faults Induced by Crosstalk in Sequential Circuits / K. Shimizu ; N. Itazaki
A Low-Power LFSR Architecture / T.-C. Huang ; K.-J. Lee
Author Index
Message from the Symposium Chair
Message from the Program Chair
Message from the 10th Anniversary Committee Chair
7.

図書

図書
sponsored by IEEE Computer Society, Test Technology Technical Council and IEEE Philadelphia Section
出版情報: Washington, D.C. : International Test Conference, c2001  xiv, 1201 p. ; 29 cm
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8.

図書

図書
sponsored by IEEE Computer Society Test Technology Technical Council
出版情報: Los Alamitos, Calif. : IEEE Computer Society, c2003  xxvii, 432 p. ; 28 cm
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9.

図書

図書
[sponsored by the IEEE Computer Society Test Technology Technical Council, the IEEE Computer Society Technical Committee on Fault-Tolerant Computing]
出版情報: Los Alamitos, Calif. : IEEE Computer Society, c2002  xiii, 441 p. ; 23 cm
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目次情報: 続きを見る
Message from the Symposium Chairs
Organizing Committee
Program Committee
Yield I / Session 1:
Manufacturability Analysis of Analog CMOS ICs Through Examination of Multiple Layout Solutions / P. Khademsameni ; M. Syrzycki
Effect of Static Power Dissipation in Burn-In Environment on Yield of VLSI / A. Vassighi ; O. Semenov ; M. Sachdev ; A. Keshavarzi
Yield Estimates for the TESH Multicomputer Network / B. M. Maziarz ; V. K. Jain
Crosstalk Faults / Session 2:
A Simplified Gate-Level Fault Model for Crosstalk Effects Analysis / P. Civera ; L. Macchiarulo ; M. Violante
A Test-Vector Generation Methodology for Crosstalk Noise Faults / H. Hashempour ; Y.-B. Kim ; N. Park
Self-Checking and ABFT / Session 3:
A Parity Code Based Fault Detection for an Implementation of the Advanced Encryption Standard / G. Bertoni ; L. Breveglieri ; I. Koren ; P. Maistri ; V. Piuri
Designing Self-Checking FPGAs Through Error Detection Codes / C. Bolchini ; F. Salice ; D. Sciuto
Self-Checking 1-out-of-n CMOS Current-Mode Checker / J. Mathew ; E. Dubrova
Partially Duplicated Code-Disjoint Carry-Skip Adder / D. Marienfeld ; V. Ocheretnij ; M. Gossel ; E. S. Sogomonyan
Input Ordering in Concurrent Checkers to Reduce Power Consumption / K. Mohanram ; N. A. Touba
Fault Simulation and Injection I / Session 4:
New Methods for Evaluating the Impact of Single Event Transients in VDSM ICs / D. Alexandrescu ; L. Anghel ; M. Nicolaidis
Injecting Bit Flip Faults by Means of a Purely Software Approach: A Case Studied / R. Velazco ; A. Corominas ; P. Ferreyra
Gate-Delay Fault Diagnosis Using the Inject-and-Evaluate Paradigm / H.-B. Wang ; S.-Y. Huang ; J.-R. Huang
Scan Design / Session 5:
Scan Architecture for Shift and Capture Cycle Power Reduction / P. M. Rosinger ; B. M. Al-Hashimi ; N. Nicolici
Inserting Test Points to Control Peak Power During Scan Testing / R. Sankaralingam
Adaptable Voltage Scan Testing of Charge-Sharing Faults for Domino Circuits / C.-H. Cheng
Test Application / Session 6:
Matrix-Based Test Vector Decompression Using an Embedded Processor / K. J. Balakrishnan
Data Compression for System-on-Chip Testing Using ATE / F. Karimi ; W. Meleis ; Z. Navabi ; F. Lombardi
Test Generation / Session 7:
Fortuitous Detection and Its Impact on Test Set Sizes Using Stuck-At and Transition Faults / J. Dworak ; J. Wingfield ; B. Cobb ; S. Lee ; L.-C. Wang ; M. R. Mercer
Test Time Reduction in a Manufacturing Environment by Combining BIST and ATE / F. J. Meyer
Testing Digital Circuits with Constraints / A. A. Al-Yamani ; S. Mitra ; E. J. McCluskey
Concurrent Error Detection / Session 8:
On-Line Testing of Transient Faults Affecting Functional Blocks of FCMOS, Domino and FPGA-Implemented Self-Checking Circuits / C. Metra ; S. Di Francescantonio ; G. Marrale
Self-Checking and Fault Tolerance Quality Assessment Using Fault Sampling / F. M. Goncalves ; M. B. Santos ; I. C. Teixeira ; J. P. Teixeira
A Memory Overhead Evaluation of the Interleaved Signature Instruction Stream / F. Rodriguez ; J. C. Campelo ; J. J. Serrano
Fault-Tolerant CAM Architectures: A Design Framework / M. G. Sami ; R. Stefanelli
Fault Simulation and Injection II / Session 9:
Using Run-Time Reconfiguration for Fault Injection in Hardware Prototypes / L. Antoni ; R. Leveugle ; B. Feher
A Fault Hypothesis Study on the TTP/C Using VHDL-Based and Pin-Level Fault Injection Techniques / S. Blanc ; J. Gracia ; P. J. Gil
Fault List Compaction Through Static Timing Analysis for Efficient Fault Injection Experiments / M. Sonza Reorda
Interconnect / Session 10:
Performance of Deadlock-Free Adaptive Routing for Hierarchical Interconnection Network TESH / S. Horiguchi ; Y. Miura
Modeling of FPGA Local/Global Interconnect Resources and Derivation of Minimal Test Configurations / X. Sun ; A. Alimohammad ; P. Trouborst
Testing Layered Interconnection Networks
Yield II / Session 11:
Repair Yield Simulation with Iterative Critical Area Analysis for Different Types of Failure / Y. Hamamura ; K. Nemoto ; T. Kumazawa ; H. Iwata ; K. Okuyama ; S. Kamohara ; A. Sugimoto
Yield Modeling of a WSI Telcom Router Architecture / B. Qiu ; Y. Savaria ; M. Lu ; C. Wang ; C. Thibeault
System-on-Chip Test / Session 12:
Fast and Energy-Frugal Deterministic Test Through Test Vector Correlation Exploitation / O. Sinanoglu ; A. Orailoglu
Adaptive Test Scheduling in SoC's by Dynamic Partitioning / D. Zhao ; S. Upadhyaya
Feasibility of CED / Session 13:
Duplication-Based Concurrent Error Detection in Asynchronous Circuits: Shortcomings and Remedies / T. Verdel ; Y. Makris
Feasibility Study of Designing TSC Sequential Circuits with 100% Fault Coverage / S. J. Piestrak
Test / Session 14:
Emulation-Based Design Errors Identification / A. CasteInuovo ; A. Fin ; F. Fummi ; F. Sforza
A New Functional Fault Model for FPGA Application-Oriented Testing / M. Rebaudengo
Neighbor Current Ratio (NCR): A New Metric for I[subscript DDQ] Data Analysis / S. S. Sabade ; D. M. H. Walker
CMOS Standard Cells Characterization for I[subscript DDQ] Testing / W. A. Pleskacz ; T. Borejko ; W. Kuzmicz
On-Chip Jitter Measurement for Phase Locked Loops / T. Xia ; J.-C. Lo
Neural Networks-Based Parametric Testing of Analog IC / V. Stopjakova ; D. Micusik ; L. Benuskova ; M. Margala
Reliable and Repairable Memories / Session 15:
Balanced Redundancy Utilization in Embedded Memory Cores for Dependable Systems / M. Choi ; Y. B. Kim
Repairability Evaluation of Embedded Multiple Region DRAMs / Y. Chang
Author Index
TTTC Information
Message from the Symposium Chairs
Organizing Committee
Program Committee
10.

図書

図書
sponsored by IEEE Computer Society, Test Technology Technical Council and IEEE Philadelphia Section
出版情報: Washington, D.C. : International Test Conference, c2002  xvi, 1250 p. ; 29 cm
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