Message from General Chair |
Message from Program Co-Chairs |
TTTC Activities Board |
Asian Test Committee |
Organizing Committee |
Program Committee |
Reviewers |
Testing in the Fourth Dimension / Keynote Address I: |
Challenges for the Academic Test Community / Keynote Address II: |
CAD Tools on Testing / Jing-Yang JouIndustry Session I: |
DFT and BIST Techniques for the Future / H.-P. Wang ; J. Turino |
DFT Closure / F. Hayat ; T. Williams ; R. Kapur ; D. Hsu |
Current Status and Future Trend on CAD Tools for VLSI Testing / W.-T. Cheng |
Taiwan Test Industry: Value Added Testing in the New Millennium / Chung-Len LeeIndustry Session II: |
Mixed-Signal SoC Testing: Is Mixed-Signal Design-for-Test on Its Way? / Panel I: |
Collaboration between Industry and Academia in Test Research / Panel II: |
Analog and Mixed Signal Test I / Kiyoshi FuruyaSession A1: |
Test Generation for Fault Isolation in Analog Circuits Using Behavioral Models / S. Cherubal ; A. Chatterjee |
Fault Diagnosis for Linear Analog Circuits / J.-W. Lin ; C.-L. Lee ; C.-C. Su ; J.-E. Chen |
Testing Mixed-Signal Cores: Practical Oscillation-Based Test in an Analog Macrocell / G. Huertas ; D. Vazquez ; E. Peralias ; A. Rueda ; J. Huertas |
New Built-in Self-Test Technique Based on Addition/Subtraction of Selected Node Voltages / K. Ko ; M. Wong |
Memory Built-in Self-Test and Self-Diagnosis / Ad J. van de GoorSession A2: |
A Built-in Self-Test and Self-Diagnosis Scheme for Embedded SRAM / C.-W. Wang ; C.-F. Wu ; J.-F. Li ; C.-W. Wu ; T. Teng ; K. Chiu ; H.-P. Lin |
An FPGA-Based Re-Configurable Functional Tester for Memory Chips / J.-R. Huang ; C. Ong ; K. Cheng |
BIST TPG for SRAM Cluster Interconnect Testing at Board Level / C.-H. Chiang ; S. Gupta |
Efficient Built-in Self-Test Algorithm for Memory / S.-J. Wang ; C.-J. Wei |
Analog and Mixed Signal Test II / M.D. ShiehSession B1: |
Optimal Test-Set Generation for Parametric Fault Detection in Switched Capacitor Filters / W. Choi ; R. Harjani ; B. Vinnakota |
TI-BIST: A Temperature Independent Analog BIST for Switched-Capacitor Filters / L. Carro ; E. Cota ; M. Lubaszewski ; Y. Bertrand ; F. Azais ; M. Renovell |
Analog Circuit Equivalent Faults in the D.C. Domain / M. Worsman ; Y. Lee |
A Methodology for Fault Model Development for Hierarchical Linear Systems / Y.-C. Huang |
Testing a PWM Circuit Using Functional Fault Models and Compact Test Vectors for Operational Amplifiers / J. Calvano ; V. Alves |
Fault Simulation and Timing Simulation / Kazumi HatayamaSession B2: |
A New Framework for Static Timing Analysis, Incremental Timing Refinement, and Timing Simulation / L.-C. Chen ; M. Breuer |
On the Feasibility of Fault Simulation Using Partial Circuit Descriptions / I. Pomeranz ; S. Reddy |
Fsimac: A Fault Simulator for Asynchronous Sequential Circuits / S. Sur-Kolay ; M. Roncken ; K. Stevens ; P. Chaudhuri ; R. Roy |
Simulation of Resistive Bridging Fault to Minimize the Presence of Intermediate Voltage and Oscillation in CMOS Circuits / A. Keshk ; Y. Miura ; K. Kinoshita |
Non-Invasive Timing Analysis of IBM G6 Microprocessor L1 Cache Using Picosecond Imaging Circuit Analysis / S. Polonsky ; M. Mc Manus ; D. Knebel ; S. Steen ; P. Sanda |
Fringe Meeting: SoC Testing and P1500 Standard / Shianling Wu ; Yervant Zorian |
Fault Analysis I / Shiyi XuSession C1: |
An Experimental Analysis of Spot Defects in SRAMs: Realistic Fault Models and Tests / S. Hamdioui |
Enhanced Untestable Path Analysis Using Edge Graphs / S. Kajihara ; T. Shimono |
A Waveform Simulator Based on Boolean Process / L. Li ; X. Yu ; Y. Min |
On the Superiority of DO-RE-ME/MPG-D over Stuck-at-Based Defective Part Level Prediction / J. Dworak ; M. Grimaila ; B. Cobb ; T-C. Wang ; Li-C. Wang ; M. Mercer |
Test Generation I / Yukihiro IguchiSession C2: |
Compaction-Based Test Generation Using State and Fault Information / A. Giani ; S. Sheng ; M. Hsiao ; V. Agrawal |
Test Sequence Compaction for Sequential Circuits with Reset States / Y. Higami ; Y. Takamatsu |
SPIRIT: Satisfiability Problem Implementation for Redundancy Identification and Test Generation / E. Gizdarski ; H. Fujiwara |
Forecasting the Efficiency of Test Generation Algorithms for Digital Circuits / S. Xu ; W. Cen |
Functional Testing / Tomoo InoueSession C3: |
Fast Hierarchical Test Path Construction for DFT-Free Controller-Datapath Circuits / Y. Makris ; J. Collins ; A. Orailoglu |
Faster Processing for Microprocessor Functional ATPG / J. Hirase ; S. Yoshimura |
Verification of Deadlock Free Property of High Level Robot Control / H. Hiraishi |
Functional Testing of Microprocessors with Graded Fault Coverage / R. Kannah ; C. Ravikumar |
Built-in Self-Test I / Jacob SavirSession D1: |
Single-Control Testability of RTL Data Paths for BIST / T. Masuzawa ; M. Izutsu ; H. Wada |
A BIST Methodology for At-Speed Testing of Data Communications Transceivers / S. Lin ; S. Mourad ; S. Krishnan |
High-Speed Generation of LFSR Signatures / M.-D. Shieh ; H.-F. Lo ; M.-H. Sheu |
Software Testing and Test Synthesis / Wen-Ben JoneSession D2: |
Strong Self-Testability for Data Paths High-Level Synthesis / X. Li |
Generating Test Items for Checking Illegal Behaviors in Software Testing / M. Hirayama ; J. Okayasu ; T. Yamamoto ; O. Mizuno ; T. Kikuno |
Using Genetic Algorithms for Test Case Generation in Path Testing / J.-C. Lin ; P.-L. Yeh |
Embedded-Core Testing / Douglas KaySession D3: |
A Hierarchical Test Control Architecture for Core Based Design / K.-J. Lee ; C.-I. Huang |
Embedded Core Testing Using Genetic Algorithms / R. Xu |
Functional Testing and Fault Analysis Based Fault Coverage Enhancement Techniques for Embedded Core Based Systems / A. Bagwe ; R. Parekhji |
Memory Testing / Rubin A. ParekhjiSession E1: |
Detection of SRAM Cell Stability by Lowering Array Supply Voltage / D.-M. Kwai ; H.-W. Chang ; H.-J. Liao ; C.-H. Chiao ; Y.-F. Chou |
A Realistic Fault Model for Flash Memories / Y.-L. Horng ; T.-Y. Chang |
Impact of Memory Cell Array Bridges on the Faulty Behavior in Embedded DRAMs / Z. Al-Ars |
Memory Test Time Reduction by Interconnecting Test Items / W.-J. Wu ; C. Tang |
An Efficient Parallel Transparent Diagnostic BIST / D. Huang ; W.-B. Jone |
Test Generation II / Christian LandraultSession E2: |
Test Generation for Crosstalk-Induced Faults: Framework and Computational Results / W.-Y. Chen |
Testing Programmable Interconnect Systems: An Algorithmic Approach / B. Liu ; F. Lombardi ; W. Huang |
Reducing Test Application Time for Full Scan Circuits by the Addition of Transfer Sequences |
TOF: A Tool for Test Pattern Generation Optimization of an FPGA Application-Oriented Test / J. Portal ; P. Faure ; J. Figueras ; Y. Zorian |
Formal Verification of Data-Path Circuits Based on Symbolic Simulation / Y. Morihiro ; T. Yoneda |
I[subscript DDQ] Testing / Sying-Jyan WangSession E3: |
Is I[subscript DDQ] Testing not Applicable for Deep Submicron VLSI in Year 2011? / C.-W. Lu |
High Speed I[subscript DDQ] Test and Its Testability for Process Variation / M. Hashizume ; H. Yotsuyanagi ; M. Ichimiya ; T. Tamesada ; M. Takeda |
Memory Reduction of I[subscript DDQ] Test Compaction for Internal and External Bridging Faults / T. Maeda |
A High-Speed I[subscript DDQ] Sensor Implementation / Y. Antonioli ; T. Inufushi ; S. Nishikawa |
Cyclic Greedy Generation Method for Limited Number of I[subscript DDQ] Tests / T. Shinogi ; M. Ushio ; T. Hayashi |
Built-in Self-Test II / Session F1: |
Accelerated Test Pattern Generators for Mixed-Mode BIST Environments / W.-L. Wang |
Effective Parallel Processing Techniques for the Generation of Test Data for a Logic Built-in Self Test System / P. Chang ; B. Keller ; S. Paliwal |
Design and Testing of Fast and Cost Effective Serial Seeding TPGs Based on One-Dimensional Linear Hybrid Cellular Automata / A. Hlawiczka ; M. Kopec |
An Efficient BIST Design Using LFSR-ROM Architecture |
Testability Analysis and Design for Testability / Xinghao ChenSession F2: |
Novel Techniques for Improving Testability Analysis / Y.-H. Su ; C.-H. Cheng ; S.-C. Chang |
A Class of Sequential Circuits with Combinational Test Generation Complexity under Single-Fault Assumption / M. Inoue |
Design for Sequential Testability: An Internal State Reseeding Approach for 100% Fault Coverage / M. Flottes ; C. Landrault ; A. Petitqueux |
Fault Tolerance / J.C. Frank LienSession F3: |
Testing Approach within FPGA-Based Fault Tolerant Systems / A. Doumar ; H. Ito |
Transient-Fault Tolerant VHDL Descriptions: A Case-Study for Area Overhead Analysis / F. Vargas ; A. Amory |
Fault Tolerant Multistage Interconnection Networks with Widely Dispersed Paths / N. Kamiura ; T. Kodera ; N. Matsui |
A Testable/Fault-Tolerant FFT Processor Design / S.-K. Lu ; J.-S. Shih |
Fault Analysis II / Mike WongSession G1: |
Charge Sharing Fault Analysis and Testing for CMOS Domino Logic Circuits / J.-S. Wang |
Testing Domino Circuits in SOI Technology / E. MacDonald ; N. Touba |
A Case Study of Failure Analysis and Guardband Determination for a 64M-Bit DRAM / C.-T. Kao ; S. Wu |
Low-Power Testing / C.P. RavikumarSession G2: |
Peak-Power Reduction for Multiple-Scan Circuits during Test Application / T.-C. Huang ; J.-J. Chen |
An Adjacency-Based Test Pattern Generator for Low Power BIST Design / P. Girard ; L. Guiller ; S. Pravossoudovitch |
Distribution-Graph Based Approach and Extended Tree Growing Technique in Power-Constrained Block-Test Scheduling / V. Muresan ; X. Wang ; M. Vladutiu |
Self-Checking Circuits and Concurrent Fault Detection / Yinghua MinSession G3: |
A Method for Determining Whether Asynchronous Circuits Are Self-Checking / M. Liebelt ; C.-C. Lim |
On Testing Safety-Sensitive Digital Systems / J. Savir |
Accumulation-Based Concurrent Fault Detection for Linear Digital State Variable Systems / I. Bayraktaroglu |
High Performance/Delay Testing / Tutorial 1: |
SoC Testing and P1500 Standard / Tutorial 2: |
Author Index |
Call for Papers of ATS 2001 |
Message from General Chair |
Message from Program Co-Chairs |
TTTC Activities Board |