| Message from the Program Chair |
| Conferences Committees |
| Keynote Speeches |
| Eccentric SoC Architectures as the Future Norm / G. Brebner |
| NoCs: A New Contract between Hardware and Software / A. Jantsch |
| Towards the Digitally Named World--Challenges for New Social Infrastructures Based on Information Technologies / H. Yasuura |
| Customizable Embedded Processor Architectures / P. Petrov ; A. Orailoglu |
| Processor and Memory Architectures |
| Distance-aware L2 Cache Organizations for Scalable Multiprocessor Systems / S. Chung ; H. Kim ; C. Jhon |
| Unified Dual Data Caches / B. Juurlink |
| CCC: Crossbar Connected Caches for Reducing Energy Consumption of On-Chip Multiprocessors / L. Li ; N. Vijaykrishnan ; M. Kandemir ; M. Irwin ; I. Kadayif |
| Synthesis (HL, LS, PS) |
| Reversible Logic Synthesis for Minimization of Full-Adder Circuit / H. Babu ; R. Islam ; A. Chowdhury ; S. Chowdhury |
| Scheduling and Assignment for Real-time Embedded Systems with Resource Contention / L. Pontani ; D. Dupont |
| Multi Component Digital Circuit Optimization by Solving FSM Equations / N. Yevtushenko ; S. Zharikova ; M. Vetrova |
| DYNORA: A New Cache Technique / P. Srivatsan ; P. Sudarshan ; P. Bhaskaran |
| A Quadruple Precision and Dual Double Precision-Floating Point Multiplier / A. Akkas ; M. Schulte |
| Causality Constraints for Processor Architectures with Sub-Word Parallelism / R. Schaffer ; R. Merker ; F. Catthoor |
| A Methodology for the Design of AHB Bus Master Wrappers / M. Bertola ; G. Bois |
| A Constructive Algorithm with Look-Ahead for Mapping and Scheduling of Task Graphs with Conditional Edges / W. Brunnbauer ; T. Wild ; J. Foag ; N. Pazos |
| An Application of Functional Decomposition in ROM-Based FSM Implementation in FPGA Devices / M. Rawski ; H. Selvaraj ; T. Luba |
| Variations on Truncated Multiplication / J. Stine ; O. Duverne |
| Exploring Storage Organization in ASIP Synthesis / M. Jain ; M. Balakrishnan ; A. Kumar |
| RDSP: A RISC DSP Based on Residue Number System / R. Chaves ; L. Sousa |
| Operating Region Modelling of Deep-Submicron CMOS Buffers Driving Global Scope Inductive Interconnects / G. Cappuccino |
| A Scheduling and Partitioning Scheme for Low Power Circuit Operating at Multiple Voltages / L. Wang |
| Information-driven Library-Based Circuit Synthesis / L. Jozwiak ; S. Bieganski ; A. Chojnacki |
| Special Architectures |
| Low-power Branch Target Buffer for Application-Specific Embedded Processors |
| A Communication Model Based on an n-Dimensional Torus Architecture Using Deadlock-Free Wormhole Routing / P. Holzenspies ; E. Schepers ; W. Bach ; M. Jonker ; B. Sikkes ; G. Smit ; P. Havinga |
| A Development and Simulation Environment for a Floating Point Operations FPGA Based Accelerator / M. Bera ; G. Danese ; I. De Lotto ; F. Leporati ; A. Spelgatti |
| A Two-Step Genetic Algorithm for Mapping Task Graphs to a Network on Chip Architecture / T. Lei ; S. Kumar |
| System-on-a-Chip |
| A Novel Specification Model for IP-Based Design / S. Klaus ; S. Huss |
| An Efficient Implementation of Fair Load Balancing over Multi-CPU SOC Architectures / G. Kornaros ; T. Orphanoudakis ; N. Zervos |
| Design and FPGA Implementation of a Video Scalar with On-chip Reduced Memory Utilization / S. Ramachandran ; S. Srinivasan |
| Estimating the Utilization of Embedded FPGA Co-Processor / Y. Qu ; J. Soininen |
| A Dynamically Reconfigurable Accelerator for Operations over Boolean and Ternary Vectors / V. Sklyarov ; I. Skliarova ; A. Oliveira ; A. Ferrari |
| Fast Heuristics for the Edge Coloring of Large Graphs / M. Hilgemeier ; N. Drechsler ; R. Drechsler |
| Back-End Dynamic Resource Allocation Heuristics for Power-Aware High-Performance Clustered Architectures / A. Baniasadi |
| NOAH, A Tool for Augument Reduction, Serial and Parallel Decomposition of Decision Tables / M. Pleban ; H. Niewiadomski ; P. Buciak ; P. Sapiecha |
| Design Tools and Resusable Libraries for FPGA-Based Digital Circuits / P. Almeida ; M. Almeida |
| HW/SW Codesign Incorporating Edge Delays Using Dynamic Programming / K. Bhasyam ; K. Bazargan |
| Reconfigurable Randomized K-way Graph Partitioning / F. Kocan |
| Multiple Voltage and Frequency Scheduling for Power Minimization / B. Radhakrishnan ; M. Venkatesan |
| A Fast Additive Normalization Method for Exponential Computation / C. Chen ; R. Chen ; M. Sheu |
| A VLIW Architecture for Logarithmic Arithmetic / M. Arnold |
| System-on-a-Chip (2) and Validation/Verification |
| Testable Design Verification Using Petri Nets / R. Ruzicka |
| Hierarchical Constraint Conscious RT-level Test Generation / O. Sinanoglu |
| A System-on-Chip Implementation of the IEEE 802.11 a MAC Layer / G. Panic ; D. Dietterle ; Z. Stamenkovic ; K. Tittelbach-Helmrich |
| The Application of Formal Verification to SPW Designs / B. Akbarpour ; S. Tahar |
| Applications of (Embedded) Digital Systems |
| Successful Prototyping of a Real-Time Hardware Based Terrain Navigation Correlator Algorithm / F. Traugott ; K. Andersson ; A. Lofgren ; L. Lindh |
| A New Algorithm for High-Speed Projection in Point Rendering Applications / M. Amor ; M. Boo ; A. del Rio ; M. Wand ; W. Strasser |
| Sensor Platform Design for Automotive Applications / M. De Marinis ; L. Fanucci ; A. Giambastiani ; A. Renieri ; A. Rocchi ; C. Rosadini ; C. Sicilia ; D. Sicilia |
| Specification and Modeling |
| Modelling and Simulation of a Digital IC System Using SimulPet: Application to a Speech Coding Communication IC / R. Fernandez-Ramos ; J. Romero-Sanchez ; F. Rios-Gomez ; J. Martin-Canales |
| T&D-Bench+--A Software Environment for Modeling and Simulation of State-of-the-Art Processors / S. Soares ; F. Wagner |
| Back-Traced Deductive-Parallel Fault Simulation for Digital Systems / V. Hahanov ; R. Ubar ; S. Hyduke |
| Temperature Influence on Power Consumption and Time Delay / A. Golda ; A. Kos |
| A Real Time Low Latency, FPGA Implementation of the 2-D Discrete Wavelet Transformation for Streaming Image Applications / O. Benderli ; Y. Tekmen ; N. Ismailoglu |
| Understanding Video Pixel Processing Applications for Flexible Implementations / O. Gangwal ; J. Janssen ; S. Rathnam ; E. Bellers ; M. Duranton |
| Power/Area Analysis and Optimization of a DS-SS Receiver for an Integrated Sensor Microsystem / N. Aydin ; T. Arslan ; D. Cumming |
| A Power Reduction Scheme for Data Buses by Dynamic Detection of Active Bits / M. Muroyama ; A. Hyodo ; T. Okuma |
| Framed Complexity Analysis in SystemC for Multi-level Design Space Exploration / A. Wellig ; J. Zory |
| Poster Papers |
| Analytical Bounds on the Threads in IXP 1200 Network Processor / S. Ramakrishna ; H. Jamadagni |
| Concurrent Operation Scheduling and Unit Allocation with an Evolutionary Technique / G. Papa ; J. Silc |
| Exact Numerical Processing / J. Chamizo ; J. Pascual ; H. Mora |
| Stochastic Reconfigurable Hardware for Neural Networks / N. Nedjah ; L. Mourelle |
| An Iterative Improvement Co-synthesis Algorithm for Optimization of SOPC Architecture with Dynamically Reconfigurable FPGAs / R. Czarnecki ; S. Deniziak ; K. Sapiecha |
| Distributing SoC Simulations over a Network of Computers / J. Riihimaki ; V. Helminen ; K. Kuusilinna ; T. Hamalainen |
| FC-Min: A Fast Multi-Output Boolean Minimizer / P. Fiser ; J. Hlavicka ; H. Kubatova |
| A Methodology for Designing Communication Architectures for Multiprocessor SoCs / V. Dvorak ; V. Kutalek |
| Compiler-Directed Management of Instruction Accesses / G. Chen ; W. Zhang ; I. Kolcu ; U. Sezer |
| Test Scheduling for Embedded Systems / Z. Kotasek ; D. Mika ; J. Strnadel |
| Author Index |
| Message from the Program Chair |
| Conferences Committees |
| Keynote Speeches |
図書
