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1.

図書

図書
IEEE International Conference on Computer Design ; IEEE Computer Society ; IEEE Circuits and Systems Society ; IEEE Electron Devices Society
出版情報: Los Alamitos, Calif. : IEEE Computer Society, c2001  xxii, 559 p. ; 28 cm
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Welcome to ICCD
Organizing Committee
Program Committee
Additional Reviewers
ICCD 2002 Call for Papers
Keynote Addresses
The In-Car Computing Network: A Challenge for Embedded Systems / K.-T. Neumann
Clear and Present Tensions in Microprocessor Design / J. Shen
Moore's Law Meets Shannon's Law: The Evolution of the Communications Industry / L. Harrison
Technical Program
Asynchronous Techniques / Session 1.1:
Mousetrap: Ultra-High-Speed Transition-Signaling Asynchronous Pipelines / M. Singh ; S. M. Nowick
Arithmetic Logic Circuits using Self-Timed Bit Level Dataflow and Early Evaluation / R. B. Reese ; M. A. Thornton ; C. Traver
Efficient Systematic Error-Correcting Codes for Semi-Delay-Insensitive Data Transmission / F.-C. Cheng ; S.-L. Ho
Embedded Tutorial / Session 1.2:
Session Abstract
Design Constraints for Efficient Cryptographic Processing in Smart Cards / J.-F. Dhem
Security of Smartcard Integrated Circuits / E. von Faber
Architectural Modeling: Performance and Power Analysis / Session 1.3:
Minimal Subset Evaluation: Rapid Warm-Up for Simulated Hardware State / J. W. Haskins, Jr. ; K. Skadron
A Framework for Energy Estimation of VLIW Architecture / H. S. Kim ; N. Vijaykrishnan ; M. Kandemir ; M. J. Irwin
High-Level Power Modeling of CPLDs and FPGAs / L. Shang ; N. K. Jha
Caching / Session 2.1:
Symbolic Cache: Fast Memory Access Based on Program Syntax Correlation of Loads and Stores / Q. Ma ; J.-K. Peir ; L. Peng ; K. Lai
In-Line Interrupt Handling for Software-Managed TLBs / A. Jaleel ; B. Jacob
Design of a Predictive Filter Cache for Energy Savings in High Performance Processor Architectures / W. Tang ; R. Gupta ; A. Nicolau
Simulation Based Verification / Session 2.2:
A New Functional Test Program Generation Methodology / F. Fallah ; K. Takayama
A Functional Validation Technique: Biased-Random Simulation Guided by Observability-Based Coverage / S. Tasiran ; D. G. Chinnery ; S. J. Weber ; K. Keutzer
Selecting a Well Distributed Hard Case Test Suite for IEEE Standard Floating Point Division / L. D. McFearin ; D. W. Matula
Modeling of Capacitance and Crosstalk Noise / Session 2.3:
Linear Time Hierarchical Capacitance Extraction without Multipole Expansion / S. Balakrishnan ; J. H. Park ; H. Kim ; Y.-M. Lee ; C. C.-P. Chen
Analysis and Reduction of Capacitive Coupling Noise in High-Speed VLSI Circuits / P. Heydari ; M. Pedram
Crosstalk Noise Estimation for Generic RC Trees / M. Takahashi ; M. Hashimoto ; H. Onodera
Improving the Performance of Caching Structures / Session 3.1:
A Banked-Promotion TLB for High Performance and Low Power / J.-H. Lee ; J.-S. Lee ; S.-W. Jeong ; S.-D. Kim
Filtering Superfluous Prefetches Using Density Vectors / W.-F. Lin ; S. K. Reinhardt ; D. Burger ; T. R. Puzak
Allocation by Conflict: A Simple, Effective Multilateral Cache Management Scheme / E. S. Tam ; S. A. Vlaovic ; G. S. Tyson ; E. S. Davidson
Test Pattern Generation, Test Compaction, and Test Point Insertion for Synchronous Sequential Circuits / Session 3.2:
COREL: A Dynamic Compaction Procedure for Synchronous Sequential Circuits with Repetition and Local Static Compaction / I. Pomeranz ; S. M. Reddy
A Partitioning and Storage Based Built-In Test Pattern Generation Method for Synchronous Sequential Circuits
Cost-Effective Non-Scan Design for Testability for Actual Testability Improvement / D. Xiang ; Y. Xu
Power 4 Microprocessor / Session 3.3 Invited Session:
Power4 Microprocessor and System Design / J. Clabes
Power4 Design Methodology / B. Zoric
Semi-Custom Design Methodology for Power4 / P. Strenski
Power4 Integration / M. Scheuermann
Boolean Reasoning for Applications in CAD / A. KuehlmannSession 4.1:
Computer Arithmetic / Session 4.2:
Improved ZDN-Arithmetic for Fast Modulo Multiplication / H. Ploog ; S. Flugel ; D. Timmermann
Design Alternatives for Parallel Saturating Multioperand Adders / P. I. Balzola ; M. J. Schulte ; J. Ruan ; J. Glossner ; E. Hokenek
A Single-Multiplier Quadratic Interpolator for LNS Arithmetic / M. G. Arnold ; M. D. Winkel
Circuit Sizing and Optimization / Session 4.3:
Gate Sizing to Eliminate Crosstalk Induced Timing Violation / T. Xiao ; M. Marek-Sadowska
Performance Optimization by Wire and Buffer Sizing under the Transmission Line Model / T.-C. Chen ; S.-R. Pan ; Y.-W. Chang
Buffered Interconnect Tree Optimization using Lagrangian Relaxation and Dynamic Programming / S.-Y. Lai ; R. Baldick
Clocking and Time-Domain Measurements / Session 5.1:
Embedded Tutorial: Clocked Timing Elements for High-Performance and Low-Power VLSI Systems / V. Oklobdzija
Jitter-Induced Power/Ground Noise in CMOS PLLs: A Design Perspective
On the Micro-Architectural Impact of Clock Distribution Using Multiple PLLs / M. Saint-Laurent ; M. Swaminathan ; J. D. Meindl
On-Chip Oscilloscopes for Noninvasive Time-Domain Measurement of Waveforms / K. L. Shepard ; Y. Zheng
Processor Microarchitecture / Session 5.2:
Selective Branch Prediction Reversal by Correlating with Data Values and Control Flow / J. L. Aragon ; J. Gonzalez ; J. M. Garcia ; A. Gonzalez
Mutable Functional Units and Their Applications on Microprocessors / Y. Solihin ; K. W. Cameron ; Y. Luo ; D. Lavenier ; M. Gokhale
Compiler-Directed Classification of Value Locality Behavior / Q. Zhao ; D. J. Lilja
A Hierarchical Dependence Check and Folded Rename Mapping Based Scalable Dispatch Stage / V. Sankaranarayanan ; A. Tyagi
Invited Session: Taming Tons of Gigabytes: Innovations in Disk Drive Electronics / Session 5.3:
Designing Circuits for Disk Drives / G. Pelz
Hard Disk Controller: The Disk Drive's Brain and Body / J. Jeppensen ; W. Allen ; S. Anderson ; M. Pilsl
Motion-Control: The Power Side of Disk Drives / W. Sereinig
Energy Efficiency Caches and Multiport Cache Structures / Session 6.1:
Static Energy Reduction Techniques for Microprocessor Caches / H. Hanson ; M. S. Hrishikesh ; V. Agarwal ; S. W. Keckler
Parallel Cachelets / D. Limaye ; R. Rakvic ; J. P. Shen
Access Region Cache: A Multi-Porting Solution for Future Wide-Issue Processors / B. S. Thakar ; G. Lee
Control by Simulation and On-line Checking / Session 6.2:
Distributed Event-Driven Simulation of VHDL-SPICE Mixed-Signal Circuits / D. Lungeanu ; C. J. R. Shi
High Performance Parallel Fault Simulation / A. K. Varshney ; B. Vinnakota ; E. Skuldt ; B. Keller
On-Line Integrity Monitoring of Microprocessor Control Logic / S. Kim ; A. K. Somani
CAD Algorithms for Physical Design / Session 6.3:
A Timing-Driven Macro-Cell Placement Algorithm / F. Mo ; A. Tabbara ; R. K. Brayton
Fixed-Outline Floorplanning through Better Local Search / S. N. Adya ; I. L. Markov
Generic ILP-Based Approaches for Dynamically Reconfigurable FPGA Partitioning / G.-M. Wu ; J.-M. Lin ; M. C.-T. Chao
Panel Discussion
How Much Longer Will SuperScalar Microarchitectures Scale? / D. Burger (chair) ; M. Hill ; M. Hopkins ; M. McDermott ; Y. Patt ; M. Snyder ; G. Sohi
Invited Session: Network Processors / Session 7.1:
Network Processing: Applications and Challenges / C. Narad
Payload+: Fast Pattern Matching and Routing for OC-48 / D. Kramer
Scaling Fully Programmable Network Processing to 10Gbps and Beyond / K. Morris
Formal Methods for Property Verification and Equivalence Verification / Session 7.2:
Arithmetic Transforms for Verifying Compositions of Sequential Datapaths / K. Radecka ; Z. Zilic
Hierarchical Image Computation with Dynamic Conjunction Scheduling / C. Meinel ; C. Stangier
Introduction to Generalized Symbolic Trajectory Evaluation / J. Yang ; C.-J. H. Seger
Hardware Representation / Session 7.3:
BDD Variable Ordering by Scatter Search / W. N. N. Hung ; X. Song
Lower Bound Based DDD Minimization for Efficient Symbolic Circuit Analysis / A. Manthe ; C-J. R. Shi
Run-Time Execution of Reconfigurable Hardware in a Java Environment / L. A. S. King ; H. Quinn ; M. Leeser ; D. Galatopoullos ; E. Manolakos
Circuit Techniques / Session 8.1:
Realization of Multiple-Output Functions by Reconfigurable Cascades / Y. Iguchi ; T. Sasao ; M. Matsuura
A Low-Power Cache Design for CalmRISC-Based Systems / S. Cho ; W. Jung ; Y. Kim
Interconnect-Centric Array Architectures for Minimum SRAM Access Time / A. J. Bhavnagarwala ; S. Kosonocky
Understanding and Addressing the Noise Induced by Electrostatic Discharge in Multiple Power Supply Systems / J. Lee ; Y. Huh ; P. Bendix ; S.-M. Kang
DSP/Multimedia / Session 8.2:
Cost-Effective Hardware Acceleration of Multimedia Applications / D. Talla ; L. K John
MPEG Macroblock Parsing and Pel Reconstruction on an FPGA-Augmented TriMedia Processor / M. Sima ; S. Cotofana ; S. Vassiliadis ; J. T. J. van Eijndhoven ; K. Vissers
Low-Energy DSP Code Generation Using a Genetic Algorithm / M. Lorenz ; R. Leupers ; P. Marwedel ; T. Drager ; G. Fettweis
Voltage Scaling for Energy Minimization with QoS Constraints / A. Manzak ; C. Chakrabarti
Novel Architectures and ISA Extensions / Session 8.3:
Matching Architecture to Application via Configurable Processors: A Case Study with Boolean Satisfiability Problem / Y. Zhao ; S. Malik ; A. Wang ; M. W. Moskewicz ; C. F. Madigan
Architectural Enhancements for Fast Subword Permutations with Repetitions in Cryptographic Applications / J. P. McGregor ; R. B. Lee
3DCGiRAM: An Intelligent Memory Architecture for Photo-Realistic Image Synthesis / H. Kobayashi ; K. Suzuki ; K. Sano ; Y. Kaeriyama ; Y. Saida ; N. Oba ; T. Nakamura
Use of Local Memory for Efficient Java Execution / S. Tomar
Poster Papers
An Analytical Model for Trace Cache Instruction Fetch Performance / A. Hossain ; D. J. Pease
Performance Driven Global Routing through Gradual Refinement / J. Hu ; S. S. Sapatnekar
Fuzzified Iterative Algorithms for Performance Driven Low Power VLSI Placement / S. M. Sait ; H. Youssef ; J. A. Khan ; A. El-Maleh
Fast Specification of Cycle-Accurate Processor Models / F. S.-H. Chang ; A. J. Hu
A Performance Analysis of the Active Memory System / W. Srisa-an ; C.-T. D. Lo ; J. M. Chang
Combined IEEE Compliant and Truncated Floating Point Multipliers for Reduced Power Dissipation / K. E. Wires ; J. E. Stine
An Algorithm for Dynamically Reconfigurable FPGA Placement
RC-In RC-Out Model Order Reduction Accurate up to Second Order Moments / P. Ganesh
Efficient Function Approximation for Embedded and ASIC Applications / J. W. Hauser ; C. N. Purdy
An Area-Efficient Iterative Modified-Booth Multiplier Based on Self-Timed Clocking / M.-C. Shin ; S.-H. Kang ; I.-C. Park
A Heuristic for Multiple Weight Set Generation / H.-S. Kim ; S. Kang
Towards a Formal Model of Shared Memory Consistency for Intel Itanium / P. Chatterjee ; G. Gopalakrishnan
Efficient Algorithms for Subcircuit Enumeration and Classification for the Module Identification Problem / J. L. White ; M.-J. Chung ; A. S. Wojcik ; T. E. Doom
MCOMA: A Multithreaded COMA Architecture / H. El Naga ; J.-L. Gaudiot
Automatic Generation and Validation of Memory Test Models for High Performance Microprocessors / K. Zarrineh ; T. A. Ziaja ; A. Majumdar
Reducing Cache Pollution of Prefetching in a Small Data Cache / P. Reungsang ; S. K. Park ; H.-L. Roh
Alloyed Path-Pattern Scheme for Branch Prediction / R. Ramanujam ; M. Ravirala
Timing Characterization of Dual-Edge Triggered Flip-Flops / N. Nedovic ; M. Aleksic ; V. G. Oklobdzija
Performance Impact of Addressing Modes on Encryption Algorithms / A. M. Fiskiran
Determining Schedules for Reducing Power Consumption Using Multiple Supply Voltages / N. Chabini ; E. M. Aboulhamid ; Y. Savaria
Pre-Routing Estimation of Shielding for RLC Signal Integrity / J. D. Z. Ma ; A. Parihar ; L. He
Author Index
Welcome to ICCD
Organizing Committee
Program Committee
2.

図書

図書
sponsored by IEEE Computer Society, IEEE Circuits and Systems Society ; in cooperation with IEEE Electron Devices Society
出版情報: Los Alamitos, Calif. : IEEE Computer Society, c2004  xviii, 578 p. ; 28 cm
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Welcome Letter
Organizing Committee
Program Committee
Additional Reviewers
Keynote Addresses
Gigascale System Design--Challenges and Opportunities / S. Borkar
Error Tolerance / M. Breuer
Digital Integrated Circuit Testing for Art Historians and Test Experts / E. McCluskey
High-Speed and Energy-Efficient Circuit Design / Session 1:
PCAM: A Ternary CAM Optimized for Longest Prefix Matching Tasks / M. Akhbarizadeh ; M. Nourani ; D. Vijayasarathi ; P. Balsara
Area and Energy-Efficient Crosstalk Avoidance Codes for On-Chip Buses / S. Sridhara ; A. Ahmed ; N. Shanbhag
An Area- and Energy-Efficient Asynchronous Booth Multiplier for Mobile Devices / J. Hensley ; A. Lastra ; M. Singh
A High-Frequency Decimal Multiplier / R. Kenney ; M. Schulte ; M. Erle
An Efficient Twin-Precision Multiplier / M. Sjalander ; H. Eriksson ; P. Larsson-Edefors
Energy-Efficient Processor Microarchitecture (1) / Session 1.2:
Defining Wakeup Width for Efficient Dynamic Scheduling / A. Aggarwal ; M. Franklin ; O. Ergin
Power-Aware Deterministic Block Allocation for Low-Power Way-Selective Cache Structure / J.-W. Park ; G.-H. Park ; S.-B. Park ; S.-D. Kim
Thermal-Aware Clustered Microarchitectures / P. Chaparro ; J. Gonzalez ; A. Gonzalez
Reducing Issue Queue Power for Multimedia Applications Using a Feedback Control Algorithm / Y. Bai ; R. Bahar
Scan Design and Test / Session 1.3:
A Novel Low-Power Scan Design Technique Using Supply Gating / S. Bhunia ; H. Mahmoodi ; S. Mukhopadhyay ; D. Ghosh ; K. Roy
Asynchronous Scan-Latch Controller for Low Area Overhead DFT / M. Tsukisaka ; M. Imai ; T. Nanya
End-to-End Testability Analysis and DfT Insertion for Mixed-Signal Paths / S. Ozev ; A. Orailoglu
Functional Illinois Scan Design at RTL / H. Ko ; N. Nicolici
On Undetectable Faults in Partial Scan Circuits Using Transparent-Scan / I. Pomeranz ; S. Reddy
Routing and Floorplanning / Session 2:
A Depth-First-Search Controlled Gridless Incremental Routing Algorithm for VLSI Circuits / H. Arslan ; S. Dutt
Simultaneous Shield and Buffer Insertion for Crosstalk Noise Reduction in Global Routing / T. Zhang ; S. Sapatnekar
A Two-Layer Bus Routing Algorithm for High-Speed Boards / M. Ozdal ; M. Wong
Reticle Floorplanning with Guaranteed Yield for Multi-Project Wafers / A. Kahng ; S. Reda
Formal Verification Embedded Tutorial / Session 2.2:
Fine-Grain Abstraction and Sequential Don't Cares for Large Scale Model Checking / C. Wang ; G. Hachtel ; F. Somenzi
Comparative Study of Strategies for Formal Verification of High-Level Processors / M. Velev
Signal Integrity and Leakage / Session 2.3:
A Highly-Efficient Technique for Reducing Soft Errors in Static CMOS Circuits / S. Krishnamohan ; N. Mahapatra
A Signal Integrity Test Bed for PCB Buses / J. Ren ; M. Greenstreet
A New Threshold Voltage Assignment Scheme for Runtime Leakage Reduction in On-Chip Repeaters / S. Shah ; K. Agarwal ; D. Sylvester
A General Post-Processing Approach to Leakage Current Reduction in SRAM-Based FPGAs / J. Lach ; J. Brandon ; K. Skadron
Special Session on High-Performance On-Chip Communication / Session 3:
Design Methodologies and Architecture Solutions for High-Performance Interconnects (Invited Paper) / D. Pandini ; C. Forzan ; L. Baldi
On-Chip Transparent Wire Pipelining (Invited Paper) / M. Casu ; L. Macchiarulo
Toward an Integrated Design Methodology for Fault-Tolerant, Multiple Clock/Voltage Integrated Systems (Invited Paper) / R. Marculescu ; D. Marculescu ; L. Pileggi
Network-on-Chip: The Intelligence is in the Wire (Invited Paper) / G. Mas ; P. Martin
Test Generation and Characterization / Session 3.2:
Low Power Test Data Compression Based on LFSR Reseeding / J. Lee ; N. Touba
An Infrastructure IP for On-Chip Clock Jitter Measurement / J.-J. Huang ; J.-L. Huang
Diagnosis of Hold Time Defects / Z. Wang ; M. Marek-Sadowska ; K.-H. Tsai ; J. Rajski
Extending the Applicability of Parallel-Serial Scan Designs / B. Arslan ; O. Sinanoglu
Quality Improvement Methods for System-Level Stimuli Generation / R. Emek ; I. Jaeger ; Y. Katz ; Y. Naveh
Physically-Aware Design Tools / Session 3.3:
XTalkDelay: A Crosstalk-Aware Timing Analysis Tool for Chip-Level Designs / Y. Li ; R. Murgai ; T. Miyoshi ; A. Verma
A Flexible Data Structure for Efficient Buffer Insertion / R. Chen ; H. Zhou
Simultaneous Scheduling, Binding and Layer Assignment for Synthesis of Vertically Integrated 3D Systems / M. Mukherjee ; R. Vemuri
Transistor and Pin Reordering for Gate Oxide Leakage Reduction in Dual T[subscript ox] Circuits / A. Sultania
Energy-Efficient Processor Microarchitecture (2) / Session 4:
Best of Both Latency and Throughput / E. Grochowski ; R. Ronen ; J. Shen ; H. Wang
Fetch Halting on Critical Load Misses / N. Mehta ; B. Singer ; M. Leuchtenburg ; R. Weiss
Frontend Frequency-Voltage Adaptation for Optimal Energy-Delay[superscript 2] / G. Magklis
Power and Timing Optimization / Session 4.2:
Gate Sizing and V[subscript t] Assignment for Active-Mode Leakage Power Reduction / F. Gao ; J. Hayes
Potential Slack Budgeting with Clock Skew Optimization / K. Wang
A New Statistical Optimization Algorithm for Gate Sizing / M. Mani ; M. Orshansky
Novel Processor Design / Session 4.3:
An Architecture for Fast Processing of Large Unstructured Data Sets / R. Chamberlain ; M. Henrichs ; B. Shands ; J. White
In-System FPGA Prototyping of an Itanium Microarchitecture / R. Wunderlich ; J. Hoe
Adaptive Selection of an Index in a Texture Cache / C.-H. Kim ; L.-S. Kim
Emerging Technologies Special Session / Session 5:
Using Circuits and Systems-Level Research to Drive Nanotechnology (Invited Paper) / M. Niemier ; R. Ravichandran ; P. Kogge
FPGA Emulation of Quantum Circuits / A. Khalid ; Z. Zilic ; K. Radecka
3D Processing Technology and Its Impact on iA32 Microprocessors (Invited Paper) / B. Black ; D. Nelson ; C. Webb ; N. Samra
Cache Memory Design / Session 5.2:
Cache Array Architecture Optimization at Deep Submicron Technologies / A. Zeng ; K. Rose ; R. Gutmann
Implementation of Fine-Grained Cache Monitoring for Improved SMT Scheduling / J. Kihm ; D. Connors
Low Energy, Highly-Associative Cache Design for Embedded Processors / A. Veidenbaum ; D. Nicolaescu
Layout-Driven Circuit Optimization / Session 6:
The Magic of a Via-Configurable Regular Fabric / Y. Ran
A Fast Delay Analysis Algorithm for the Hybrid Structured Clock Network / Y. Zou ; Y. Cai ; Q. Zhou ; X. Hong ; S. Tan
Layout Driven Optimization of Datapath Circuits Using Arithmetic Reasoning / I. Neumann ; D. Stoffel ; K. Sulimma ; M. Berkelaar ; W. Kunz
Floorplan-Aware Low-Complexity Digital Filter Synthesis for Low-Power and High-Speed / D. Kang ; H. Choo
Instruction-Level Parallelism (1) / Session 6.2:
A Minimal Dual-Core Speculative Multi-Threading Architecture / S. Srinivasan ; H. Akkary ; T. Holman ; K. Lai
Exploiting Quiescent States in Register Lifetime / R. Sangireddy ; A. Somani
Evaluating Techniques for Exploiting Instruction Slack / Y. Chin ; J. Sheu ; D. Brooks
Power Estimation and Minimization / Session 6.3:
Static Transition Probability Analysis under Uncertainty / S. Garg ; S. Tata ; R. Arunachalam
Circuit-Based Preprocessing of ILP and Its Applications in Leakage Minimization and Power Estimation / D. Chai ; A. Kuehlmann
Analyzing Power Consumption of Message Passing Primitives in a Single-Chip Multiprocessor / M. Loghi ; L. Benini ; M. Poncino
An Architectural Power Estimator for Analog-to-Digital Converters / Z. Huang ; P. Zhong
Formal Verification Techniques / Session 7:
Formal Hardware Verification Based on Signal Correlation Properties--A PVS Library for Redundant Number Representation / N. Kikkeri ; P.-M. Seidel
Generating Monitor Circuits for Simulation-Friendly GSTE Assertion Graphs / K. Ng ; A. Hu ; J. Yang
Graph Automorphism-Based Algorithm for Determining Symmetric Inputs / C.-L. Chou ; C.-Y. Wang ; G.-W. Lee ; J.-Y. Jou
Networks on Chips / Session 7.2:
Linear Programming Based Techniques for Synthesis of Network-on-Chip Architectures / K. Srinivasan ; K. Chatha ; G. Konjevod
Thermal-Aware IP Virtualization and Placement for Networks-on-Chip Architecture / W. Hung ; C. Addo-Quaye ; T. Theocharides ; Y. Xie ; N. Vijaykrishnan ; M. Irwin
Many-to-Many Core-Switch Mapping in 2-D Mesh NoC Architectures / C.-E. Rhee ; H.-Y. Jeong ; S. Ha
Novel Processor Architecture / Session 7.3:
An Embedded Reconfigurable SIMD DSP with Capability of Dimension-Controllable Vector Processing / L. Han ; J. Chen ; C. Zhou ; X. Zhang ; Z. Liu ; X. Wei ; B. Li
Runtime Execution Monitoring (REM) to Detect and Prevent Malicious Code Execution / A. Fiskiran ; R. Lee
Dynamic Address Compression Schemes: A Performance, Energy, and Cost Study / J. Liu ; K. Sundaresan
Instruction-Level Parallelism (2) / Session 8:
Compiler-Based Frame Formation for Static Optimization / F. Shi ; S. Almukhaizam ; P.-C. Lin ; Y. Makris
IPC Driven Dynamic Associative Cache Architecture for Low Energy / S. Nadathur ; A. Tyagi
Increasing Processor Performance through Early Register Release / D. Balkan ; D. Ponomarev ; K. Ghose
Topics in Synthesis and Co-Simulation / Session 8.2:
Combined Channel Segmentation and Buffer Insertion for Routability and Performance Improvement of Field Programmable Analog Arrays / H. Huang ; J. Bernstein ; M. Peckerar ; J. Luo
Software/Network Co-Simulation of Heterogeneous Industrial Networks Architectures / F. Fummi ; S. Martini ; M. Monguzzi ; G. Perbellini
Hardware/Software Co-Modeling of SAT Solver Based on Distributed Computing Elements Using SystemC / J. Xi
Coping with the Variability of Combinational Logic Delays / J. Cortadella ; A. Kondratyev ; L. Lavagno ; C. Sotiriou
Low-Power Architecture / Session 8.3:
Design-Space Exploration of Power-Aware On/Off Interconnection Networks / V. Soteriou ; L.-S. Peh
Energy Characterization of Hardware-Based Data Prefetching / Y. Guo ; S. Chheda ; I. Koren ; C. Krishna ; C. Moritz
Design and Implementation of Scalable Low-Power Montgomery Multiplier / H.-K. Son ; S.-G. Oh
Test Generation / Session 9:
Compressed Embedded Diagnosis of Logic Cores / S. Ollivierre ; A. Kinsman
An Automatic Test Pattern Generation Framework for Combinational Threshold Logic Networks / P. Gupta ; R. Zhang ; N. Jha
An Efficient Algorithm for Reconfiguring Shared Spare RRAM / H.-Y. Lin ; H.-Z. Chou ; F.-M. Yeh ; I.-Y. Chen ; S.-Y. Kuo
Network Routing / Session 9.2:
An Accurate Combinatorial Model for Performance Prediction of Deterministic Wormhole Routing in Torus Multicomputer Systems / H. Najaf-abadi ; H. Sarbazi-azad
Technique to Eliminate Sorting in IP Packet Forwarding Devices / R. Baldwin ; E. Ng
Placement and Floorplanning / Session 9.3:
I/O Clustering in Design Cost and Performance Optimization for Flip-Chip Design / H.-M. Chen ; I.-M. Liu ; M. Shao ; L.-D. Huang
Placement with Alignment and Performance Constraints Using the B*-Tree Representation / M.-C. Wu ; Y.-W. Chang
ACG-Adjacent Constraint Graph for General Floorplans / J. Wang
Author Index
Welcome Letter
Organizing Committee
Program Committee
3.

図書

図書
IEEE/ACM International Conference on Computer-Aided Design ; IEEE Circuits and Systems Society ; IEEE Computer Society ; Institute of Electrical and Electronics Engineers ; IEEE Electron Devices Society
出版情報: New York : Association for Computing Machinery, c1998  xxii, 704 p. ; 28 cm
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4.

図書

図書
sponsored by IEEE Computer Society, IEEE Circuits and Systems Society ; in cooperation with IEEE Electron Devices Society
出版情報: Los Alamitos, Calif. : IEEE Computer Society, c1999  xxv, 661 p. ; 28 cm
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Foreword
Organizing Committee
Technical Program Committee
Reviewers
System Design: Traditional Concepts and New Paradigms / A. Ferrari ; A. Sangiovanni-Vincentelli
The Marco/Darpa Gigascale Silicon Research Center / Kurt Keutzer ; A. Richard Newton
Embedded Tutorial
CAD Techniques for Embedded Systems-on-Silicon
Applied Verification Techniques
Verification of Real Time Controllers against Timing Diagram Specifications Using Constraint Logic Programming / E. Cerny ; F. Jin
Formal Verification of Synthesized Analog Designs / A. Ghosh ; R. Vemuri
Implicit Verification of Structurally Dissimilar Arithmetic Circuits / T. Stanion
Automatic Error Correction of Tri-State Circuits / D. Hoffmann ; T. Kropf
Computer Arithmetic
Design Methodology for a One-Shot Reed-Solomon Encoder and Decoder / S. Morioka ; Y. Katayama
High-Speed CORDIC Architecture Based on Redundant Sum Formation and Overlapped [sigma]-Selection / J. Choi ; J.-H. Kwak ; E. Swartzlander, Jr.
Multilevel Reverse-Carry Computation for Comparison and for Sign and Overflow Detection in Addition / T. Lang ; J. Bruguera
A Unified Method for Iterative Computation of Modular Multiplication and Reduction Operations / W. Freking ; K. Parhi
Evolution of DSP Architecture
Machines and Characterization
Designing the M - CORE M3 CPU Architecture / J. Scott ; L. Lee ; A. Chin ; J. Arends ; B. Moyer
Performance Evaluation of Configurable Hardware Features on the AMD-K5 / M. Clark ; L. John
Detailed Characterization of a Quad Pentium Pro Server Running TPC-D / Q. Cao ; P. Trancoso ; J.-L. Larriba-Pey ; J. Torrellas ; R. Knighten ; Y. Won
Power and Noise Considerations in Microprocessor Design
Simultaneous Switching Noise Considerations in the Design of a High Speed, Multiported TLB of a Server-Class Microprocessor / N. Kalyanasundharam ; N. Patwa
On the Use of Pseudorandom Sequences for High Speed Resource Allocators in Superscalar Processors / S. Srinivasan
Power Estimation of System-Level Buses for Microprocessor-Based Architectures: A Case Study / W. Fornaciari ; D. Sciuto ; C. Silvano
Architectures for Embedded Systems
A DSP with Caches -- A Study of the GSM-EFR Codec on the TI C6211 / T. Jeremiassen
Evaluation of Computing in Memory Architectures for Digital Image Processing Applications / D. Landis ; P. Hulina ; S. Deno ; L. Roth ; L. Coraor
Customization of a CISC Processor Core for Low-Power Applications / Y.-S. Chang ; B.-I. Park ; I.-C. Park ; C.-M. Kyung
Built-In Self Test
A New Weight Set Generation Algorithm for Weighted Random Pattern Generation / H. Lee ; S. Kang
Multiple Paths Sensitization of Digital Oscillation Built-In Self Test / C. Dufaza
Design and Implementation of a Parallel Weighted Random Pattern and Logic Built in Self Test Algorithm / P. Chang ; B. Keller ; S. Paliwal
Intelligent Memory
Design and Evaluation of a Selective Compressed Memory System / J.-S. Lee ; W.-K. Hong ; S.-D. Kim
FlexRAM: Toward an Advanced Intelligent Memory System / Y. Kang ; W. Huang ; S.-M. Yoo ; D. Keen ; Z. Ge ; V. Lam ; P. Pattnaik
ActiveOS: Virtualizing Intelligent Memory / M. Oskin ; F. Chong ; T. Sherwood
Performance and Area Optimization
An Efficient Buffer Insertion Algorithm for Large Networks Based on Lagrangian Relaxation / I.-M. Liu ; A. Aziz ; D. Wong ; H. Zhou
An Exact Tree-Based Structural Technology Mapping Algorithm for Configurable Logic Blocks in FPGAs / K. Lee
An Effective Algorithm for Gate-Level Power-Delay Tradeoff Using Two Voltages / C. Chen ; M. Sarrafzadeh
VLSI Implementation of Arithmetic Circuits
Switching Characteristics of Generalized Array Multiplier Architectures and Their Applications to Low Power Design / K. Muhammad ; D. Somasekhar ; K. Roy
Low-Power Radix-4 Combined Division and Square Root / A. Nannarelli
A Regular Layout Structured Multiplier Based on Weighted Carry-Save Adders
Design Convergence
A Robust Solution to the Timing Convergence Problem in High-Performance Design / N. Shenoy ; M. Iyer ; R. Damiano ; P. Thilking ; K. Harer ; H.-K. Ma
Performance Driven Optimization of Network Length in Physical Placement / W. Donath ; P. Kudva ; L. Reddy
Efficient Crosstalk Estimation / M. Kuhlmann ; S. Sapatnekar
Poster Presentations
A High-Performance Hardware-Efficient Memory Allocation Technique and Design / H. Cam ; M. Abd-El-Barr ; S. Sait
Improving Microcontroller Power Consumption through a Segmented Gray Code Program Counter / R. Hakenes ; Y. Manoli
A Superscalar RISC Processor with 160 FPRs for Large Scale Scientific Processing / K. Shimada ; T. Kawashimo ; M. Hanawa ; R. Yamagata ; E. Kamada
Characterization of Java Applications at Bytecode and Ultra-SPARC Machine Code Levels / R. Radhakrishnan ; J. Rubio
Automatic Generation of Tree Multipliers Using Placement-Driven Netlists / A. Gautam ; V. Visvanathan ; S. Nandy
Yield Optimization by Design Centering and Worst-Case Distance Analysis / G. Samudra ; H. Chen ; D. Chan ; Y. Ibrahim
Area, Performance, and Yield Implications of Redundancy in On-Chip Caches / T. Thomas ; B. Anthony
Conceptual Modeling and Simulation / W. Cyre
System-on-a-Chip Bus Architecture for Embedded Applications / P. Aldworth
CalmRISC: A Low Power Microcontroller with Efficient Coprocessor Interface / K.-M. Lim ; S.-W. Jeong ; Y.-C. Kim ; S.-J. Jeong ; H.-K. Kim ; Y.-H. Kim ; B.-Y. Chung ; H.-L. Roh ; H. Yang
An Even Wiring Approach to the Ball Grid Array Package Routing / S.-S. Chen ; J.-J. Chen ; C.-C. Tsai ; S.-J. Chen
Synthesis of Pseudo Kronecker Lattice Diagrams / P. Lindgren ; R. Drechsler ; B. Becker
Generic Universal Switch Blocks / M. Shyu ; Y.-D. Chang ; G.-M. Wu ; Y.-W. Chang
Multi-Level Logic Minimization through Fault Dictionary Analysis / R. Mehler ; M. Mercer
A Fast and Exact Cell Matching Method for MUX-Based FPGA Technology Mapping / K. Yi ; S. Ohm
Novel Formulations for Low-Power Binding of Function Units in High-Level Synthesis / A. Kumar ; M. Bayoumi
An Efficient Functional Coverage Test for HDL Descriptions at RTL / C.-N. Liu ; J.-Y. Jou
An Efficient Interconnect Test Using BIST Module in a Boundary-Scan Environment / H.-J. Kim ; J. Shin
On-Line BIST for Testing Analog Circuits / J. Velasco-Medina ; I. Rayane ; M. Nicolaidis
Iteration-Free Timing Closure
MicroProcessor Architecture; Trends and Directions / Uri Weiser
System Level Issues
A Design Methodology for a Fully Synthesized High Speed DSP Core in a Deep Sub-Micron Technology / J. Rao ; K. Madathil ; V. Shah ; H. Udayakumar ; A. Menon ; S. Chandar
An Environment for Exploring Low Power Memory Configurations in System Level Design / S. Coumeri ; D. Thomas
Architectural Synthesis of Timed Asynchronous Systems / B. Bachman ; H. Zheng ; C. Myers
Computing Minimum Feedback Vertex Sets by Contraction Operations and Its Applications on CAD / H.-M. Lin
Compilers and Algorithms
A Compiler-Assisted Data Prefetch Controller / S. Vander Wiel ; D. Lilja
Energy and Performance Improvements in Microprocessor Design Using a Loop Cache / N. Bellas ; I. Hajj ; C. Polychronopoulos ; G. Stamoulis
A Fast Median Filter Using AltiVec / P. Kolte ; R. Smith ; W. Su
Approximating Hexagonal Steiner Minimal Trees by Fast Optimal Layout of Minimum Spanning Trees / G.-H. Lin ; G. Xue ; D. Zhou
Test Generation and Delay Testing
On Detecting Bridges Causing Timing Failures / S. Mandava ; S. Chakravarty ; S. Kundu
Design for Testability to Combat Delay Faults / J. Savir
Fault Simulation Based Test Generation for Combinational Circuits Using Dynamically Selected Subcircuits / I. Pomeranz ; S. Reddy
Using an Embedded Processor for Efficient Deterministic Testing of Systems-on-a-Chip / A. Jas ; N. Touba
Microarchitecture
Architecture of the Atlas Chip-Multiprocessor: Dynamically Parallelizing Irregular Applications / L. Codrescu ; D. Wills
Load-Balancing Branch Target Cache and Prefetch Buffer / C.-H. Chi ; J.-L. Yuan
Dynamic Branch Decoupled Architecture / A. Tyagi ; H.-C. Ng ; P. Mohapatra
Efficient State-Space Exploration
Improving Witness Search Using Orders on States / R. Sumners ; J. Bhadra ; J. Abraham
Verification of Scheduling in the Presence of Loops Using Uninterpreted Symbolic Simulation / P. Ashar ; A. Raghunathan ; A. Gupta ; S. Bhattacharya
Efficient Fixpoint Computation for Invariant Checking / K. Ravi ; F. Somenzi
Clocking and Analog Circuit Prototyping
A Low-Power Microcontroller with On-Chip Self-Tuning Digital Clock-Generator for Variable-Load Applications / M. Olivieri ; A. Trifiletti ; A. De Gloria
A Methodology for Rapid Prototyping of Analog Systems / S. Ganesan
Transmission Line Clock Driver / M. Becker ; T. Knight, Jr.
Benchmarking, Selection and Debugging of Microcontrollers
Digital Signal Processors
The Specialization of General Purpose Processor Architecture Elements for Programmable Digital Signal Processors / D. Steiss
DSP for the Third Generation Wireless Communications / U. Ko ; M. McMahan ; E. Auslander
Performance and Reliability Verification of C6201/C6701 Digital Signal Processors / N. NS ; F. Cano ; S. Thiruvengadam ; D. Kapoor
Caching Approaches
Pursuing the Performance Potential of Dynamic Cache Line Sizes / P. van Vleet ; E. Anderson ; L. Brown ; J.-L. Baer ; A. Karlin
The Non-Critical Buffer: Using Load Latency Tolerance to Improve Data Cache Efficiency / B. Fisk ; R. Bahar
Cache Optimization for Memory-Resident Decision Support Commercial Workloads
CMOS Circuit Design Techniques
An Investigation of Power Delay Trade-Offs for Dual V[subscript t] CMOS Circuits / Q. Wang ; S. Vrudhula
Delay Optimization of CMOS Logic Circuits Using Closed-Form Expressions / M. Shams ; M. Elmasry
Design and Synthesis of Monotonic Circuits / T. Thorp ; G. Yee ; C. Sechen
SOI Implementation of a 64-Bit Adder / J. Tran ; F. Mounes-Toussi ; S. Storino ; D. Stasiak
Forty Five Years of Computer Architecture -- All That's Old is New Again / Harvey G. Cragon
The TriMedia CPU64 VLIW Media Processor
TriMedia CPU64 Application Domain and Benchmark Suite / A. Riemens ; K. Vissers ; R. Schutten ; F. Sijstermans ; G. Hekstra ; G. La Hei
TriMedia CPU64 Architecture / J. van Eijndhoven ; E. Pol ; M. Tromp ; P. Struik ; R. Bloks ; P. van der Wolf ; A. Pimentel ; H. Vranken
TriMedia CPU64 Application Development Environment / B. Aarts ; J. van de Waerdt
TriMedia CPU64 Design Space Exploration / P. Bingley
Logic Synthesis
On State Assignment of Finite State Machines Using Hypercube Embedding Approach / I. Ahmad ; R. Ul-Mustafa
Synthesis of Arrays and Records / P. Jha ; S. Barnfield ; J. Weaver ; R. Mukherjee ; R. Bergamaschi
Decomposition of Finite State Machines for Area, Delay Minimization / R. Shelar ; M. Desai ; H. Narayanan
BDD Decomposition for Efficient Logic Synthesis / C. Yang ; V. Singhal ; M. Ciesielski
Hardware Software Partitioning and Synthesis
Software Synthesis for Complex Reactive Embedded Systems / F. Balarin ; M. Chiodo
Hardware/Software Partitioning of Multirate System Using Static Scheduling Theory / R. Kamdem ; A. Fonkoua ; A. Zenatti
Compositional Software Synthesis of Communicating Processes / X. Zhu ; B. Lin
Preference-Driven Hierarchical Hardware/Software Partitioning / G. Quan ; X. Hu ; G. Greenwood
Author Index
Foreword
Organizing Committee
Technical Program Committee
5.

図書

図書
sponsored by IEEE Computer Society, IEEE Circuits and Systems Society, in cooperation with IEEE Electron Devices Society
出版情報: New York, NY : Institute of Electrical and Electronics Engineers, c1983  xii, 259 p. ; 28 cm
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図書

図書
sponsored by IEEE Computer Society, IEEE Circuits and Systems Society ; in cooperation with IEEE Electron Devices Society
出版情報: Los Alamitos, Calif. : IEEE Computer Society, c2000  xvii, 611 p. ; 28 cm
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目次情報: 続きを見る
Chairs' Message
Conference Organizers
Program Committee
Additional Reviewers
Keynote Address
On the Road to a Mobile Information Society / Dirk Friebel
New Architectures / Mauricio BreternitzSession 1.1:
Architectural Impact of Secure Socket Layer on Internet Servers / K. Kant ; R. Iyer ; P. Mohapatra
Fast Subword Permutation Instructions Using Omega and Flip Network Stages / X. Yang ; R. Lee
Sleipnir--An Instruction-Level Simulator Generator / T. Jeremiassen
Fault-Simulation and ATPG at Different Design Levels / Nur ToubaSession 1.2:
Analog Transient Concurrent Fault Simulation with Dynamic Fault Grouping / J. Hou ; A. Chatterjee
Pseudoexhaustive TPG with a Provably Low Number of LFSR Seeds / D. Kagaris ; S. Tragoudas
An Application of Genetic Algorithms and BDDs to Functional Testing / F. Ferrandi ; A. Fin ; F. Fummi ; D. Sciuto
Advanced Design Techniques / Ken ShepardSession 1.3:
High-Performance, Low-Power Skewed Static Logic in Very Deep-Submicron (VDSM) Technology / C. Kim ; J. Lee ; K.-H. Baek ; E. Martina ; S.-M. Kang
Estimation of Inductive and Resistive Switching Noise on Power Supply Network in Deep Sub-micron CMOS Circuits / S. Zhao ; K. Roy ; C.-K. Koh
Self-Calibrating Clocks for Globally Asynchronous Locally Synchronous Systems / S. Moore ; G. Taylor ; P. Cunningham ; R. Mullins ; P. Robinson
Improving CPU Performance / Brian GraysonSession 2.1:
Hybridizing and Coalescing Load Value Predictors / M. Burtscher ; B. Zorn
A 2-Way Thrashing-Avoidance Cache (TAC): An Efficient Instruction Cache Scheme for Object-Oriented Languages / Y. Chu ; M. Ito
Architectural Support for Dynamic Memory Management / J. Chang ; W. Srisa-an ; C.-T. Lo
SCIMA: Software Controlled Integrated Memory Architecture for High Performance Computing / M. Kondo ; H. Okawara ; H. Nakamura ; T. Boku
Parasitic Modeling, Analysis, and Optimization / Tom DillingerSession 2.2:
Worst Delay Estimation in Crosstalk Aware Static Timing Analysis / T. Xiao ; M. Marek-Sadowska
Analysis and Optimization of Ground Bounce in Digital CMOS Circuits / P. Heydari ; M. Pedram
An Efficient and Accurate Model for RF/Microwave Spiral Inductors Using Microstrip Lines Theory / N. Masoumi ; S. Safavi-Naeini ; M. Elmasry
Comparative Study of Parallel Algorithms for 3-D Capacitance Extraction on Distributed Memory Multiprocessors / Y. Yuan ; P. Banerjee
Low Power and Arithmetic / Margarida JacomeSession 2.3:
A Novel Low-Power Microprocessor Architecture / R. Hakenes ; Y. Manoli
A Power Perspective of Value Speculation for Superscalar Microprocessors / R. Moreno ; L. Pinuel ; S. del Pino ; F. Tirado
Multilevel Reverse-Carry Adder / J. Bruguera ; T. Lang
Evaluating Signal Processing and Multimedia Applications on SIMD, VLIW and Superscalar Architectures / D. Talla ; L. John ; V. Lapinskii ; B. Evans
Servers and Parallelism / Ruby LeeSession 3.1:
Unified Fine-Granularity Buffering of Index and Data: Approach and Implementation / Q. Cao ; J. Torrellas ; H. Jagadish
Analysis of Shared Memory Misses and Reference Patterns / J. Rothman ; A. Smith
Power-Sensitive Multithreaded Architecture / J. Seng ; D. Tullsen ; G. Cai
Circuit Optimization and Analysis / Shervin HojatSession 3.2:
Delay Constrained Optimization by Simultaneous Fanout Tree Construction, Buffer Insertion/Sizing and Gate Sizing / I-M. Liu ; A. Aziz
Application-Based, Transistor-Level Full-Chip Power Analysis for 700 MHz PowerPC Microprocessor / Y.-K. Cheng ; D. Bearden ; K. Suryadevara
Buffer Library Selection / C. Alpert ; R. Gandham ; J. Neves ; S. Quay
High-Performance Low-Power CMOS Circuits Using Multiple Channel Length and Multiple Oxide Thickness / N. Sirisantana ; L. Wei
Logic Circuit Families / Shyh-Jye JouSession 3.3:
Current-Mode Threshold Logic Gates / S. Bobba ; I. Hajj
Skewed CMOS: Noise-Immune High-Performance Low-Power Static Circuit Family / A. Solomatnikov ; D. Somasekhar
Output Prediction Logic: A High-Performance CMOS Design Technique / L. McMurchie ; S. Kio ; G. Yee ; T. Thorp ; C. Sechen
The Future of Populist Parallelism / Greg Pfister
Intelligent Memory / Steven ReinhardtSession 4.1:
A Study of Channeled DRAM Memory Architectures / L. Friebe ; Y. Yabe ; M. Motomura
DRAM-Page Based Prediction and Prefetching / H. Yu ; G. Kedem
Reducing Cost and Tolerating Defects in Page-Based Intelligent Memory / M. Oskin ; D. Keen ; J. Hensley ; L.-V. Lita ; F. Chong
Processor Microarchitecture / Steve FurberSession 4.2:
A Selective Temporal and Aggressive Spatial Cache System Based on Time Interval / J.-H. Lee ; J.-S. Lee ; S.-D. Kim
Design of Instruction Stream Buffer with Trace Support for X86 Processors / J.-C. Chiu ; I-H. Huang ; C.-P. Chung
A Trace Based Evaluation of Speculative Branch Decoupling / A. Nadkarni ; A. Tyagi
Digital Logic Techniques / Barbara ChappellSession 4.3:
An Adder Using Charge Sharing and Its Application in DRAMs / H.-S. Yu ; S. Lee ; J. Abraham
Fixed-Width Multiplier for DSP Application / S.-J. Jou ; H.-H. Wang
Dynamic Flip-Flop with Improved Power / N. Nedovic ; V. Oklobdzija
Embedded Processors: Architecture and System-Design Issues / Ricardo GonzalesSession 5.1:
Processors for Mobile Applications / F. Koushanfar ; V. Prabhu ; M. Potkonjak ; J. Rabaey
AMULET3: A 100 MIPS Asynchronous Embedded Processor / S. Furber ; D. Edwards ; J. Garside
Xtensa with User Defined DSP Coprocessor Microarchitectures / G. Ezer
Predictive Strategies for Low-Power RTOS Scheduling / P. Kumar ; M. Srivastava
Floorplanning and Partitioning / Tim BurksSession 5.2:
Rectilinear Block Placement Using B*-Trees / G.-M. Wu ; Y.-C. Chang ; Y.-W. Chang
Fast Hierarchical Floorplanning with Congestion and Timing Control / A. Ranjan ; K. Bazargan ; M. Sarrafzadeh
An Evaluation of Move-Based Multi-Way Partitioning Algorithms / E. Yarack ; J. Carletta
Assignment-Space Exploration Approach to Concurrent Data-Path/Floorplan Synthesis / K. Oohashi ; M. Kaneko ; S. Tayu
Basic Algorithms in Verification and Test / Yatin HoskoteSession 5.3:
On Solving Stack-Based Incremental Satisfiability Problems / J. Kim ; J. Whittemore ; K. Sakallah
Efficient Dynamic Minimization of World-Level DDs Based on Lower Bound Computation / W. Gunther ; R. Drechsler ; S. Horeth
Sensitivity Levels of Test Patterns and Their Usefulness in Simulation-Based Test Generation / I. Pomeranz ; S. Reddy
On Test Application Time and Defect Detection Capabilities of Test Sets for Scan Designs
Special Session: Advancements in DSP Architecture / Jim Bondi ; Nagaraj NSSession 6.1:
Effective Hardware-Based Two-Way Loop Cache for High Performance Low Power Processors / T. Anderson ; S. Agarwala
A Multi-Level Memory System Architecture for High-Performance DSP Applications / C. Fuoco ; D. Comisky ; C. Mobley
A Scalable High-Performance DMA Architecture for DSP Applications
Advanced Architectural Design and Synthesis / Edward GrochowskiSession 6.2:
Efficient Place and Route for Pipeline Reconfigurable Architectures / S. Cadambi ; S. Goldstein
PEAS-III: An ASIP Design Environment / M. Itoh ; S. Higaki ; J. Sato ; A. Shiomi ; Y. Takeuchi ; A. Kitajima ; M. Imai
Symbolic Binding for Clustered VLIW ASIPs / S. Pillai ; M. Jacome
Interfacing Hardware and Software Using C++ Class Libraries / D. Ramanathan ; R. Roth ; R. Gupta
Application and Case Studies in Test and Verification / Carl PixleySession 6.3:
Formal Verification of an Industrial System-on-a-Chip / H. Choi ; M.-K. Yim ; J.-Y. Lee ; B.-W. Yun ; Y.-T. Lee
Equivalence Checking Combining a Structural SAT-Solver, BDDs, and Simulation / V. Paruthi ; A. Kuehlmann
Efficient Design Error Correction of Digital Circuits / D. Hoffmann ; T. Kropf
An Automatic Validation Methodology for Logic BIST in High Performance VLSI Design / M. Cogswell ; D. Pearl ; J. Sage ; A. Troidl
Invited Paper
The Birth of the Baby / H. Kahn ; R. Napper
Logic Optimization / Chin-Long WeySession 7.1:
Efficient Logic Optimization Using Regularity Extraction / T. Kutzschebauch
Binary and Multi-Valued SPFD-Based Wire Removal in PLA Networks / S. Sinha ; S. Khatri ; R. Brayton ; A. Sangiovanni-Vincentelli
Minimization of Ordered Pseudo Kronecker Decision Diagrams / P. Lindgren ; B. Becker
High Level Specification and Synthesis / Pranav AsharSession 7.2:
Rethinking Behavioral Synthesis for a Better Integration within Existing Design Flows / W. Cesario ; A. Jerraya ; Z. Sugar ; I. Moussa
Synthesis and Optimization of Interface Hardware between IP's Operating at Different Clock Frequencies / B.-I. Park ; I.-C. Park ; C.-M. Kyung
Multi-Level Communication Synthesis of Heterogeneous Multilanguage Specification / F. Hessel ; P. Coste ; G. Nicolescu ; P. LeMarrec ; N. Zergainoh
Poster Sessions
Low Power Video Object Motion-Tracking Architecture for Very Low Bit Rate Online Video Applications / W. Badawy ; M. Bayoumi
An SEU Injection Tool to Evaluate DSP-Based Architectures for Space Applications / A. Benso ; S. Martinetto ; P. Prinetto ; R. Mariani
On Integrating a Proprietary and a Commercial Architecture for Optimal BIST Performances in SoCs / S. Di Carlo ; S. Chiusano ; F. Ricciato ; M. Bodoni ; M. Spadari
Static Timing Analysis with False Paths / H. Chen ; B. Lu ; D.-Z. Du
A Methodology and Tool for Automated Transformational High-Level Design Space Exploration / J. Gerlach ; W. Rosenstiel
Cheap Out-of-Order Execution Using Delayed Issue / J. Grossman
Representing and Scheduling Looping Behavior Symbolically / S. Haynal ; F. Brewer
Advanced Wiring RC Timing Design Techniques for Logic LSIs in Gigahertz Era and Beyond / Y. Ito ; S. Isomura ; T. Hiyama ; K. Nojiri
A Register File with Transposed Access Mode / Y. Jung ; S. Berg ; D. Kim ; Y. Kim
Leakage Power Analysis and Reduction during Behavioral Synthesis / K. Khouri ; N. Jha
An Advanced Instruction Folding Mechanism for a Stackless Java Processor / A. Kim ; M. Chang
OpenDesign: An Open User-Configurable Project Environment for Collaborative Design and Execution on the Internet / H. Lavana ; F. Brglez ; R. Reese ; G. Konduri ; A. Chandrakasan
A Decompression Architecture for Low Power Embedded Systems / H. Lekatsas ; J. Henkel ; W. Wolf
Optimal vs. Heuristic Approaches to Context Scheduling for Multi-Context Reconfigurable Architectures / R. Maestre ; F. Kurdahi ; M. Fernandez ; R. Hermida ; N. Bagherzadeh ; H. Singh
The M-CORE M340 Unified Cache Architecture / A. Malik ; B. Moyer ; D. Cermak
Crosstalk-Constrained Performance Optimization by Using Wire Sizing and Perturbation / S.-R. Pan
Hierarchical Simulation of a Multiprocessor Architecture / M. Pirvu ; L. Bhuyan ; R. Mahapatra
On Multiple Precision Based Montgomery Multiplication without Precomputation of N[subscript 0]' = -N[subscript 0 superscript -1] mod W / H. Ploog ; D. Timmerman
A Technique for Identifying RTL and Gate-Level Correspondences / S. Ravi ; I. Ghosh ; V. Boppana
A Direct Mapping FPGA Architecture for Industrial Process Control Applications / J. Welch
Source-Level Transformations for Improved Formal Verification / B. Winters ; A. Hu
Author Index
Chairs' Message
Conference Organizers
Program Committee
7.

図書

図書
sponsored by IEEE Computer Society, IEEE Circuits and Systems Society ; in cooperation with IEEE Electron Devices Society
出版情報: Los Angeles, Calif. : IEEE Computer Society, c1984  xii, 288 p. ; 28 cm
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8.

図書

図書
sponsored by IEEE Computer Society, IEEE Circuits and Systems Society ; in cooperation with IEEE Electron Devices Society
出版情報: Los Alamitos, Calif. : IEEE Computer Society, c2003  xxii, 563 p. ; 28 cm
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Welcome
Organizing Committee
Program Committee
Additional Reviewers
Keynotes
High-Speed Link Design, Then and Now / M. Horowitz
Terascale Computing and BlueGene / W. Pulley
Advanced EDA Tools for High-Performance Design / T. Vucurevich
Energy Efficiency / Session 1.1:
Energy Efficient Asymmetrically Ported Register Files / A. Aggarwal ; M. Franklin
Power Efficient Data Cache Designs / J. Abella ; A. Gonzalez
On Reducing Register Pressure and Energy in Multiple-Banked Register Files
Low Power Multiplication Algorithm for Switching Activity Reduction through Operand Decomposition / M. Ito ; D. Chinnery ; K. Keutzer
Timing Verification / Session 1.2:
Verification of Timed Circuits with Failure Directed Abstractions / H. Zheng ; C. Myers ; D. Walter ; S. Little ; T. Yoneda
Procedures for Identifying Untestable and Redundant Transition Faults in Synchronous Sequential Circuits / G. Chen ; S. Reddy ; I. Pomeranz
Event-Centric Simulation of Crosstalk Pulse Faults in Sequential Circuits / M. Phadoongsidhi ; K. Saluja
Specifying and Verifying Systems with Multiple Clocks / E. Clarke ; D. Kroening ; K. Yorav
Electrical Analysis for System LSI / Session 1.3:
Enhanced QMM-BEM Solver for 3-D Finite-Domain Capacitance Extraction with Multilayered Dielectrics / W. Yu ; Z. Wang ; X. Hong
An Improved Method for Fast Noise Estimation Based on Net Segmentation / C. Huang ; A. Dasgupta
Symbolic Failure Analysis of Custom Circuits due to Excessive Leakage Current / H. Song ; S. Bohidar ; I. Bahar ; J. Grodstein
An Efficient Algorithm for Calculating the Worst-case Delay due to Crosstalk / V. Rajappan ; S. Sapatnekar
Power Optimization / Session 2.1:
A Compact Model for Analysis and Design of On-chip Power Network with Decoupling Capacitors / P. Zarkesh-Ha ; K. Doniger ; W. Loh ; D. Sun ; R. Stephani ; G. Priebe
Precomputation-Based Guarding for Dynamic and Leakage Power Reduction / A. Abddollahi ; M. Pedram ; F. Fallah ; I. Ghosh
Charge-Recycling Voltage Domains for Energy-Efficient Low-Voltage Operation of Digital CMOS Circuits / S. Rajapandian ; Z. Xu ; K. Shepard
Low Power Adder with Adaptive Supply Voltage / H. Suzuki ; W. Jeong ; K. Roy
A Transparent Voltage Conversion Method and Its Application to a Dual-Supply-Voltage Register File / N. Tzartzanis ; W. Walker
Invited Session: Gene Chip Design / Session 2.2:
Detection of Biological Molecules: From Self-Assembled Films to Self-Integrated Devices / R. Levicky
Embedded Tutorial
Design Flow Enhancements for DNA Arrays / A. Kahng ; I. Mandoiu ; S. Reda ; X. Xu ; A. Zelikovsky
System Level Design / Session 2.3:
Bus Architecture Synthesis for Hardware-Software Co-Design of Deep Submicron Systems on Chip / N. Thepayasuwan ; V. Damle ; A. Doboli
Dynamically Optimized Synchronous Communication for Low Power System on Chip Designs / V. Chandra ; G. Carpenter ; J. Burns
Interface Synthesis Using Memory Mapping for an FPGA Platform / M. Luthra ; S. Gupta ; N. Dutt ; R. Gupta ; A. Nicolau
Efficient Synthesis of Networks On Chip / A. Pinto ; L. Carloni ; A. Sangiovanni-Vincentelli
Reducing Compilation Time Overhead in Compiled Simulators / M. Reshadi
Systems Performance / Session 3.1:
Profiling Interrupt Handler Performance through Kernel Instrumentation / B. Moore ; T. Slabach ; L. Schaelicke
Design and Performance of Compressed Interconnects for High Performance Servers / K. Kant ; R. Iyer
Routed Inter-ALU Networks for ILP Scalability and Performance / K. Sankaralingam ; V. Singh ; S. Keckler ; D. Burger
Micro Processor Test & Diagnosis / Session 3.2:
Automatic Generation of Critical-Path Tests for a Partial-Scan Microprocessor / D. Bhavsar ; V. Bettada ; R. Davies
Test Generation for Non-separable RTL Controller-datapath Circuits Using a Satisfiability Based Approach / L. Lingappan ; S. Ravi ; N. Jha
Cost-Effective Graceful Degradation in Speculative Processor Subsystems: The Branch Prediction Case / S. Almukhaizim ; T. Verdel ; Y. Makris
Multiple Fault Diagnosis Using n-Detection Tests / M. Marek-Sadowska ; K. Tsai ; J. Rajski
Physical Design / Session 3.3:
A Physical Design Methodology for 1.3GHz SPARC64 Microprocessor / N. Ito ; H. Komatsu ; Y. Tanamura ; R. Yamashita ; H. Sugiyama ; Y. Sugiyama ; H. Hamamura
Physical Design of the "2.5D" Stacked System / Y. Deng ; W. Maly
Flow-Based Cell Moving Algorithm for Desired Cell Distribution / B. Choi ; H. Xu ; M. Wang ; M. Sarrafzadeh
Performance Optimization / Session 4.1:
NpBench: A Benchmark Suite for Control plane and Data plane Applications for Network Processors / B. Lee ; L. John
Hardware-Only Compression of Underutilized Address Buses: Design and Performance, Power, and Cost Analysis / N. Mahapatra ; J. Liu ; K. Sundaresan
Pipelined Multiplicative Division with IEEE Rounding / G. Even ; P. Seidel
Clock & Signal Distribution / Session 4.2:
Design of Resonant Global Clock Distributions / S. Chan ; P. Restley
Modeling and Mitigation of Jitter in Multi-Gbps Source-Synchronous I/O Links / G. Balamurugan ; N. Shanbhag
A Mixed-Mode Delay-Locked Loop Architecture / D. Eckerbert ; L. Svensson ; P. Larsson-Edefors
Optimal Inductance for On-chip RLC Interconnections / S. Das ; K. Agarwal ; D. Blaauw ; D. Sylvester
Performance and Power-Driven Physical Design / Session 4.3:
Spec Based Flip-Flop and Buffer Insertion / N. Akkiraju ; M. Mohan
A Microeconomic Model for Simultaneous Gate Sizing and Voltage Scaling for Power Optimization / N. Ranganathan ; A. Murugavel
A Simple Yet Effective Merging Scheme for Prescribed-Skew Clock Routing / R. Chaturvedi ; J. Hu
Instruction Execution / Session 5.1:
Hardware-Based Pointer Data Prefetcher / S. Lai ; S. Lu
A Dependence Driven Efficient Dispatch Scheme / S. Nadathur ; A. Tyagi
An Efficient VLIW DSP Architecture for Baseband Processing / T. Lin ; C. Chang ; C. Lee ; C. Jen
Dynamic Thread Resizing for Speculative Multithreaded Processors / M. Zahran
Invited Session: Test Compression Technology / Session 5.2:
Care Bit Density and Test Cube Clusters: Multi-Level Compression Opportunities / B. Koenemann
XMAX: X-Tolerant Architecture for MAXimal Test Compression / S. Mitra ; K. Kim
Test Data Compression and Compaction for Embedded Test of Nanometer Technology Designs / J. Tyszer
Physical Design for Regular Fabrics and FPGA's / Session 5.3:
Non-Crossing OBDDs for Mapping to Regular Circuit Structures / A. Cao ; C. Koh
Interconnect Estimation for FPGAs under Timing Driven Domains / P. Kannan ; D. Bhatia
ROAD: An Order-Impervious Optimal Detailed Router for FPGAs / H. Arslan ; S. Dutt
Array Design Optimization / Session 6.1:
Reducing dTLB Energy through Dynamic Resizing / V. Delaluz ; M. Kandemir ; A. Sivasubramaniam ; M. Irwin ; N. Vijaykrishnan
Distributed Reorder Buffer Schemes for Low Power / G. Kucuk ; O. Ergin ; D. Ponomarev ; K. Ghose
Virtual Page Tag Reduction for Low-Power TLBs / P. Petrov ; A. Orailoglu
Dynamic Cluster Resizing / J. Gonzalez
Test Compaction / Session 6.2:
Independent Test Sequence Compaction through Integer Programming / P. Drineas
On Combining Pinpoint Test Set Relaxation and Run-Length Codes for Reducing Test Data Volume / S. Kajihara ; Y. Doi ; L. Li ; K. Chakrabarty
Static Test Compaction for Multiple Full-Scan Circuits
A Method to Find Don't Care Values in Test Sequences for Sequential Circuits / Y. Higami ; S. Kobayashi ; Y. Takamatsu
Invited Session: Techniques for Synthesizing into Fabrics / Session 6.3:
Simplifying SoC Design with the Customizable Control Processor Platform / C. Ogilvie ; R. Ray ; R. Devins ; M. Kautzman ; M. Hale ; R. Bergamaschi ; B. Lynch ; S. Gaur
Structured ASICs: Opportunities and Challenges / B. Zahiri
System LSI Implementation Fabrics for the Future / S. Kaptanoglu
Hardware Partitioning / Session 7.1:
Multiple-V[subscript dd] Scheduling/Allocation for Partitioned Floorplan / D. Kang ; M. Johnson
SCATOMi: Scheduling Driven Circuit Partitioning Algorithm for Multiple FPGAs Using Time-multiplexed, Off-chip, Multicasting Interconnection Architecture / Y. Kwon ; B. Park ; C. Kyung
A Study of Hardware Techniques that Dynamically Exploit Frequent Operands to Reduce Power Consumption in Integer Function Units / K. Gandhi
Energy-Aware Design and Application / Session 7.2:
KnapBind: An Area-Efficient Binding Algorithm for Low-leakage Datapaths / C. Gopalakrishnan ; S. Katkoori
A Novel Synthesis Strategy Driven by Partial Evaluation Based Circuit Reduction for Application Specific DSP Circuits / M. Mukherjee ; R. Vemuri
Power Fluctuation Minimization During Behavioral Synthesis Using ILP-Based Datapath Scheduling / S. Mohanty ; S. Chappidi
An Energy-Aware Simulation Model and Transaction Protocol for Dynamic Workload Distribution in Mobile Ad Hoc Networks / F. Ghasemi-Tari ; P. Rong
Invited Session: High-Speed Design Issues and Test Challenges / Session 7.3:
CMOS High-Speed Serial I/Os--Present and Future / M. Lee ; W. Dally ; R. Farjad-Rad ; H. Ng ; R. Senthinathan ; J. Edmondson ; J. Poulton
Fully Differential Receiver Chipset for 40 Gb/s Applications Using GaInAs/InP Single Heterojunction Bipolar Transistors / K. Kiziloglu ; S. Seetharaman ; K. Glass ; C. Bil ; H. Duong ; G. Asmanis
Paradigm Shift for Jitter and Noise in Design and Test [greater than sign]GB/s Data Communication Systems / M. Li ; J. Wilstrup
Efficiency and Reliability / Session 8.1:
Cost-Efficient Memory Architecture Design of NAND Flash Memory Embedded Systems / C. Park ; J. Seo ; D. Seo ; S. Kim ; B. Kim
Exploiting Microarchitectural Redundancy for Defect Tolerance / P. Shivakumar ; C. Moore
Reducing Multimedia Decode Power Using Feedback Control / Z. Lu ; J. Lach ; M. Stan ; K. Skadron
Novel Methods in Logic Synthesis / Session 8.2:
Structural Detection of Symmetries in Boolean Functions / G. Wang ; A. Kuehlmann
Boolean Decomposition Based on Cyclic Chains / E. Dubrova ; M. Teslenko ; J. Karlsson
SAT-Based Algorithms for Logic Minimization / S. Sapra ; M. Theobald
Communications and Context Management / Session 9.1:
Low-Density Parity-Check Decoder Architecture for High Throughput Optical Fiber Channels / A. Selvarathinam ; E. Kim ; G. Choi
Improving Branch Prediction Accuracy in Embedded Processors in the Presence of Coniext Switches / S. Pasricha ; A. Veidenbaum
Reducing Operand Transport Complexity of Superscalar Processors Using Distributed Register Files / S. Bunchua ; D. Wills ; L. Wills
xpipes: a Latency Insensitive Parameterized Network-on-chip Architecture for Multi-Processor SoCs / M. Dall'Osso ; G. Biccari ; L. Giovannini ; D. Bertozzi ; L. Benini
Board Test and Power-Aware Test / Session 9.2:
Aggressive Test Power Reduction through Test Stimuli Transformation / O. Sinanoglu
Power-Time Tradeoff in Test Scheduling for SoCs / M. Nourani ; J. Chin
Multiple Transition Model and Enhanced Boundary Scan Architecture to Test Interconnects for Signal Integrity / M. Tehranipour ; N. Ahmed
Author Index
Welcome
Organizing Committee
Program Committee
9.

図書

図書
sponsored by IEEE Computer Society, IEEE Circuits and Systems Society in cooperation with IEEE Electron Devices Society
出版情報: Los Alamitos : IEEE Computer Society Press, c1998  xix, 644 p. ; 28 cm
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10.

図書

図書
sponsored by IEEE Computer Society, IEEE Circuits and Systems Society in cooperation with IEEE Electron Devices Society
出版情報: Los Alamitos ; Tokyo : IEEE Computer Society Press, c1994  xvii, 639 p. ; 28 cm
所蔵情報: loading…
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