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1.

図書

図書
editors, Henrique Paques, Ling Liu, David Grossman ; sponsored by the Association for Computing Machinery, SIGIR and SIGMIS
出版情報: New York, N.Y. : ACM Order Department, c2001  xvii, 597 p. ; 28 cm
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2.

図書

図書
sponsored by ACM SIGMOBILE ; in cooperation with ACM SIGCOMM and SIGMETRICS and the IEEE Communication Society ; with support from Alcatel (Platinum Plus Suppoter) ...[et al.]
出版情報: New York, N.Y. : Association for Computing Machinery, c2001  356 p. ; 28 cm
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3.

コンピュータファイル

コンピュータファイル
Association for Computing Machinery
出版情報: New York : Association for Computing Machinery, c2001  1 CD-ROM ; 12 cm
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4.

図書

図書
sponsored by ACM, ACM SIGDA, Purdue University, Department of Electrical and Computer Engineering, Intel Corporation
出版情報: New York : Association for Computing Machinery, c2001  xii, 152 p. ; 28 cm
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5.

図書

図書
Bernard Mourrain, editor
出版情報: New York, N.Y. : ACM Press, c2001  xii, 352 p. ; 28 cm
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6.

図書

図書
ACM/IEEE-CS Joint Conference on Digital Libraries ; Association for Computing Machinery ; IEEE Computer Society
出版情報: New York, N.Y. : ACM, c2001  xviii, 490 p. ; 28 cm
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7.

図書

図書
[sponsored by VLSI Society of India (VSI), DOE, Government of India ; in cooperation with Association for Computing Machinery ...[et al.] ]
出版情報: Los Alamitos, Calif. : IEEE Computer Society, c2001  xxxvii, 541 p. ; 28 cm
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目次情報: 続きを見る
General Chair's Message
Message from the Program Chairs
Conference Committee
Steering Committee
VLSI Design 2000 Conference Awards
Reviewers
Conference History
Program Committee
Keynote Speakers
Tutorials
Optimization and Analysis Techniques for the Deep Submicron Regime / Noel Menezes ; Sachin Sapatnekar
Embedded Memories in System Design: Technology, Application, Design and Tools / Doris Keitel-Shulz ; Norbert When ; Francky Catthoor ; Preeti Ranjan Panda ; Nikil Dutt
Introduction to System C / Sudipta Bhawmik
Low-Power Mobile Wireless Communication System Design: Protocols, Architectures, and Design Methodologies / Anand Raghunathan ; Sujit Dey
IBM's Blue Logic Design Methodology-Circuits and Physical Design / Ruchira Kamdar ; Seetharam Gundurao ; R. V. Joshi ; N. S. Murty
Next Generation Network Processors / Deepak Kataria
Functional Verification of Programmable DSP Cores / Mahesh Mehendale ; Santhosh Kumar Amanna
System Level Testability Issues of Core Based System-on-a-Chip / V. Ranganathan ; R. Sundar
Tutorial: CMOS Analog Circuits for Wireless Communications / R. Harjani ; J. Harvey
Papers
Embedded Systems / Session 1A:
Integrating Communication Cost Estimation in Embedded Systems Design: A PCI Case Study / A. Rastogi ; M. Balakrishnan ; A. Kumar
Evaluation of the Traffic-Performance Characteristics of System-on-Chip Communication Architectures / K. Lahiri ; A. Raghunathan ; S. Dey
Performance Considerations in Embedded DSP Based System-on-a-Chip Designs / A. Gupte ; M. Mehendale ; R. Ramamritham ; D. Nair
Hardware Software Codesign of DSP System Using Grammar Based Approach / A. K. Deb ; A. Hemani ; J. Oberg ; A. Postula ; D. Lindqvist
A Systematic Approach for System Bus Load Reduction Applied to Medical Imaging / K. Danckaert ; C. Kulkarni ; F. Catthoor ; H. De Man ; V. Tiwari
Embedded Systems II / Session 1B:
Battery Life Estimation of Mobile Embedded Systems / D. Panigrahi ; C. Chiasserini ; R. Rao
Power-Aware Multimedia Systems Using Run-Time Prediction / P. Kumar ; M. Srivastava
Processor-Memory Co-Exploration Driven by a Memory-Aware Architecture Description Language / P. Mishra ; P. Grun ; N. Dutt ; A. Nicolau
ASIP Design Methodologies: Survey and Issues / M. K. Jain
SOC Methodologies / Session 1C:
ReDeEm_RTL: A Software Tool for Customizing Soft Cells for Embedded Applications / G. Surendra ; S. K. Nandy ; P. Sathya
The Hierarchical Concurrent Flow Graph Approach for Modeling and Analysis of Design Processes / V. Sahula ; C. P. Ravikumar
Satisfying Timing Constraints of Preemptive Real-Time Tasks through Task Layout Technique / A. Datta ; S. Choudhury ; A. Basu ; H. Tomiyama
Error Diagnosis of Sequential Circuits Using Region-Based Model / A. L. D'Souza ; M. S. Hsiao
Test / Session 2A:
On Improving Static Test Compaction for Sequential Circuits / R. Guo ; I. Pomeranz ; S. M. Reddy
On Fault-Simulation through Embedded Memories on Large Industrial Designs / S. Yadavalli ; S. Kundu
A Novel Strategy to Test Core Based Designs / D. Bagchi ; D. R. Chowdhury ; J. Mukherjee ; S. Chattopadhyay
Testable Design of Sequential Circuits with Improved Fault Efficiency / D. K. Das ; B. B. Bhattacharya ; S. Ohtake ; H. Fujiwara
Combination of Structural and State Analysis for Partial Scan / S. Sharma
Test II / Session 2B:
Combinational Test Generation for Acyclic Sequential Circuits Using a Balanced ATPG Model / Y. C. Kim ; V. D. Agrawal ; K. K. Saluja
Synthesis of System-on-a-Chip for Testability / S. Ravi ; N. K. Jha
Timing Verification and Delay Test Generation for Hierarchical Designs / A. Krishnamachary ; J. A. Abraham ; R. S. Tupuri
A Graph Traversal Based Framework for Sequential Logic Implication with an Application to C-Cycle Redundancy Identification / J.-K. Zhao ; J. A. Newquist ; J. H. Patel
Verification / Session 2C:
Implementation of Read-k-times BDDs on Top of Standard BDD Packages / W. Gunther ; R. Drechsler
Application of Esterel for Modelling and Verification of Cache Protocol on CRF Memory Model / S. R. Phanse ; R. K. Shyamasundar
Design Verification and Functional Testing of Finite State Machines / M. W. Weiss ; S. C. Seth ; S. K. Mehta ; K. L. Einspahr
Design of Provably Correct Storage Arrays / W. Hwang ; A. Kuehlmann
Low-Power / Session 3A:
Invited Paper: Low-Power Wireless Sensor Networks / R. Min ; M. Bhardwaj ; S.-W. Cho ; E. Shih ; A. Sinha ; A. Wang ; A. Chandrakasan
Sub-Domino Logic: Ultra-Low Power Dynamic Sub-Threshold Digital Logic / H. Soeleman ; K. Roy ; B. Paul
Average Power in Digital CMOS Circuits using Least Square Estimation / A. K. Murugavel ; N. Ranganathan ; R. Chandramouli ; S. Chavali
Dynamic Voltage Scheduling Using Adaptive Filtering of Workload Traces / A. P. Chandrakasan
Optimal Assignment of High Threshold Voltage for Synthesizing Dual Threshold CMOS Circuits / N. Tripathi ; A. Bhosle ; D. Samanta ; A. Pal
Low-Power II / Session 3B:
Accurate Power Macro-Modeling Techniques for Complex RTL Circuits / N. R. Potlapally ; G. Lakshminarayana ; S. T. Chakradhar
Architecture of a Reconfigurable Low Power Gigabit ATM Switch / A. M. Lele
Formulation and Validation of an Energy Dissipation Model for the Clock Generation Circuitry and Distribution Networks / D. Duarte ; V. Narayanan ; M. J. Irwin ; M. Kandemir
Software Power Optimizations in an Embedded System / V. Dalal
Analog Design / Session 3C:
Library Binding for High-Level Synthesis of Analog Systems / S. Ganesan ; R. Vemuri
An Integrated Quadrature Mixer with Improved Image Rejection at Low Voltage
A Code Transition Delay Model for ADC Test / S. Mohan ; M. L. Bushnell
Computing Phase Noise Eigenfunctions Directly from Harmonic Balance/Shooting Matrices / A. Demir ; D. Long ; J. Roychowdhury
FPGA / Session 4A:
Logic Synthesis for CPLDs and FPGAs with PLA-Style Logic Blocks / K. Yan
FPGA Hardware Synthesis from MATLAB / M. Haldar ; A. Nayak ; N. Shenoy ; A. Choudhary ; P. Banerjee
Efficient Synthesis of Array Intensive Computations onto FPGA Based Accelerators
Performance Driven Optimization for MUX Based FPGAs
Application Specific Macro Based Synthesis / S. Sundararaman ; S. Govindarajan
Physical Design / Session 4B:
Modeling of Nonuniform Interconnects by Using Differential Quadrature Method / Q. Xu ; P. Mazumder ; M. Bhattacharya
A Novel Algorithm for Multi-Node Bridge Analysis of Large VLSI Circuits / S. T. Zachariah ; S. Chakravarty
How to Half Wire Lengths in the Layout of Cyclic Shifters / M. A. Hillebrand ; T. Schurger ; P.-M. Seidel
Partitioning Routing Area into Zones with Distinct Pins / K. Sinha ; S. Sur-Kolay ; P. S. Dasgupta
Physical Design II / Session 4C:
Minimizing Area and Maximizing Porosity for Cell Layouts Using Innovative Routing Strategies / S. Sengupta ; S. Ramanathan ; B. Chatterjee ; D. Goswami
Transmission Line Modeling by Modified Method of Characteristics / Z.-F. Li
Crosstalk Noise Verification in Digital Designs with Interconnect Process Variations / Nagaraj NS ; P. Balsara ; C. Cantrell
Early Evaluation of Bus Interconnects Dependability for System-on-Chip Designs / M. Lajolo ; M. S. Reorda ; M. Violante
Built-In Test / Session 5A:
An Efficient Parallel Transparent BIST Method for Multiple Embedded Memory Buffers / D. C. Huang ; W. B. Jone ; S. R. Das
Observability Register Architecture for Efficient Production Test and Debug of VLSI Circuits / D. Bhavsar ; R. Tan
Efficient Signature-Based Fault Diagnosis Using Variable Size Windows / T. Clouqueur ; O. Ercevik ; H. Takahashi
A Parallel Built-In Self-Diagnostic Method for Embedded Memory Buffers
Hierarchical Cellular Automata As an On-Chip Test Pattern Generator / B. K. Sikdar ; P. Majumder ; M. Mukherjee ; N. Ganguly ; P. P. Chaudhuri
Synthesis / Session 5B:
High Level Synthesis of Multi-Precision Data Flow Graphs / V. Agrawal ; A. Pande ; M. M. Mehendale
Multilevel Logic Minimization Using Functional Don't Cares / L. Wang ; A. E. A. Almaini
Complexity of Minimum-Delay Gate Resizing / S. Chakraborty ; R. Murgai
Synthesis of Transparent Circuits for Hierarchical and System-on-a-Chip Test / K. Chakrabarty ; R. Mukherjee ; A. Exnicios
Architecture / Session 5C:
Scaling Up of Wave Pipelines / M. Fukase ; T. Sato ; R. Egawa ; T. Nakamura
VLSI Architectures for High-Speed MAP Decoders / A. Worm ; H. Lamm ; N. Wehn
Design of Multiple Attractor GF(2[superscript P]) Cellular Automata for Diagnosis of VLSI Circuits
Synthesizing a Long Latency Unit within VLIW Processor / R. L. Gupta ; A. Van Der Werf ; G. N. Busa
Technology / Session 6A:
Invited Paper: Extending Resolution Limits of IC Fabrication Technology: Demonstration by Device Fabrication and Circuit Performance / O. Nalamasu ; G. P. Watson ; R. A. Cirelli ; J. Bude ; I. C. Kizilyalli ; R. Kohler
FD-TLM Electromagnetic Field Simulation of High-Speed III-V Heterojunction Bipolar Transistor Digital Logic Gates / R. J. Lomax
Performance Optimization of 60 nm Channel Length Vertical MOSFETs Using Channel Engineering / G. Shrivastav ; S. Mahapatra ; V. Ramgopal Rao ; J. Vasi
Effect of Fringing Capacitances in Sub 100 nm MOSFET's with High-K Gate Dielectrics / N. R. Mohapatra ; A. Dutta ; M. P. Desai ; V. R. Rao
Technology II / Session 6B:
Degradation of NMOSFETs During High-Field Injection with Reverse Biased Voltage at Source and Drain Junctions / R. K. Jarwal ; D. Misra
High Frequency Behaviour of Electron Transport in Silicon and Its Implication for Drain Conductance of MOS Transistors / B. Prasad ; P. J. George ; C. Shekhar
An On-Chip Coupling Capacitance Measurement Technique / P. A. Nair ; A. Gupta
Spectral Algorithm to Compute and Synthesize Reduced Order Passive Models for Arbitrary RC Multiports / S. H. Batterywala ; H. Narayanan
Deep Sub-Micron / Session 6C:
Repeater Insertion to Minimise Delay in Coupled Interconnects / D. Pamunuwa ; H. Tenhunen
Integrated Crosstalk and Oxide Integrity Analysis in DSM Designs / N. V. Arvind ; P. R. Suresh ; V. Sivakumar ; C. Pal ; D. Das
Switching Noise Analysis Framework for High Speed Logic Families / M. Delaurenti ; M. Graziano ; G. Masera ; G. Piccinini ; M. Zamboni
Estimating Crosstalk from VLSI Layouts / V. S. Subramanian
Author Index
VLSI Design 2002 Call for Papers
5th IEEE VLSI Design and Test Workshops 2001 Call for Participation
General Chair's Message
Message from the Program Chairs
Conference Committee
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