| Welcome to ICCD |
| Organizing Committee |
| Program Committee |
| Additional Reviewers |
| ICCD 2002 Call for Papers |
| Keynote Addresses |
| The In-Car Computing Network: A Challenge for Embedded Systems / K.-T. Neumann |
| Clear and Present Tensions in Microprocessor Design / J. Shen |
| Moore's Law Meets Shannon's Law: The Evolution of the Communications Industry / L. Harrison |
| Technical Program |
| Asynchronous Techniques / Session 1.1： |
| Mousetrap: Ultra-High-Speed Transition-Signaling Asynchronous Pipelines / M. Singh ; S. M. Nowick |
| Arithmetic Logic Circuits using Self-Timed Bit Level Dataflow and Early Evaluation / R. B. Reese ; M. A. Thornton ; C. Traver |
| Efficient Systematic Error-Correcting Codes for Semi-Delay-Insensitive Data Transmission / F.-C. Cheng ; S.-L. Ho |
| Embedded Tutorial / Session 1.2： |
| Session Abstract |
| Design Constraints for Efficient Cryptographic Processing in Smart Cards / J.-F. Dhem |
| Security of Smartcard Integrated Circuits / E. von Faber |
| Architectural Modeling: Performance and Power Analysis / Session 1.3： |
| Minimal Subset Evaluation: Rapid Warm-Up for Simulated Hardware State / J. W. Haskins, Jr. ; K. Skadron |
| A Framework for Energy Estimation of VLIW Architecture / H. S. Kim ; N. Vijaykrishnan ; M. Kandemir ; M. J. Irwin |
| High-Level Power Modeling of CPLDs and FPGAs / L. Shang ; N. K. Jha |
| Caching / Session 2.1： |
| Symbolic Cache: Fast Memory Access Based on Program Syntax Correlation of Loads and Stores / Q. Ma ; J.-K. Peir ; L. Peng ; K. Lai |
| In-Line Interrupt Handling for Software-Managed TLBs / A. Jaleel ; B. Jacob |
| Design of a Predictive Filter Cache for Energy Savings in High Performance Processor Architectures / W. Tang ; R. Gupta ; A. Nicolau |
| Simulation Based Verification / Session 2.2： |
| A New Functional Test Program Generation Methodology / F. Fallah ; K. Takayama |
| A Functional Validation Technique: Biased-Random Simulation Guided by Observability-Based Coverage / S. Tasiran ; D. G. Chinnery ; S. J. Weber ; K. Keutzer |
| Selecting a Well Distributed Hard Case Test Suite for IEEE Standard Floating Point Division / L. D. McFearin ; D. W. Matula |
| Modeling of Capacitance and Crosstalk Noise / Session 2.3： |
| Linear Time Hierarchical Capacitance Extraction without Multipole Expansion / S. Balakrishnan ; J. H. Park ; H. Kim ; Y.-M. Lee ; C. C.-P. Chen |
| Analysis and Reduction of Capacitive Coupling Noise in High-Speed VLSI Circuits / P. Heydari ; M. Pedram |
| Crosstalk Noise Estimation for Generic RC Trees / M. Takahashi ; M. Hashimoto ; H. Onodera |
| Improving the Performance of Caching Structures / Session 3.1： |
| A Banked-Promotion TLB for High Performance and Low Power / J.-H. Lee ; J.-S. Lee ; S.-W. Jeong ; S.-D. Kim |
| Filtering Superfluous Prefetches Using Density Vectors / W.-F. Lin ; S. K. Reinhardt ; D. Burger ; T. R. Puzak |
| Allocation by Conflict: A Simple, Effective Multilateral Cache Management Scheme / E. S. Tam ; S. A. Vlaovic ; G. S. Tyson ; E. S. Davidson |
| Test Pattern Generation, Test Compaction, and Test Point Insertion for Synchronous Sequential Circuits / Session 3.2： |
| COREL: A Dynamic Compaction Procedure for Synchronous Sequential Circuits with Repetition and Local Static Compaction / I. Pomeranz ; S. M. Reddy |
| A Partitioning and Storage Based Built-In Test Pattern Generation Method for Synchronous Sequential Circuits |
| Cost-Effective Non-Scan Design for Testability for Actual Testability Improvement / D. Xiang ; Y. Xu |
| Power 4 Microprocessor / Session 3.3 Invited Session： |
| Power4 Microprocessor and System Design / J. Clabes |
| Power4 Design Methodology / B. Zoric |
| Semi-Custom Design Methodology for Power4 / P. Strenski |
| Power4 Integration / M. Scheuermann |
| Boolean Reasoning for Applications in CAD / A. KuehlmannSession 4.1： |
| Computer Arithmetic / Session 4.2： |
| Improved ZDN-Arithmetic for Fast Modulo Multiplication / H. Ploog ; S. Flugel ; D. Timmermann |
| Design Alternatives for Parallel Saturating Multioperand Adders / P. I. Balzola ; M. J. Schulte ; J. Ruan ; J. Glossner ; E. Hokenek |
| A Single-Multiplier Quadratic Interpolator for LNS Arithmetic / M. G. Arnold ; M. D. Winkel |
| Circuit Sizing and Optimization / Session 4.3： |
| Gate Sizing to Eliminate Crosstalk Induced Timing Violation / T. Xiao ; M. Marek-Sadowska |
| Performance Optimization by Wire and Buffer Sizing under the Transmission Line Model / T.-C. Chen ; S.-R. Pan ; Y.-W. Chang |
| Buffered Interconnect Tree Optimization using Lagrangian Relaxation and Dynamic Programming / S.-Y. Lai ; R. Baldick |
| Clocking and Time-Domain Measurements / Session 5.1： |
| Embedded Tutorial: Clocked Timing Elements for High-Performance and Low-Power VLSI Systems / V. Oklobdzija |
| Jitter-Induced Power/Ground Noise in CMOS PLLs: A Design Perspective |
| On the Micro-Architectural Impact of Clock Distribution Using Multiple PLLs / M. Saint-Laurent ; M. Swaminathan ; J. D. Meindl |
| On-Chip Oscilloscopes for Noninvasive Time-Domain Measurement of Waveforms / K. L. Shepard ; Y. Zheng |
| Processor Microarchitecture / Session 5.2： |
| Selective Branch Prediction Reversal by Correlating with Data Values and Control Flow / J. L. Aragon ; J. Gonzalez ; J. M. Garcia ; A. Gonzalez |
| Mutable Functional Units and Their Applications on Microprocessors / Y. Solihin ; K. W. Cameron ; Y. Luo ; D. Lavenier ; M. Gokhale |
| Compiler-Directed Classification of Value Locality Behavior / Q. Zhao ; D. J. Lilja |
| A Hierarchical Dependence Check and Folded Rename Mapping Based Scalable Dispatch Stage / V. Sankaranarayanan ; A. Tyagi |
| Invited Session: Taming Tons of Gigabytes: Innovations in Disk Drive Electronics / Session 5.3： |
| Designing Circuits for Disk Drives / G. Pelz |
| Hard Disk Controller: The Disk Drive's Brain and Body / J. Jeppensen ; W. Allen ; S. Anderson ; M. Pilsl |
| Motion-Control: The Power Side of Disk Drives / W. Sereinig |
| Energy Efficiency Caches and Multiport Cache Structures / Session 6.1： |
| Static Energy Reduction Techniques for Microprocessor Caches / H. Hanson ; M. S. Hrishikesh ; V. Agarwal ; S. W. Keckler |
| Parallel Cachelets / D. Limaye ; R. Rakvic ; J. P. Shen |
| Access Region Cache: A Multi-Porting Solution for Future Wide-Issue Processors / B. S. Thakar ; G. Lee |
| Control by Simulation and On-line Checking / Session 6.2： |
| Distributed Event-Driven Simulation of VHDL-SPICE Mixed-Signal Circuits / D. Lungeanu ; C. J. R. Shi |
| High Performance Parallel Fault Simulation / A. K. Varshney ; B. Vinnakota ; E. Skuldt ; B. Keller |
| On-Line Integrity Monitoring of Microprocessor Control Logic / S. Kim ; A. K. Somani |
| CAD Algorithms for Physical Design / Session 6.3： |
| A Timing-Driven Macro-Cell Placement Algorithm / F. Mo ; A. Tabbara ; R. K. Brayton |
| Fixed-Outline Floorplanning through Better Local Search / S. N. Adya ; I. L. Markov |
| Generic ILP-Based Approaches for Dynamically Reconfigurable FPGA Partitioning / G.-M. Wu ; J.-M. Lin ; M. C.-T. Chao |
| Panel Discussion |
| How Much Longer Will SuperScalar Microarchitectures Scale? / D. Burger (chair) ; M. Hill ; M. Hopkins ; M. McDermott ; Y. Patt ; M. Snyder ; G. Sohi |
| Invited Session: Network Processors / Session 7.1： |
| Network Processing: Applications and Challenges / C. Narad |
| Payload+: Fast Pattern Matching and Routing for OC-48 / D. Kramer |
| Scaling Fully Programmable Network Processing to 10Gbps and Beyond / K. Morris |
| Formal Methods for Property Verification and Equivalence Verification / Session 7.2： |
| Arithmetic Transforms for Verifying Compositions of Sequential Datapaths / K. Radecka ; Z. Zilic |
| Hierarchical Image Computation with Dynamic Conjunction Scheduling / C. Meinel ; C. Stangier |
| Introduction to Generalized Symbolic Trajectory Evaluation / J. Yang ; C.-J. H. Seger |
| Hardware Representation / Session 7.3： |
| BDD Variable Ordering by Scatter Search / W. N. N. Hung ; X. Song |
| Lower Bound Based DDD Minimization for Efficient Symbolic Circuit Analysis / A. Manthe ; C-J. R. Shi |
| Run-Time Execution of Reconfigurable Hardware in a Java Environment / L. A. S. King ; H. Quinn ; M. Leeser ; D. Galatopoullos ; E. Manolakos |
| Circuit Techniques / Session 8.1： |
| Realization of Multiple-Output Functions by Reconfigurable Cascades / Y. Iguchi ; T. Sasao ; M. Matsuura |
| A Low-Power Cache Design for CalmRISC-Based Systems / S. Cho ; W. Jung ; Y. Kim |
| Interconnect-Centric Array Architectures for Minimum SRAM Access Time / A. J. Bhavnagarwala ; S. Kosonocky |
| Understanding and Addressing the Noise Induced by Electrostatic Discharge in Multiple Power Supply Systems / J. Lee ; Y. Huh ; P. Bendix ; S.-M. Kang |
| DSP/Multimedia / Session 8.2： |
| Cost-Effective Hardware Acceleration of Multimedia Applications / D. Talla ; L. K John |
| MPEG Macroblock Parsing and Pel Reconstruction on an FPGA-Augmented TriMedia Processor / M. Sima ; S. Cotofana ; S. Vassiliadis ; J. T. J. van Eijndhoven ; K. Vissers |
| Low-Energy DSP Code Generation Using a Genetic Algorithm / M. Lorenz ; R. Leupers ; P. Marwedel ; T. Drager ; G. Fettweis |
| Voltage Scaling for Energy Minimization with QoS Constraints / A. Manzak ; C. Chakrabarti |
| Novel Architectures and ISA Extensions / Session 8.3： |
| Matching Architecture to Application via Configurable Processors: A Case Study with Boolean Satisfiability Problem / Y. Zhao ; S. Malik ; A. Wang ; M. W. Moskewicz ; C. F. Madigan |
| Architectural Enhancements for Fast Subword Permutations with Repetitions in Cryptographic Applications / J. P. McGregor ; R. B. Lee |
| 3DCGiRAM: An Intelligent Memory Architecture for Photo-Realistic Image Synthesis / H. Kobayashi ; K. Suzuki ; K. Sano ; Y. Kaeriyama ; Y. Saida ; N. Oba ; T. Nakamura |
| Use of Local Memory for Efficient Java Execution / S. Tomar |
| Poster Papers |
| An Analytical Model for Trace Cache Instruction Fetch Performance / A. Hossain ; D. J. Pease |
| Performance Driven Global Routing through Gradual Refinement / J. Hu ; S. S. Sapatnekar |
| Fuzzified Iterative Algorithms for Performance Driven Low Power VLSI Placement / S. M. Sait ; H. Youssef ; J. A. Khan ; A. El-Maleh |
| Fast Specification of Cycle-Accurate Processor Models / F. S.-H. Chang ; A. J. Hu |
| A Performance Analysis of the Active Memory System / W. Srisa-an ; C.-T. D. Lo ; J. M. Chang |
| Combined IEEE Compliant and Truncated Floating Point Multipliers for Reduced Power Dissipation / K. E. Wires ; J. E. Stine |
| An Algorithm for Dynamically Reconfigurable FPGA Placement |
| RC-In RC-Out Model Order Reduction Accurate up to Second Order Moments / P. Ganesh |
| Efficient Function Approximation for Embedded and ASIC Applications / J. W. Hauser ; C. N. Purdy |
| An Area-Efficient Iterative Modified-Booth Multiplier Based on Self-Timed Clocking / M.-C. Shin ; S.-H. Kang ; I.-C. Park |
| A Heuristic for Multiple Weight Set Generation / H.-S. Kim ; S. Kang |
| Towards a Formal Model of Shared Memory Consistency for Intel Itanium / P. Chatterjee ; G. Gopalakrishnan |
| Efficient Algorithms for Subcircuit Enumeration and Classification for the Module Identification Problem / J. L. White ; M.-J. Chung ; A. S. Wojcik ; T. E. Doom |
| MCOMA: A Multithreaded COMA Architecture / H. El Naga ; J.-L. Gaudiot |
| Automatic Generation and Validation of Memory Test Models for High Performance Microprocessors / K. Zarrineh ; T. A. Ziaja ; A. Majumdar |
| Reducing Cache Pollution of Prefetching in a Small Data Cache / P. Reungsang ; S. K. Park ; H.-L. Roh |
| Alloyed Path-Pattern Scheme for Branch Prediction / R. Ramanujam ; M. Ravirala |
| Timing Characterization of Dual-Edge Triggered Flip-Flops / N. Nedovic ; M. Aleksic ; V. G. Oklobdzija |
| Performance Impact of Addressing Modes on Encryption Algorithms / A. M. Fiskiran |
| Determining Schedules for Reducing Power Consumption Using Multiple Supply Voltages / N. Chabini ; E. M. Aboulhamid ; Y. Savaria |
| Pre-Routing Estimation of Shielding for RLC Signal Integrity / J. D. Z. Ma ; A. Parihar ; L. He |
| Author Index |
図書
