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1.

図書

図書
sponsored by IEEE Computer Society, Test Technology Technical Council and IEEE Philadelphia Section
出版情報: Washington, D.C. : International Test Conference, c2001  xiv, 1201 p. ; 29 cm
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2.

図書

図書
sponsored by IEEE Computer Society Test Technology Technical Council
出版情報: Los Alamitos, Calif. : IEEE Computer Society, c2001  xxxiii, 417 p. ; 28 cm
所蔵情報: loading…
目次情報: 続きを見る
Foreword
Acknowledgements
Organizing Committee
Steering Committee
Program Committee
Reviewers
VTS 2000 Best Paper Award
VTS 2000 Best Tutorial Award
Test Technology Technical Council
Test Technology Education Program: Overview of Tutorials
Plenary Session
Welcome Message
Keynote Address: Staying Ahead of the Test Technology Curve / Roger W. Blethen
Program Introduction / Sreejit Chakravarty ; Andre Ivanov
Invited Presentation: Testing the Limits of System-on-Chip / Ronnie Vasishta
BIST Techniques / Session 1:
Hybrid BIST Based on Weighted Pseudo-Random Testing: A New Test Resource Partitioning Scheme / A. Jas ; C. Krishna ; N. Touba
Compression Technique for Interactive BIST Application / D. Kay ; S. Mourad
Robust and Low-Cost BIST Architectures for Sequential Fault Testing in Datapath Multipliers / M. Psarakis ; D. Gizopoulos ; A. Paschalis ; N. Kranitis ; Y. Zorian
Diagnosis Methods / Session 2:
Diagnosis of Tunneling Opens / J. Li ; E. McCluskey
On Diagnosing Path Delay Faults in an At-Speed Environment / R. Tekumalla ; S. Venkataraman ; J. Ghosh-Dastidar
On Improving the Accuracy Of Multiple Defect Diagnosis / S.-Y. Huang
Test Data Compression / Session 3:
Frequency-Directed Run-Length (FDR) Codes with Application to System-on-a-Chip Test Data Compression / A. Chandra ; K. Chakrabarty
Design of Parameterizable Error-Propagating Space Compactors for Response Observation / A. Morosov ; M. Gossel ; B. Bhattacharya
A Geometric-Primitives-Based Compression Scheme for Testing Systems-on-a-Chip / A. El-Maleh ; S. al Zahir ; E. Khan
Sythesis and Design for Testability / Session 4:
Testable Sequential Circuit Design: A Partition and Resynthesis Approach / R. Chou ; K. Saluja
A Methodology for Testing High-Performance Circuits at Arbitrarily Low Test Frequency / M. Nummer ; M. Sachdev
Breaking Correlation to Improve Testability / K. Ockunzzi ; C. Papachristou
Scan Chain Design / Session 5:
Partial Reset for Synchronous Sequential Circuits Using Almost Independent Reset Signals / D. Xiang ; Y. Xu
Multiple Scan Chain Design for Two-Pattern Testing / I. Polian ; B. Becker
Scan Wheel - A Technique for Interfacing a High Speed Scan-Path with a Slow Speed Tester / D. Bhavsar
Innovative Measurement Techniques / Session 6:
A Method for Measuring the Cycle-to-Cycle Period Jitter of High-Frequency Clock Signals / T. Yamaguchi ; M. Soma ; D. Halter ; R. Raina ; J. Nissen ; M. Ishida
Built-in-Chip Testing of Voltage Overshoots in High-Speed SoCs / A. Attarha ; M. Nourani
Current Measurement for Dynamic Idd Test / X. Sun ; B. Vinnakota
Diagnosis and Verification ATPG / Session 7:
Fault Equivalence Identification Using Redundancy Information and Static and Dynamic Extraction / M. Amyeen ; W. Fuchs ; I. Pomeranz ; V. Boppana
Semi-Formal Test Generation for a Block of Industrial DSP / J. Dushina ; M. Benjamin ; D. Geist
Defect Analysis and IDDx Diagnosis / Session 8:
Resistive Opens in a Class of CMOS Latches: Analysis and DFT / A. Zenteno ; V. Champac
A Process and Technology-Tolerant I[subscript DDQ] Method for IC Diagnosis / C. Patel ; J. Plusquellic
Panel / Special Session 1:
Guaranteeing Quality throughout the Product Life Cycle: On-Line Test and Repair to the Rescue
Hot Topic Session / Special Session 2:
ITRS Test Chapter 2001: We'll Tell You What We're Doing, You Tell Us What We Should Be Doing
SOC Testing / Session 9:
Socillator Test: A Delay Test Scheme for Embedded ICs in the Boundary-Scan Environment / T. Tan ; C. Lee
Novel Spectral Methods for Built-In Self-Test in a System-on-a-Chip Environment / A. Giani ; S. Sheng ; M. Hsiao ; V. Agrawal
High-Level Crosstalk Defect Simulation for System-on-Chip Interconnects / X. Bai ; S. Dey
Online Testing / Session 10:
Design Diversity for Concurrent Error Detection in Sequential Logic Circuits / S. Mitra
Early Error Detection in Systems-on-Chip for Fault-Tolerance and At-Speed Debugging / E. Sogomonyan ; A. Singh ; J. Rzeha
Design of Redundant Systems Protected against Common-Mode Failures
Self-Test Techniques / Session 11:
A Self-Test Methodology for IP Cores in Bus-Based Programmable SoCs / J.-R. Huang ; M. Iyer ; K.-T. Cheng
Embedded-Software-Based Approach to Testing Crosstalk-Induced Faults at On-Chip Buses / W.-C. Lai
Electrically Induced Stimuli for MEMS Self-Test / B. Charlot ; S. Mir ; F. Parrain ; B. Courtois
Memory Testing / Session 12:
Flash Memory Disturbances: Modeling and Test / M. Mohammad
Efficient Neighborhood Pattern-Sensitive Fault Test Algorithms for Semiconductor Memories / K.-L. Cheng ; M.-F. Tsai ; C.-W. Wu
An Efficient Methodology for Generating Optimal and Uniform March Tests / S. Al-Harbi ; S. Gupta
Scalable Fault Simulation, Model Build and ATPG Methods / Session 13:
RT-Level Fault Simulation Based on Symbolic Propagation / O. Sinanoglu ; A. Orailoglu
Efficient Transparency Extraction and Utilization in Hierarchical Test / Y. Makris ; V. Patel
Analysis of Testing Methodologies for Custom Designs in PowerPC[superscript TM] Microprocessor / M. Abadir ; J. Zhu ; L.-C. Wang
Test Stimulus Generation for Analog Testing / Session 14:
Test Waveform Shaping in Mixed Signal Test Bus by Pre-Equalization / Y.-T. Chen ; C. Su
A Low-Cost Adaptive Ramp Generator for Analog BIST Applications / F. Azais ; S. Bernard ; Y. Bertrand ; X. Michel ; M. Renovell
Self-Testable Pipelined ADC with Low Hardware Overhead / E. Peralias ; G. Huertas ; A. Rueda ; J. Huertas
Soft Errors and Tolerance for Soft Errors / Special Session 3:
Embedded Tutorial / Special Session 4:
Yield Optimization and Its Relation to Test
ATPG for Design Errors--Is It Possible? / Special Session 5:
Memory Diagnosis / Session 15:
Defect Oriented Fault Diagnosis for Semiconductor Memories Using Charge Analysis, Theory and Experiments / I. de Paul ; M. Rosales ; B. Alorda ; J. Segura ; C. Hawkins ; J. Soden
Enabling Embedded Memory Diagnosis via Test Response Compression / J. Chen ; J. Rajski ; J. Khare ; O. Kebichi ; W. Maly
Automatic Generation of Diagnostic March Tests / D. Niggemeyer ; E. Rudnick
Minimizing Test Power / Session 16:
A Modified Clock Scheme for a Low Power BIST Test Pattern Generator / P. Girard ; L. Guiller ; C. Landrault ; S. Pravossoudovitch ; H.-J. Wunderlich
Test Scheduling for Minimal Energy Consumption under Power Constraints / T. Schuele ; A. Stroele
Reducing Power Dissipation during Test Using Scan Chain Disable / R. Sankaralingam ; B. Pouya
Estimating and Reducing Infant Mortality / Session 17:
Burn-in Failures and Local Region Yield: An Integrated Yield-Reliability Model / T. Barnett ; V. Nelson
High-Voltage Stress Test Paradigms of Analog CMOS ICs for Gate-Oxide Reliability Enhancement / M. Khalil ; C.-L. Wey
MINVDD Testing for Weak CMOS ICs / C.-W. Tseng ; R. Chen ; P. Nigh
Novel ATPG Techniques / Session 18:
SPIRIT: A Highly Robust Combinational Test Generation Algorithm / E. Gizdarski ; H. Fujiwara
On the Use of Fault Dominance in n-Detection Test Generation / S. Reddy
Test Generation for Maximizing Ground Bounce for Internal Circuitry with Reconvergent Fan-outs / Y.-S. Chang ; M. Breuer
Test Scheduling, Leakage Estimation and Onchip Delay Measurement / Session 19:
Precedence-Based, Preemptive, and Power-Constrained Test Scheduling for System-on-a-Chip / V. Iyengar
Average Leakage Current Estimation of CMOS Logic Circuits / J. de Gyvez ; E. van de Wetering
An On-Chip Short-Time Interval Measurement Technique for Testing High-Speed Communication Links / J.-L. Huang
Fault Modeling and BIST Evaluation / Session 20:
Tools for the Characterization of Bipolar CML Testability / G. Monte ; B. Antaki ; S. Patenaude ; Y. Savaria ; C. Thibeault ; P. Trouborst
Testing of Dynamic Logic Circuits Based on Charge Sharing / K. Heragu ; M. Sharma ; R. Kundu ; R. Blanton
An Evaluation of Pseudo Random Testing for Detecting Real Defects / S. Davidson
Showcase / Special Session 6:
IP and Automation to Support IEEE P1500
Reliability Beyond GHz / Special Session 7:
Analog and Mixed Signal Benchmark Circuit Development: Who Needs Them? / Special Session 8:
Author Index
Foreword
Acknowledgements
Organizing Committee
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