Proceedings, 2001 IEEE International Workshop on Memory Technology, Design and Testing, August 6-7, 2001, San Jose, California, USA

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Proceedings, 2001 IEEE International Workshop on Memory Technology, Design and Testing, August 6-7, 2001, San Jose, California, USA / editors, Yervant Zorian ... [et al.] ; sponsored by IEEE Computer Society, IEEE Computer Society Technical Council on Test Technology, IEEE Computer Society Technical Committee on VLSI ; in cooperation with IEEE Solid State Circuits Society

資料種別:

図書

出版情報:

Los Alamitos, Calif. : IEEE Computer Society, c2001

形態:

viii, 108 p. ; 28 cm

著者名:

IEEE International Workshop on Memory Technology, Design, and Testing <DA12300318>

Zorian, Yervant

Courtois, B. (Bernard) <DA09741734>

Wik, Thomas

Cockburn, Bruce

IEEE Computer Society <DA00479199>

IEEE Computer Society. Test Technology Technical Council <DA1250352X>

IEEE Computer Society. Technical Committee on VLSI <DA04967445>

IEEE Solid-State Circuits Society <DA13128277>

さらに 4 件

ISBN:

9780769512426 [0769512429]
9780769512433 [0769512437] (: case)

書誌ID:

BA53591736

子書誌情報

フルテキスト

所蔵情報

他の版・巻

書誌詳細

その他の標題:

Records of the 2001 IEEE International Workshop on Memory Technology, Design and Testing
PR01242

注記:

"IEEE Computer Society Order Number PR01242" -- T. p. verso
Includes bibliographical references and index

言語:

英語

目次情報:

Message from the Chairs

Conference Committee

TTTC Information

Plenary Session

Memory Design / Session 1：

A DRAM Compiler for Fully Optimized Memory Instances / G. Harling

Orthogonal Transpose-RAM Cell Array Architecture with Alternate Bit-Line To Bit-Line Contact Scheme / K. Kim ; K. Rho ; K. Lee

Design of an Embedded Fully-Depleted SOI SRAM / R. Sung ; J. Koob ; T. Brandon ; D. Elliott ; B. Cockburn

Memory BIST / Session 2：

A P1500 Compliant Programable BistShell for Embedded Memories / S. Koranne ; C. Wouters ; T. Waayers ; S. Kumar ; R. Beurze ; G. Visweswaran

BIST-Based Bitfail Mapping of an Embedded DRAM / B. Kessler ; J. Dreibelbis ; T. McMahon ; J. McCloy ; R. Kho

Tutorial on Soft Error in Memories / Session 3：

Special Session on Memory Yield and Manufacturability / Session 4：

Redundancy and Error Control / Session 5：

A Method to Caculate Redundancy Coverage for FLASH Memory / S. Matarrese ; L. Fasoli

An Error Control Code Scheme for Multilevel Flash Memories / S. Gregori ; O. Khouri ; R. Micheloni ; G. Torelli

An Approach for Evaluation of Redunancy Analysis Algorithms / S. Shoukourian ; V. Vardanian ; Y. Zorian

Fault Models and Multi-Port SRAM Testing / Session 6：

Transient Faults in DRAMs: Concepts, Analysis and Impact on Tests / Z. Al-Ars ; A. van de Goor

Realistic Fault Models and Test Procedures for Multi-Port SRAMs / S. Hamdioui ; D. Eastwick ; M. Rodgers

A Parallel Approach for Testing Multi-Port Static Random Access Memories / F. Karimi ; S. Irrinki ; T. Crosby ; F. Lombardi

Verification and Test / Session 7：

Equivalence Checking a 256MB SDRAM / S. Napper ; D. Yang

Testing Carry Logic Modules of SRAM-based FPGAs / X. Sun ; J. Xu ; P. Trouborst

Low Output Resistance Charge Pump for Flash Memory Programming / D. Soltesz

Author Index

Message from the Chairs

Conference Committee

TTTC Information

Plenary Session

Memory Design / Session 1：

A DRAM Compiler for Fully Optimized Memory Instances / G. Harling

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