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1.

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図書
1. Proceedings of the IEEE 2001 Custom Integrated Circuits Conference : Town and Country Hotel, May 6-9, 2001, San Diego, California (: soft.)
sponsored by the IEEE Solid State Circuits Society and the Electron Devices Society
出版情報: [United States] : IEEE, c2001  582 p. ; 28 cm
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2.

図書
図書
2. Proceedings of the 2001 Bipolar/BiCMOS Circuits and Technology Meeting, September 30 - October 2, 2001 (: softbound)
sponsored by IEEE Electron Devices Society ; in cooperation with IEEE Solid State Circuits Society IEEE Twin Cities Section
出版情報: Piscataway, N.J. : Institute of Electrical and Electronics Engineers, c2001  199 p. ; 28 cm
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3.

図書
図書
3. GaAs IC Symposium : IEEE Gallium Arsenide Integrated Circuit Symposium : 23rd Annual, Technical Digest 2001, Baltimore, Maryland, October 21-24,2001
co-sponsored by the IEEE Electron Devices Society, the IEEE Microwave Theory and Techniques Society, and the IEEE Solid-State Circuits Society
出版情報: Piscataway, N.J. : IEEE Service Center, c2001  ix, 279 p. ; 29 cm
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4.

図書
図書
4. 2001 IEEE International Solid-State Circuits Conference : digest of technical papers : ISSCC, February 5-7, 2001. 1st ed. (: softbound)
[editor, John H. Wuorinen ; sponsors, IEEE Solid-State Circuits Society, IEEE San Francisco Section, Bay Area Council, Univ. of Pa.]
出版情報: Piscataway, NJ : IEEE Service Senter, c2001  495 p. ; 28 cm
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5.

図書
図書
5. Proceedings, 2001 IEEE International Workshop on Memory Technology, Design and Testing, August 6-7, 2001, San Jose, California, USA (: case)
editors, Yervant Zorian ... [et al.] ; sponsored by IEEE Computer Society, IEEE Computer Society Technical Council on Test Technology, IEEE Computer Society Technical Committee on VLSI ; in cooperation with IEEE Solid State Circuits Society
出版情報: Los Alamitos, Calif. : IEEE Computer Society, c2001  viii, 108 p. ; 28 cm
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目次情報: 続きを見る
Message from the Chairs
Conference Committee
TTTC Information
Plenary Session
Memory Design / Session 1：
A DRAM Compiler for Fully Optimized Memory Instances / G. Harling
Orthogonal Transpose-RAM Cell Array Architecture with Alternate Bit-Line To Bit-Line Contact Scheme / K. Kim ; K. Rho ; K. Lee
Design of an Embedded Fully-Depleted SOI SRAM / R. Sung ; J. Koob ; T. Brandon ; D. Elliott ; B. Cockburn
Memory BIST / Session 2：
A P1500 Compliant Programable BistShell for Embedded Memories / S. Koranne ; C. Wouters ; T. Waayers ; S. Kumar ; R. Beurze ; G. Visweswaran
BIST-Based Bitfail Mapping of an Embedded DRAM / B. Kessler ; J. Dreibelbis ; T. McMahon ; J. McCloy ; R. Kho
Tutorial on Soft Error in Memories / Session 3：
Special Session on Memory Yield and Manufacturability / Session 4：
Redundancy and Error Control / Session 5：
A Method to Caculate Redundancy Coverage for FLASH Memory / S. Matarrese ; L. Fasoli
An Error Control Code Scheme for Multilevel Flash Memories / S. Gregori ; O. Khouri ; R. Micheloni ; G. Torelli
An Approach for Evaluation of Redunancy Analysis Algorithms / S. Shoukourian ; V. Vardanian ; Y. Zorian
Fault Models and Multi-Port SRAM Testing / Session 6：
Transient Faults in DRAMs: Concepts, Analysis and Impact on Tests / Z. Al-Ars ; A. van de Goor
Realistic Fault Models and Test Procedures for Multi-Port SRAMs / S. Hamdioui ; D. Eastwick ; M. Rodgers
A Parallel Approach for Testing Multi-Port Static Random Access Memories / F. Karimi ; S. Irrinki ; T. Crosby ; F. Lombardi
Verification and Test / Session 7：
Equivalence Checking a 256MB SDRAM / S. Napper ; D. Yang
Testing Carry Logic Modules of SRAM-based FPGAs / X. Sun ; J. Xu ; P. Trouborst
Low Output Resistance Charge Pump for Flash Memory Programming / D. Soltesz
Author Index
Message from the Chairs
Conference Committee
TTTC Information
6.

図書
図書
6. 2001 Symposium on VLSI Circuits : digest of technical papers, June 14-16, 2001, Kyoto (: softbound)
the Janan Society of Applied Physics, the IEEE Solid-State Circuits Society
出版情報: Tokyo : Business Center for Academic Societies Japan, c2001  xvi, 255 p. ; 29 cm
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