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1. Proceedings of the 2003 IEEE International Symposium on Circuits and Systems : analog circuits and signal processing : Sunday, May 25-Wednesday, May 28, 2003, Imperial Queen's Park Hotel, PBangkok, Thailand (: set - v. 5)
sponsored by the IEEE Circuits and Systems Society and the Mahanakorn University of Technology
出版情報: Piscataway, N.J. : IEEE Operations Center, c2003  5 v. ; 28 cm
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2. Proceedings 2003, Design Automation Conference : 40th, Anaheim Convention Center, Anahaim CA, June 2-6, 2003
ACM/IEEE Design Automation Conference ; ACM Special Interest Group on Design Automation ; EDA Consortium ; IEEE Circuits and Systems Society
出版情報: New York : Association for Computing Machinery, c2003  xxxiv, 981 p. ; 29 cm
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3. Proceedings : 16th International Conference on VLSI Design : concurrently with the 2nd International Conference on Embedded Systems Design : 4-8 January 2003, New Delhi, India
sponsored by VLSI Society of India (VSI), Ministry of Communication and Information Technology, Government of India ; in cooperation with IEEE Circuits and Systems Society, ACM SIGDA, NASSCOM
出版情報: Los Alamitos, Calif. : IEEE Computer Society, c2003  xxvi, 595 p. ; 28 cm.
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4.

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4. Proceedings of the ASP-DAC 2003 : Asia and South Pacific Design Automation Conference 2003, January 21-January 24, 2003, Kitakyushu International Conference Center, Kitakyushu, Japan (: [pbk])
sponsored by IEEE Circuits and Systems Society...[et al.] ; supported by JEITA (Japan Electronics and Information Technologies Industry Asscociation)...[et al.] ; in cooperation with JIEP (Japan Institute of Electronics Packaging)
出版情報: Piscataway, N.J. : IEEE, c2003  xl, 914 p. ; 30 cm
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5.

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5. Proceedings : 21st International Conference on Computer Design : October 13 to 15, 2003, San Jose, California (: softbound)
sponsored by IEEE Computer Society, IEEE Circuits and Systems Society ; in cooperation with IEEE Electron Devices Society
出版情報: Los Alamitos, Calif. : IEEE Computer Society, c2003  xxii, 563 p. ; 28 cm
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目次情報: 続きを見る
Welcome
Organizing Committee
Program Committee
Additional Reviewers
Keynotes
High-Speed Link Design, Then and Now / M. Horowitz
Terascale Computing and BlueGene / W. Pulley
Advanced EDA Tools for High-Performance Design / T. Vucurevich
Energy Efficiency / Session 1.1：
Energy Efficient Asymmetrically Ported Register Files / A. Aggarwal ; M. Franklin
Power Efficient Data Cache Designs / J. Abella ; A. Gonzalez
On Reducing Register Pressure and Energy in Multiple-Banked Register Files
Low Power Multiplication Algorithm for Switching Activity Reduction through Operand Decomposition / M. Ito ; D. Chinnery ; K. Keutzer
Timing Verification / Session 1.2：
Verification of Timed Circuits with Failure Directed Abstractions / H. Zheng ; C. Myers ; D. Walter ; S. Little ; T. Yoneda
Procedures for Identifying Untestable and Redundant Transition Faults in Synchronous Sequential Circuits / G. Chen ; S. Reddy ; I. Pomeranz
Event-Centric Simulation of Crosstalk Pulse Faults in Sequential Circuits / M. Phadoongsidhi ; K. Saluja
Specifying and Verifying Systems with Multiple Clocks / E. Clarke ; D. Kroening ; K. Yorav
Electrical Analysis for System LSI / Session 1.3：
Enhanced QMM-BEM Solver for 3-D Finite-Domain Capacitance Extraction with Multilayered Dielectrics / W. Yu ; Z. Wang ; X. Hong
An Improved Method for Fast Noise Estimation Based on Net Segmentation / C. Huang ; A. Dasgupta
Symbolic Failure Analysis of Custom Circuits due to Excessive Leakage Current / H. Song ; S. Bohidar ; I. Bahar ; J. Grodstein
An Efficient Algorithm for Calculating the Worst-case Delay due to Crosstalk / V. Rajappan ; S. Sapatnekar
Power Optimization / Session 2.1：
A Compact Model for Analysis and Design of On-chip Power Network with Decoupling Capacitors / P. Zarkesh-Ha ; K. Doniger ; W. Loh ; D. Sun ; R. Stephani ; G. Priebe
Precomputation-Based Guarding for Dynamic and Leakage Power Reduction / A. Abddollahi ; M. Pedram ; F. Fallah ; I. Ghosh
Charge-Recycling Voltage Domains for Energy-Efficient Low-Voltage Operation of Digital CMOS Circuits / S. Rajapandian ; Z. Xu ; K. Shepard
Low Power Adder with Adaptive Supply Voltage / H. Suzuki ; W. Jeong ; K. Roy
A Transparent Voltage Conversion Method and Its Application to a Dual-Supply-Voltage Register File / N. Tzartzanis ; W. Walker
Invited Session: Gene Chip Design / Session 2.2：
Detection of Biological Molecules: From Self-Assembled Films to Self-Integrated Devices / R. Levicky
Embedded Tutorial
Design Flow Enhancements for DNA Arrays / A. Kahng ; I. Mandoiu ; S. Reda ; X. Xu ; A. Zelikovsky
System Level Design / Session 2.3：
Bus Architecture Synthesis for Hardware-Software Co-Design of Deep Submicron Systems on Chip / N. Thepayasuwan ; V. Damle ; A. Doboli
Dynamically Optimized Synchronous Communication for Low Power System on Chip Designs / V. Chandra ; G. Carpenter ; J. Burns
Interface Synthesis Using Memory Mapping for an FPGA Platform / M. Luthra ; S. Gupta ; N. Dutt ; R. Gupta ; A. Nicolau
Efficient Synthesis of Networks On Chip / A. Pinto ; L. Carloni ; A. Sangiovanni-Vincentelli
Reducing Compilation Time Overhead in Compiled Simulators / M. Reshadi
Systems Performance / Session 3.1：
Profiling Interrupt Handler Performance through Kernel Instrumentation / B. Moore ; T. Slabach ; L. Schaelicke
Design and Performance of Compressed Interconnects for High Performance Servers / K. Kant ; R. Iyer
Routed Inter-ALU Networks for ILP Scalability and Performance / K. Sankaralingam ; V. Singh ; S. Keckler ; D. Burger
Micro Processor Test & Diagnosis / Session 3.2：
Automatic Generation of Critical-Path Tests for a Partial-Scan Microprocessor / D. Bhavsar ; V. Bettada ; R. Davies
Test Generation for Non-separable RTL Controller-datapath Circuits Using a Satisfiability Based Approach / L. Lingappan ; S. Ravi ; N. Jha
Cost-Effective Graceful Degradation in Speculative Processor Subsystems: The Branch Prediction Case / S. Almukhaizim ; T. Verdel ; Y. Makris
Multiple Fault Diagnosis Using n-Detection Tests / M. Marek-Sadowska ; K. Tsai ; J. Rajski
Physical Design / Session 3.3：
A Physical Design Methodology for 1.3GHz SPARC64 Microprocessor / N. Ito ; H. Komatsu ; Y. Tanamura ; R. Yamashita ; H. Sugiyama ; Y. Sugiyama ; H. Hamamura
Physical Design of the "2.5D" Stacked System / Y. Deng ; W. Maly
Flow-Based Cell Moving Algorithm for Desired Cell Distribution / B. Choi ; H. Xu ; M. Wang ; M. Sarrafzadeh
Performance Optimization / Session 4.1：
NpBench: A Benchmark Suite for Control plane and Data plane Applications for Network Processors / B. Lee ; L. John
Hardware-Only Compression of Underutilized Address Buses: Design and Performance, Power, and Cost Analysis / N. Mahapatra ; J. Liu ; K. Sundaresan
Pipelined Multiplicative Division with IEEE Rounding / G. Even ; P. Seidel
Clock & Signal Distribution / Session 4.2：
Design of Resonant Global Clock Distributions / S. Chan ; P. Restley
Modeling and Mitigation of Jitter in Multi-Gbps Source-Synchronous I/O Links / G. Balamurugan ; N. Shanbhag
A Mixed-Mode Delay-Locked Loop Architecture / D. Eckerbert ; L. Svensson ; P. Larsson-Edefors
Optimal Inductance for On-chip RLC Interconnections / S. Das ; K. Agarwal ; D. Blaauw ; D. Sylvester
Performance and Power-Driven Physical Design / Session 4.3：
Spec Based Flip-Flop and Buffer Insertion / N. Akkiraju ; M. Mohan
A Microeconomic Model for Simultaneous Gate Sizing and Voltage Scaling for Power Optimization / N. Ranganathan ; A. Murugavel
A Simple Yet Effective Merging Scheme for Prescribed-Skew Clock Routing / R. Chaturvedi ; J. Hu
Instruction Execution / Session 5.1：
Hardware-Based Pointer Data Prefetcher / S. Lai ; S. Lu
A Dependence Driven Efficient Dispatch Scheme / S. Nadathur ; A. Tyagi
An Efficient VLIW DSP Architecture for Baseband Processing / T. Lin ; C. Chang ; C. Lee ; C. Jen
Dynamic Thread Resizing for Speculative Multithreaded Processors / M. Zahran
Invited Session: Test Compression Technology / Session 5.2：
Care Bit Density and Test Cube Clusters: Multi-Level Compression Opportunities / B. Koenemann
XMAX: X-Tolerant Architecture for MAXimal Test Compression / S. Mitra ; K. Kim
Test Data Compression and Compaction for Embedded Test of Nanometer Technology Designs / J. Tyszer
Physical Design for Regular Fabrics and FPGA's / Session 5.3：
Non-Crossing OBDDs for Mapping to Regular Circuit Structures / A. Cao ; C. Koh
Interconnect Estimation for FPGAs under Timing Driven Domains / P. Kannan ; D. Bhatia
ROAD: An Order-Impervious Optimal Detailed Router for FPGAs / H. Arslan ; S. Dutt
Array Design Optimization / Session 6.1：
Reducing dTLB Energy through Dynamic Resizing / V. Delaluz ; M. Kandemir ; A. Sivasubramaniam ; M. Irwin ; N. Vijaykrishnan
Distributed Reorder Buffer Schemes for Low Power / G. Kucuk ; O. Ergin ; D. Ponomarev ; K. Ghose
Virtual Page Tag Reduction for Low-Power TLBs / P. Petrov ; A. Orailoglu
Dynamic Cluster Resizing / J. Gonzalez
Test Compaction / Session 6.2：
Independent Test Sequence Compaction through Integer Programming / P. Drineas
On Combining Pinpoint Test Set Relaxation and Run-Length Codes for Reducing Test Data Volume / S. Kajihara ; Y. Doi ; L. Li ; K. Chakrabarty
Static Test Compaction for Multiple Full-Scan Circuits
A Method to Find Don't Care Values in Test Sequences for Sequential Circuits / Y. Higami ; S. Kobayashi ; Y. Takamatsu
Invited Session: Techniques for Synthesizing into Fabrics / Session 6.3：
Simplifying SoC Design with the Customizable Control Processor Platform / C. Ogilvie ; R. Ray ; R. Devins ; M. Kautzman ; M. Hale ; R. Bergamaschi ; B. Lynch ; S. Gaur
Structured ASICs: Opportunities and Challenges / B. Zahiri
System LSI Implementation Fabrics for the Future / S. Kaptanoglu
Hardware Partitioning / Session 7.1：
Multiple-V[subscript dd] Scheduling/Allocation for Partitioned Floorplan / D. Kang ; M. Johnson
SCATOMi: Scheduling Driven Circuit Partitioning Algorithm for Multiple FPGAs Using Time-multiplexed, Off-chip, Multicasting Interconnection Architecture / Y. Kwon ; B. Park ; C. Kyung
A Study of Hardware Techniques that Dynamically Exploit Frequent Operands to Reduce Power Consumption in Integer Function Units / K. Gandhi
Energy-Aware Design and Application / Session 7.2：
KnapBind: An Area-Efficient Binding Algorithm for Low-leakage Datapaths / C. Gopalakrishnan ; S. Katkoori
A Novel Synthesis Strategy Driven by Partial Evaluation Based Circuit Reduction for Application Specific DSP Circuits / M. Mukherjee ; R. Vemuri
Power Fluctuation Minimization During Behavioral Synthesis Using ILP-Based Datapath Scheduling / S. Mohanty ; S. Chappidi
An Energy-Aware Simulation Model and Transaction Protocol for Dynamic Workload Distribution in Mobile Ad Hoc Networks / F. Ghasemi-Tari ; P. Rong
Invited Session: High-Speed Design Issues and Test Challenges / Session 7.3：
CMOS High-Speed Serial I/Os--Present and Future / M. Lee ; W. Dally ; R. Farjad-Rad ; H. Ng ; R. Senthinathan ; J. Edmondson ; J. Poulton
Fully Differential Receiver Chipset for 40 Gb/s Applications Using GaInAs/InP Single Heterojunction Bipolar Transistors / K. Kiziloglu ; S. Seetharaman ; K. Glass ; C. Bil ; H. Duong ; G. Asmanis
Paradigm Shift for Jitter and Noise in Design and Test [greater than sign]GB/s Data Communication Systems / M. Li ; J. Wilstrup
Efficiency and Reliability / Session 8.1：
Cost-Efficient Memory Architecture Design of NAND Flash Memory Embedded Systems / C. Park ; J. Seo ; D. Seo ; S. Kim ; B. Kim
Exploiting Microarchitectural Redundancy for Defect Tolerance / P. Shivakumar ; C. Moore
Reducing Multimedia Decode Power Using Feedback Control / Z. Lu ; J. Lach ; M. Stan ; K. Skadron
Novel Methods in Logic Synthesis / Session 8.2：
Structural Detection of Symmetries in Boolean Functions / G. Wang ; A. Kuehlmann
Boolean Decomposition Based on Cyclic Chains / E. Dubrova ; M. Teslenko ; J. Karlsson
SAT-Based Algorithms for Logic Minimization / S. Sapra ; M. Theobald
Communications and Context Management / Session 9.1：
Low-Density Parity-Check Decoder Architecture for High Throughput Optical Fiber Channels / A. Selvarathinam ; E. Kim ; G. Choi
Improving Branch Prediction Accuracy in Embedded Processors in the Presence of Coniext Switches / S. Pasricha ; A. Veidenbaum
Reducing Operand Transport Complexity of Superscalar Processors Using Distributed Register Files / S. Bunchua ; D. Wills ; L. Wills
xpipes: a Latency Insensitive Parameterized Network-on-chip Architecture for Multi-Processor SoCs / M. Dall'Osso ; G. Biccari ; L. Giovannini ; D. Bertozzi ; L. Benini
Board Test and Power-Aware Test / Session 9.2：
Aggressive Test Power Reduction through Test Stimuli Transformation / O. Sinanoglu
Power-Time Tradeoff in Test Scheduling for SoCs / M. Nourani ; J. Chin
Multiple Transition Model and Enhanced Boundary Scan Architecture to Test Interconnects for Signal Integrity / M. Tehranipour ; N. Ahmed
Author Index
Welcome
Organizing Committee
Program Committee
6.

図書
図書
6. 2003 Southwest Symposium on Mixed-Signal Design : SSMSD : February 23-25, 2003, Las Vegas, Nevada, U.S.A. (pbk.)
sponsored by the University of Arizona ; with technical co-sponsorship by the IEEE Circuits and Systems Society
出版情報: Piscataway, N.J. : IEEE, c2003  x, 270 p. ; 28 cm
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7.

図書
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7. SCS 2003 : International Symposium on Signals, Circuits, and Systems, July 10-11, 2003, Iași, Romania : proceedings (: set ; vol. 1 of 2 ; vol. 2 of 2)
organized by Faculty of Electronics and Telecommunications, "Gh. Asachi" Technical University of Iaşi and IEEE Romania Section CAS Chapter ; in cooperation with IEEE--CAS Society
出版情報: Piscataway, NJ : IEEE, c2003  2 v. (ii, 668 p.) ; 30 cm
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8.

図書
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8. Proceedings of the 46th IEEE International Midwest Symposium on Circuits & Systems, Cairo, Egypt, December 27th-30th 2003 (: set - v. 3)
co-sponsored by the Arab Academy for Science & Technology AAST, Egypt and the IEEE Circuits & Systems Society
出版情報: Piscataway, N.J. : IEEE Operations Center, [2003]  3 v. (liv, 1611 p.) ; 28 cm
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9.

図書
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9. Proceedings, the 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, June 30 to July 2, 2003, Calgary, Alberta, Canada
co-sponsored by IEEE Circuits and Systems Society ... [et al.] ; edited by Wael Badawy ... [et al.]
出版情報: Los Alamitos, Calif. : IEEE Computer Society, c2003  xii, 408 p. ; 28 cm.
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目次情報: 続きを見る
Message from the General Chairs
Program Committee
SoC Design Methodologies 1
Template Generation and Selection Algorithms / Y. Guo ; G. Smit ; H. Broersma ; P. Heysters
Optimized Datapath Design by Evolutionary Computation / S. Araujo ; A. Mesquita ; C. Pedroza
A Performance Evaluation Method for Optimizing Embedded Applications / M. Grunewald ; J. Niemann ; U. Ruckert
A Robust Handshake for Asynchronous System / K. Cheng ; W. Chang ; C. Tu
SoC Physical Design--Invited
Detailed Placement with Net Length Constraints / B. Halpin ; H. Sehgal ; C. Chen
Steiner Tree Construction Based on Congestion for the Global Routing Problem / L. Behjat ; A. Vannelli
Interconnection Modelling Using Distributed RLC Models / D. Kucar
Low Power SoCs
Energy Optimization in a HW/SW Tool: Design of Low Power Architecture System / P. Guitton-Ouhamou ; C. Belleudy ; M. Auguin
Incorporating Pattern Prediction Technique for Energy Efficient Filter Cache Design / K. Vivekanandarajah ; T. Srikanthan ; S. Bhattacharya ; P. Kannan
A Survey of Dynamic Power Optimization Techniques / L. Weng ; X. Wang ; B. Liu
The Design of Low-Power Fixed-Point FIR Differentiator IP Blocks / T. Fox ; A. Carreira ; L. Turner
Arithmetic Techniques
IP Watermarking Techniques: Survey and Comparison / A. Abdel-Hamid ; S. Tahar ; E. Aboulhamid
The Application of 2D Algebraic Integer Encoding to a DCT IP Core / M. Fu ; G. Jullien ; V. Dimitrov ; M. Ahmadi ; W. Miller
Transformations of Signed-Binary Number Representations for Efficient VLSI Arithmetic / B. Andreev ; E. Titlebaum ; E. Friedman
Digital Realization of Analogue Computing Elements Using Bit Streams / N. Patel ; G. Coghill ; S. Nguang
Analog and Mixed Signals 1
A High Performance Wide-Band CMOS Transimpedance Amplifier for Optical Transceivers / S. Hasan
A Design of CMOS Broadband Amplifier with High-Q Active Inductor / J. Yang ; Y. Cheng ; C. Lee
A Mixed-Mode Delay-Locked Loop for Wide-Range Operation and Multiphase Clock Generation / Y. Lo ; W. Yu ; S. Hung
A 5.8-GHz High Efficient, Low Power, Low Phase Noise CMOS VCO for IEEE 802.11a / S. Yu ; R. Liu ; W. Chen
A Low-Power Fully Differential 2.4-GHz Prescaler in 0.18[mu] CMOS Technology / S. Machan
Reconfigurable Hardware
Dynamic Hardware-Software Partitioning on Reconfigurable System-on-Chip / P. Waldeck ; N. Bergmann
Hardware Partitioning Software for Dynamically Reconfigurable SoC Design / P. Brunet ; C. Tanougast ; Y. Berviller ; S. Weber
A Catalog of Hardware Acceleration Techniques for Real-Time Reconfigurable System on Chip / J. Williams
Application Specific Coarse-Grained FPGA for Processing Element in Real-Time Parallel Particle Filters / M. Sadasivam ; S. Hong
Reconfigurable Digital Instrumentation Based on FPGA / C. Giaconia ; A. Di Stefano ; G. Capponi
Introducing an FPGA Based Genetic Algorithms in the Applications of Blind Signals Separation / H. Emam ; M. Ashour ; H. Fekry ; A. Wahdan
Digital Circuits
A High Speech Multi-Input Comparator with Clocking-Charge Based for Low-Power Systems / S. Hsia
Area Efficient Implementation of Noise Generation System / D. Kim ; M. An ; H. Chung
High-Performance Crossbar Design for System-On-Chip / P. Wijetunga
Interfacing in Microprocessor-Based Systems with a Fast Physical Addressing / M. Maamoun ; A. Benbelkacem ; D. Berkani ; A. Guessoum
SoC Applications 1
A Speech Speed Control Using Fourier Composite Approach / H. Saito ; S. Nakamura ; M. Yoneyama
Feasibility of Fixed-Point Transversal Adaptive Filters in FPGA Devices with Embedded DSP Blocks / A. Lin ; K. Gugel ; J. Principe
Low-Power FFT/IFFT VLSI Macro Cell for Scalable Broadband VDSL Modem / S. Saponara ; L. Serafini ; L. Fanucci
VLSI Implementation of Very Low-Power Motion Estimator for Scaleable Coding Systems
Modeling Issues in SoCs
A CMOS Inverter TIA Modeling with VHDL-AMS / M. Karray ; P. Desgreys ; J. Charlot
High Level Modeling and Simulation of a VDSL Modem in SystemC 2.0 - IPsim / A. Armaroli ; M. Coppola ; M. Nava
Java Based Co-Verification of Expedited Mobile Device Collaboration Using Observability / S. Aly ; A. Salem
Multi-Models Adaptive Controller for Multivariable Systems / K. Rashid
Message from the General Chairs
Program Committee
SoC Design Methodologies 1
10.

図書
図書
10. 2003 IEEE Workshop on Signal Processing Systems : SIPS 2003 : design and implementation, 27-29 August, 2003, Seoul, Korea
edited by Myung Hoon Sunwoo, Wonyong Sung
出版情報: Piscataway, N.J. : IEEE Operations Center, c2003  xii, 395 p. ; 28 cm
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