Message from the General Chair |
Steering Committee |
Program Committee |
The System View / Session 1: |
Requirements Modeling Technology: A Vision for Better, Faster, and Cheapter Systems / D. Barker |
On Upgrading Legacy Electronics Systems: Methodology, Enabling Technologies and Tools / V. Madisetti ; Y.-K. Jung ; M. Khan ; J. Kim ; T. Finnessy |
System Design Approaches / Session 2: |
Predicting the Performance of SoC Verification Technologies / G. Peterson |
Another Approach to System Level Design / Y. Veller |
Objects for Modeling Embedded Systems / J. Benzakki |
Language Extensions / Session 3: |
Automated Test Vector Generation from Rosetta Requirements / K. Ranganathan ; M. Rangarajan ; P. Alexander ; T. Regan |
Gated Clocks in RT-Synthesis and Simulation / W. Ecker ; A. Windisch ; J. Mades ; T. Schneider ; K. Yang |
Panel: Setting the Context for VHDL 200X / Stephen BaileySession 4: |
XML in the VHDL Environment / Session 5: |
HDML: Compiled VHDL in XML / M. Reshadi ; B. Gorji-Ara ; Z. Navabi |
An XML-Based Meta-Model for Design of Multiprocessor Embedded Systems / W. Cesario ; L. Gauthier ; D. Lyonnard ; G. Nicolescu ; A. Jerraya |
Using XML for Representation and Visualization of Elaborated VHDL-AMS Models / T. Karayiannis |
A Procedural Interface for VHDL / Session 6: |
Testing a Procedural Interface for Conformance to a Standard / U. Parvathy ; F. Martinolle ; S. Subramanian |
Mixed Language Design Data Access: Procedural Interface Design Considerations |
Modeling Foreign Architectures with VHPI / J. Shields |
Panel: Object Methodologies for System Design / Judith BenzakkiSession 7: |
Novel VHDL Application / Session 8: |
Induction Motor Drive System Modeled in VHDL / M. Cirstea ; A. Aounis ; M. McCormick ; P. Urwin ; L. Haydock |
A VHDL Success Story: Electric Drive System Using Neural Controller / A. Dinu ; D. Nicula |
High-Level Test Generation from VHDL Behavioral Descriptions / A. Gharebaghi |
Author Index |
Message from the General Chair |
Steering Committee |
Program Committee |