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1.

図書

図書
editors, Bernard Courtois, Thomas Wik, Yervant Zorian ; sponsored by IEEE Computer Society, IEEE Computer Society Technical Council on Test Technology, IEEE Computer Society Technical Committee on VLSI ; in cooperation with IEEE Solid-State Circuits Society
出版情報: Los Alamitos, Calif. : IEEE Computer Society, c2002  xii, 182 p. ; 28 cm
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目次情報: 続きを見る
Message from the Chairs
Conference Committee
TTTC Information
Joint Session with The Eighth IEEE International On-Line Testing Workshop (IOLTW 2002)
Plenary Session / Session A:
Keynote Address: Embedded Memory Test and Repair / A. Kablanian
Memory BIST Analysis and Application / Session B:
Defect-Oriented Analysis of Memory BIST Tests / A. Jee
A BIST-Based Solution for the Diagnosis of Embedded Memories Adopting Image Processing Techniques / D. Appello ; A. Fudoli ; V. Tancorre ; F. Corno ; M. Rebaudengo ; M. Sonza Reorda
A Scan-Bist Environment for Testing Embedded Memories / F. Karimi ; F. Lombardi
Memory ECC and Soft Errors / Session C:
Soft Error Protection for Embedded Memories / M. Nicolaidis
Fast and Compact Error Correcting Scheme for Reliable Multilevel Flash Memories / D. Rossi ; C. Metra ; B. Ricco
High Speed 15 ns 4 Mbits SRAM for Space Application / B. Coloma ; P. Delaunay ; O. Husson
High Reliability in Railway and Automotive Systems / Session D:
The YATE Fail-Safe Interface: The User's Point of View / D. Bied-Charreton ; D. Guillon ; B. Jacques
Fault Tolerant Insertion and Verification: A Case Study / A. Manzone ; D. De Costantini
Design and Implementation of a Self-Checking Scheme for Railway Trackside Systems / L. Schiano ; D. Marino
Embedded Memory Yield Enhancement / Session E:
A Silicon-Based Yield Gain Evaluation Methodology for Embedded-SRAMs with Different Redundancy Scenarios / E. Rondey ; Y. Tellier ; S. Borri
A March-Based Fault Location Algorithm for Static Random Access Memories / V. A. Vardanian ; Y. Zorian
A Simulator for Evaluating Redundancy Analysis Algorithms of Repairable Embedded Memories / R.-F. Huang ; J.-F. Li ; J.-C. Yeh ; C.-W. Wu
MTDT
Keynote Address: Challenges and Opportunities Created by the SoC Shockwave / M. Templeton
Embedded Memory Systems and Test Optimization / Session 1:
Design and Test of a 9-Port SRAM for a 100 Gb/s STS-1 Switch / R. Gibbins ; R. D. Adams ; T. Eckenrode ; M. Ouellette ; Y. Wu
Design of Embedded System for Video Coding with Logic-Enhanced DRAM and Configurable Process / T. Kaya ; I. Shirakawa ; R. Miyamoto ; T. Onoye
Adder Merged DRAM Architecture / M. Hashimoto
Memory Test Strategies / Session 2:
March SS: A Test for All Static Simple RAM Faults / S. Hamdioui ; A. J. van de Goor ; M. Rodgers
Random Testing of Multi-Port Static Random Access Memories / F. J. Meyer
Fault Modeling / Session 3:
A Fault Modeling Technique to Test Memory BIST Algorithms / R. Venkatesh ; S. Kumar ; J. Philip ; S. Shukla
Fault Modeling and Pattern-Sensitivity Testing for a Multilevel DRAM / M. Redeker ; B. F. Cockburn ; D. G. Elliott ; Y. Xiang ; S. A. Ung
An Investigation into Crosstalk Noise in DRAM Structures
Embedded Memory Compiler Tutorial / Session 4:
Keynote Address: SoC's Trends and Challenges going to 0.10 [mu]m / P. Magarshack
EPROM/EEPROM Design / Session 5:
An Automated Design Methodology for EEPROM Cell (ADE) / J. M. Portal ; L. Forli ; H. Aziza ; D. Nee
A Novel Memory Array Based on an Annular Single-Poly EPROM Cell for Use in Standard CMOS Technology / C. Dray ; P. Gendrier
A New Single Ended Sense Amplifier for Low Voltage Embedded EEPROM Non Volatile Memories / C. Papaix ; J. M. Daga
Process Technology and Reliability / Session 6:
Validated 90 nm CMOS Technology Platform with Low-k Copper Interconnects for Advanced System-on-Chip (SoC) / T. Devoivre ; M. Lunenborg ; C. Julien ; J-P. Carrere ; P. Ferreira ; W. J. Toren ; A. VandeGoor ; P. Gayet ; T. Berger ; O. Hinsinger ; P. Vannier ; Y. Trouiller ; Y. Rody ; P-J. Goirand ; R. Palla ; I. Thomas ; F. Guyader ; D. Roy ; B. Borot ; N. Planes ; S. Naudet ; F. Pico ; D. Duca ; F. Lalanne ; D. Heslinga ; M. Haond
Converting an Embedded Low-Power SRAM from Bulk to PD-SOI / M. R. Casu ; P. Flatresse
Decreasing EEPROM Programming Bias with Negative Voltage, Reliability Impact / R. Laffont ; J. Razafindramora ; P. Canet ; R. Bouchakour ; J. M. Mirabel
Advanced Memory Technologies Panel / Session 7:
Panel on Advanced Embedded Memory Technologies
Author Index
Message from the Chairs
Conference Committee
TTTC Information
2.

図書

図書
sponsored by IEEE Computer Society and the Philadelphia Section of the IEEE
出版情報: New York : Institute of Electrical and Electronics Engineers, c1977  x, 198 p. ; 28 cm
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3.

図書

図書
edited by R. Rajsuman and T. Wik ; sponsored by IEEE Computer Society, IEEE Computer Society Test Technology Technical Council, IEEE Computer Society Technical Committee on VLSI ; in cooperation with IEEE Solid-State Circuits Society
出版情報: Los Alamitos, Calif. : IEEE Computer Society, c2004  vii, 121 p. ; 28 cm
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