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1.

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1. Proceedings of The 26th International Symposium on Computer Architecture , May 2-4, 1999, Atlanta, Georgia (: softbound ; : casebound ; : microfiche)
sponsored by IEEE Computer Society TCCA, ACM SIGARCH ; with support from The Georgia Institute of Technology
出版情報: Los Alamitos, CA : IEEE Computer Society, c1999  xii, 317 p. ; 28 cm
シリーズ名: Computer architecture news ; vol. 27, no. 2 May 1999 special issue
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2.

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2. Proceedings, 1997 International Conference on Parallel Architectures and Compilation Techniques, San Francisco, Calfornia, November 10-14, 1997
sponsors IFIP WG 10.3, IEEE Computer Society, ACM SIGARCH
出版情報: Los Alamitos, Calif. : IEEE Computer Society Press, c1997  ix, 319 p. ; 28 cm
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3.

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3. The 25th Annual International Symposium on Computer Architecture conference proceedings, June 27-July 1, 1998, Barcelona, Spain (: softbound ; : casebound ; : microfiche)
sponsored by ACM SIGARCH, IEEE Computer Society, TCCA ; with support of CICYT and CIRIT ; in cooperation with UPC
出版情報: Los Alamitos, CA : IEEE Computer Society, c1998  xiii, 394 p. ; 28 cm
シリーズ名: Computer architecture news ; special issue v. 26, no. 3 June 1998
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4.

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4. Proceedings of the 1996 Conference on Parallel Architectures and Compilation Techniques (PACT '96), October 20-23, 1996, Boston, Massachusetts (IEEE order plan ; microfiche)
sponsored by The IEEE Computer Society Technical Committee on Computer Architecture, IFIP WG 10.3 (Concurrent Systems), Association for Computing Machinery SIGARCH
出版情報: Los Alamitos, Calif. : IEEE Computer Society Press, c1996  xiv, 304 p. ; 28 cm
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5.

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5. Proceedings : the 23rd Annual International Symposium on Computer Architecture : ISCA '23 proceedings, May 22-24, 1996, Philadelphia, Pennsylvania (: softbound ; : casebound ; : microfiche)
sponsored by ACM SIGARCH, IEEE Computer Society, TCCA
出版情報: New York : ACM Press, c1996  xii, 318 p. ; 28 cm
シリーズ名: Computer architecture news ; v. 24, no. 2
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6.

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6. The 18th Annual International Symposium on Computer Architecture, May 27-30, 1991, Toronto, Canada : proceedings (: case ; : pbk ; : microfiche)
International Symposium on Computer Architecture ; SIGARCH ; Institute of Electrical and Electronics Engineers ; IEEE Computer Society. Technical Committee on Computer Architecture
出版情報: New York : ACM, c1991  xv, 399 p. ; 28 cm
シリーズ名: Computer architecture news ; v. 19, no. 3
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7.

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図書
7. Proceedings, Supercomputing '91 : Albuquerque, New Mexico, November 18-22, 1991 (: case - : ACM)
sponsored by the ACM Special Interest Group on Computer Architecture, the IEEE Computer Society Technical Committees on Supercomputing Applications and Computer Architecture ; in cooperation with Lawrence Livermore Laboratory ... [et al.]
出版情報: Los Alamitos, Calif. : IEEE Computer Society Press, c1991  xxiii, 917 p. ; 29 cm
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8.

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8. Proceedings : the 19th Annual International Symposium on Computer Architecture, May 19-21, 1992, Gold Coast, Australia (: soft - : case)
[sponsored by Association for Computing Machinery, SIGARCH, IEEE Computer Society, Technical Committee on Computer Architecture]
出版情報: New York : ACM, c1992  xvi, 439 p. ; 28 cm
シリーズ名: Computer architecture news ; v. 20, no. 2
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9.

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9. Proceedings, Supercomputing '92 : Minneapolis, Minnesota, November 16-20, 1992 (: paper - : ACM)
sponsored by IEEE Computer Society Technical Committee on Supercomputing Applications, IEEE Computer Society Technical Committee on Computer Architecture, ACM SIGARCH
出版情報: Los Alamitos, Calif. : IEEE Computer Society Press, c1992  xxiv, 848 p. ; 29 cm
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10.

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10. The 17th Annual International Symposium on Computer Architecture, May 28-31, 1990, Seattle, Washington : proceedings (pbk. ; case)
[sponsored by IEEE Computer Society Technical Committee on Computer Architecture, Association for Computing Machinery SIGARCH, the Institute of Electrical and Electronics Engineers]
出版情報: Washington, D.C. : Computer Society Press of the IEEE, c1990  xv, 378 p. ; 28 cm
シリーズ名: Computer architecture news ; v. 18, no. 2
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11.

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11. The 15th Annual International Symposium on Computer Architecture, May 30-June 2, 1988, Honolulu, Hawaii : conference proceedings (: pbk. ; : microfiche ; : case)
sponsored by IEEE Computer Society Technical Committee on Computer Architecture, Association for Computing Machinery SIGARCH, the Institute of Electrical and Electronics Engineers
出版情報: Washington, D.C. : Computer Society Press of the IEEE, c1988  xi, 461 p. ; 28 cm
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12.

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12. The 16th Annual International Symposium on Computer Architecture (: pbk. ; : microfiche ; : case)
[sponsored by IEEE Computer Society Technical Committee on Computer Architecture, Association for Computing Machinery SIGARCH, the Institute of Electrical and Electronics, Engineers]
出版情報: Washington, D.C. : IEEE Computer Society Press, c1989  xvii, 426 p. ; 28 cm
シリーズ名: Computer architecture news ; v. 17, no. 3
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13.

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13. Proceedings, Supercomputing '93 : Portland, Oregon, November 15-19 (: paper ; : micro. ; : case.)
sponsored by IEEE Computer Society Technical Committees on Supercomputing Applications and Computer Architecture, ACM SIGARCH
出版情報: Los Alamitos, Calif. : IEEE Computer Society Press, c1993  xxii, 935 p. ; 29 cm
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14.

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14. Proceedings : the 20th Annual International Symposium on Computer Architecture, May 16-19, 1993, San Diego, California (: paper - : ACM hc.)
sponsored by IEEE Computer Society, Technical Committee on Computer Architecture, Association for Computing Machinery, SIGARCH
出版情報: Los Alamitos : IEEE Computer Society Press, c1993  xii, 361 p. ; 28 cm
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15.

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15. Proceedings, 10th International Symposium on Modeling, Analysis, and Simulation of Computer and Telecommunications Systems : MOSCOTS 2002, 11-16 October 2002, Fort Worth, Texas
edited by A. Boukerche, S. K. Das, and S. Majumdar ; sponsored by IEEE Computer Society Technical Committee on Computer Architecture, IEEE Computer Society Technical Committee on Simulation ; in cooperation with ACM SIGSIM, ACM SIGARCH ; supported by University of North Texas, University of Texas at Arlington
出版情報: Los Alamitos, Calif. : IEEE Computer Society, c2002  xvi, 521 p. ; 28 cm
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16.

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16. Proceedings of the 27th International Symposium on Computer Architecture, Jun 12-14, 2000, Vancouver, British Columbia, Canada (: case ; ACM)
sponsored by IEEE Computer Society TCCA, ACM SIGARCH
出版情報: Los Alamitos, CA : IEEE Computer Society, c2000 , New York, NY : the Association for Computing Machinery, c2000  vi, 328 p. ; 28 cm
シリーズ名: Computer architecture news ; v.28, no.2, May 2000
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17.

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17. Proceedings : 29th Annual International Symposium on Computer Architecture, 25-29 May 2002, Anchorage, Alaska
sponsored by IEEE TCCA, ACM SIGARCH
出版情報: Los Alamitos, Calif. : IEEE Computer Society, c2002  xv, 331 p. ; 28 cm
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目次情報: 続きを見る
Message from the General Chair
Message from the Program Chair
Organizing Committee
Steering Committee
Program Committee
Reviewers
Welcoming Remarks
Keynote Address / Burton J. Smith
Processor Pipelines / Session 1：
The Optimum Pipeline Depth for a Microprocessor / A. Hartstein ; T. Puzak
The Optimal Logic Depth per Pipeline Stage Is 6 to 8 FO4 Inverter Delays / M. Hrishikesh ; N. Jouppi ; K. Farkas ; D. Burger ; S. Keckler ; P. Shivakumar
Increasing Processor Performance by Implementing Deeper Pipelines / E. Sprangle ; D. Carmean
Processor Scheduling / Session 2：
Efficient Dynamic Scheduling through Tag Elimination / D. Ernst ; T. Austin
Slack: Maximizing Performance under Technological Constraints / B. Fields ; R. Bodik ; M. Hill
A Large, Fast Instruction Window for Tolerating Cache Misses / A. Lebeck ; J. Koppanalil ; T. Li ; J. Patwardhan ; E. Rotenberg
An Instruction Set and Microarchitecture for Instruction Level Distributed Processing / H.-S. Kim ; J. Smith
Safety and Reliability / Robert P. ColwellSession 3：
Transient-Fault Recovery Using Simultaneous Multithreading / T. Vijaykumar ; I. Pomeranz ; K. Cheng
Detailed Design and Evaluation of Redundant Multithreading Alternatives / S. Mukherjee ; M. Kontz ; S. Reinhardt
ReVive: Cost-Effective Architectural Support for Rollback Recovery in Shared-Memory Multiprocessors / M. Prvulovic ; Z. Zhang ; J. Torrellas
SafetyNet: Improving the Availability of Shared Memory Multiprocessors with Global Checkpoint/Recovery / D. Sorin ; M. Martin ; D. Wood
Power Aware Architecture / Session 4：
Dynamic Fine-Grain Leakage Reduction Using Leakage-Biased Bitlines / S. Heo ; K. Barr ; M. Hampton ; K. Asanovic
Drowsy Caches: Simple Techniques for Reducing Leakage Power / K. Flautner ; N. Kim ; S. Martin ; D. Blaauw ; T. Mudge
Power and Performance Evaluation of Globally Asynchronous Locally Synchronous Processors / A. Iyer ; D. Marculescu
Memory Systems / Session 5：
Using a User-Level Memory Thread for Correlation Prefetching / Y. Solihin ; J. Lee
Avoiding Initialization Misses to the Heap / J. Lewis ; B. Black ; M. Lipasti
Going the Distance for TLB Prefetching: An Application-Driven Study / G. Kandiraju ; A. Sivasubramaniam
Dynamic Optimization / Session 6：
Timekeeping in the Memory System: Predicting and Optimizing Memory Behavior / Z. Hu ; S. Kaxiras ; M. Martonosi
Implementing Optimizations at Decode Time / I. Kim
Managing Multi-configuration Hardware via Dynamic Working Set Analysis / A. Dhodapkar
Data and Storage Networks / Session 7：
Queue Pair IP: A Hybrid Architecture for System Area Networks / P. Buonadonna ; D. Culler
Experiences with VI Communication for Database Storage / Y. Zhou ; A. Bilas ; S. Jagannathan ; C. Dubnicki ; J. Philbin ; K. Li
Vector Architectures / Session 8：
Speculative Dynamic Vectorization / A. Pajuelo ; A. Gonzalez ; M. Valero
Tarantula: A Vector Extension to the Alpha Architecture / R. Espasa ; F. Ardanaz ; J. Emer ; S. Felix ; J. Gago ; R. Gramunt ; I. Hernandez ; T. Juan ; G. Lowney ; M. Mattina ; A. Seznec
Supporting Deep Speculation / Session 9：
Design Tradeoffs for the Alpha EV8 Conditional Branch Predictor / V. Krishnan ; Y. Sazeides
Difficult-Path Branch Prediction Using Subordinate Microthreads / R. Chappell ; F. Tseng ; A. Yoaz ; Y. Patt
A Scalable Instruction Queue Design Using Dependence Chains / S. Raasch ; N. Binkert
Author Index
Message from the General Chair
Message from the Program Chair
Organizing Committee
18.

図書
図書
18. Proceedings, 2000 International Conference on Parallel Architectures and Compilation Techniques, October 15-19, 2000, Philadelphia, Pennsylvania (: pbk)
sponsored by IEEE Technical Committee on Computer Architecture, IEEE Technical Committee on Parallel Processing ; in cooperation with ACM SIGARCH, IBM, Intel, SGI
出版情報: Los Alamitos, Calif. : IEEE Computer Society, c2000  xi, 309 p. ; 28 cm
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目次情報: 続きを見る
Introduction
Organizing Committee
Program Committee
Reviewers
Keynote
"New Challenges in Microarchitecture and Compiler Design" / Fred Pollack
Register Allocation and Analysis
Register Queues: A New Hardware/Software Approach To Efficient Software Pipelining / M. Smelyanskiy ; G. Tyson ; E. Davidson
Global Register Partitioning / J. Hiser ; S. Carr ; P. Sweany
Region Formation Analysis with Demand-Driven Inlining for Region-Based Optimization / T. Way ; B. Breech ; L. Pollock
Architectural Design
aSOC: A Scalable, Single-Chip Communications Architecture / J. Liang ; S. Swaminathan ; R. Tessier
Address Partitioning in DSM Clusters with Parallel Coherence Controllers / I. Pragaspathy ; B. Falsafi
Custom Wide Counterflow Pipelines for High-Performance Embedded Applications / B. Childers ; J. Davidson
Optimizations and Opportunities
A Lightweight Algorithm for Dynamic If-Conversion during Dynamic Optimization / K. Hazelwood ; T. Conte
Exploring the Limits of Sub-Word Level Parallelism / K. Scott
The Dynamic Trace Memoization Reuse Technique / A. da Costa ; F. Franca ; E. Filho
Exploring Sub-Block Value Reuse for Superscalar Processors / J. Huang ; D. Lilja
"Dynamic Optimization: An Online Opportunity" / Michael Smith
High Performance Memory Techniques
Hiding Relaxed Memory Consistency with Compilers / J. Lee ; D. Padua
Neighborhood Prefetching on Multiprocessors Using Instruction History / D. Koppelman
Characterization of Silent Stores / G. Bell ; K. Lepak ; M. Lipasti
Speculation and Prediction
On Some Implementation Issues for Value Prediction on Wide-Issue ILP Processors / S-J. Lee ; P-C. Yew
A Unified Compiler Framework for Control and Data Speculation / R. Ju ; K. Nomura ; U. Mahadevan ; L-C. Wu
Applying Data Speculation in Modulo Scheduled Loops / R. Hank
Branch Prediction
Branch Prediction in Multi-Threaded Processors / J. Gummaraju ; M. Franklin
The Effect of Code Reordering on Branch Prediction / A. Ramirez ; J. Larriba-Pey ; M. Valero
A Taxonomy of Branch Mispredictions, and Alloyed Prediction as a Robust Solution to Wrong-History Mispredictions / K. Skadron ; M. Martonosi ; D. Clark
Dynamic Branch Prediction for a VLIW Processor / J. Hoogerbrugge
"Blue Gene" / Monty Denneau
Parallel Computation
Fine Grained Multithreading with Process Calculi / L. Lopes ; F. Silva ; V. Vasconcelos
Data Relation Vectors: A New Abstraction for Data Optimizations / M. Kandemir ; J. Ramanujam
Combined Selection of Tile Sizes and Unroll Factors Using Iterative Compilation / T. Kisuki ; P. Knijnenburg ; M. O'Boyle
Applications
Faster FFTs via Architecture-Cognizance / K. Gatlin ; L. Carter
Hybrid Parallel Circuit Simulation Approaches / E. Naroska ; R-J. Shang ; F. Lai ; U. Schwiegelshohn
Multithreaded Programming of PC Clusters / M. Schulz
Instruction Scheduling
A Fast Algorithm for Scheduling Instructions with Deadline Constraints on RISC Processors / H. Wu ; J. Jaffar ; R. Yap
Instruction Scheduling for Clustered VLIW DSPs / R. Leupers
Efficient Backtracking Instruction Schedulers / S. Abraham ; W. Meleis ; I. Baev
Author Index
Introduction
Organizing Committee
Program Committee
19.

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図書
19. Proceedings, 32nd International Symposium on Computer Architecture : Madison, Wisconsin, June 4-8, 2005
sponsored by IEEE Computer Society Technical Committee on Computer Architecture, ACM SIGARCH
出版情報: Los Alamitos, Calif. : IEEE Computer Society, c2005  xviii, 557 p. ; 27 cm.
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20.

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20. Proceedings, 18th International Parallel and Distributed Processing Symposium : Santa Fe, New Mexico, April 26-30, 2004
sponsored by IEEE Computer Society Technical Committee on Parallel Processing ; in cooperation with IEEE Computer Society Technical Committee on Computer Architecture, IEEE Computer Society Technical Committee on Distributed Processing, ACM SIGARCH
出版情報: Los Alamitos, Calif. : IEEE Computer Society, c2004  lvi, 289 p. ; 28 cm.
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目次情報: 続きを見る
Heterogeneous Computing Workshop--HCW / Workshop 1：
Workshop Introduction
Message from the Steering Committee Chair
Message from the General Chair
Message from the Program Chair
IQ-Services: Resource-Aware Middleware for Heterogeneous Applications / Z. Cai ; G. Eisenhauer ; C. Poellabauer ; K. Schwan ; M. Wolf
Data Partitioning with a Realistic Performance Model of Networks of Heterogeneous Computers / A. Lastovetsky ; R. Reddy
Multisite Resource Selection and Scheduling Algorithm on Computational Grid / W. Zhang ; B. Fang ; H. He ; H. Zhang ; M. Hu
An Execution-Time Estimation Model for Heterogeneous Clusters / Y. Kishimoto ; S. Ichikawa
A Comparison of Static QoS-Based Scheduling Heuristics for a Meta-Task with Multiple QoS Dimensions in Heterogeneous Computing / K. Golconda ; F. Ozguner ; A. Dogan
Capabilities-Based Query Planning in Mediator Systems / J. Tang ; J. Song ; W. Xiao
A High Performance, Low Complexity Algorithm for Compile-Time Task Scheduling in Heterogeneous Systems / T. Hagras ; J. Janecek
Metainformation and Workflow Management for Solving Complex Problems in Grid Environments / H. Yu ; X. Bai ; G. Wang ; Y. Ji ; D. Marinescu
Evaluation of an Unfair Decider Mechanism for the Self-Tuning dynP Job Scheduler / A. Streit
A Framework for Heterogeneous Middleware Security / S. Foley ; T. Quillinan ; M. O'Connor ; B. Mulcahy ; J. Morrison
Improving Performance of Java Applications Using a Coprocessor / F. Li ; M. Kandemir
Automatic Deployment for Hierarchical Network Enabled Servers / E. Caron ; P. Chouhan ; A. Legrand
Static Mapping of Subtasks in a Heterogeneous Ad Hoc Grid Environment / S. Shivle ; r. Castain ; H. Siegel ; A. Maciejewski ; T. Banka ; K. Chindam ; S. Dussinger ; P. Pichumani ; P. Satyasekaran ; W. Saylor ; D. Sendek ; J. Sousa ; J. Sridharan ; P. Sugavanam ; J. Velazco
Performance Improvement in Web Services Invocation Framework / M. Migliardi ; R. Podesta
Application of Lagrangian Receding Horizon Techniques to Resource Management in Ad Hoc Grid Environments / R. Castain
A Hybrid Heuristic for DAG Scheduling on Heterogeneous Systems / R. Sakellariou ; H. Zhao
Parallel Implementation of Strassen's Matrix Multiplication Algorithm for Heterogeneous Clusters / Y. Ohtaki ; D. Takahashi ; T. Boku ; M. Sato
Latency Tolerance through Parallelization of Time in Scientific Applications / A. Srinivasan ; N. Chandra
Performance and Client Heterogeneity in Service-Based Metacomputing / T. Wrzosek ; D. Kurzyniec ; V. Sunderam
Workshop on Parallel and Distributed Real-Time Systems--WPDRTS / Workshop 2：
Resource Management of Highly Configurable Tasks / J. Hansen ; S. Ghosh ; R. Rajkumar ; J. Lehoczky
Quality-Based Adaptive Resource Management Architecture (QARMA): A CORBA Resource Management Service / D. Fleeman ; M. Gillen ; A. Lenharth ; M. Delaney ; L. Welch ; D. Juedes ; C. Liu
Heuristic Resource Allocation Algorithms for Maximizing Allowable Workload in Dynamic, Distributed Real-Time Systems / F. Drews
Robust Partitioning for Reliable Real-Time Systems / R. Seyer ; C. Siemers ; R. Falsett ; K. Ecker ; H. Richter
Iterative Integer Programming Formuation for Robust Resource Allocation in Dynamic Real-Time Systems / S. Gertphol ; V. Prasanna
Time-sensitive Computation of Aggregate Functions over Distributed Imprecise Data / Q. Han ; M. Nguyen ; S. Irani ; N. Venkatasubramanian
Pfair Scheduling of Periodic Tasks with Allocation Constraints on Multiple Processors / D. Liu ; Y. Lee
Improved Conditions for Bounded Tardiness under EPDF Fair Multiprocessor Scheduling / U. Devi ; J. Anderson
Group Scheduling in Systems Software / M. Frisbie ; D. Niehaus ; V. Subramonian ; C. Gill
Cost Efficient Synthesis of Real-Time Systems upon Heterogeneous Multiprocessor Platforms / S. Baruah
Synthesis of Pipelined Systems for the Contemporaneous Execution of Periodic and Aperiodic Tasks with Hard Real-Time Constraints / P. Palazzari ; L. Baldini ; M. Coli
Design of a Real-Time CORBA Event Service Customised for the CAN Bus / R. Finocchiaro ; S. Lankes ; A. Jabs
Message Routing in Multi-segment FTT Networks: The Isochronous Approach / P. Pedreiras ; L. Almeida
Software Organization to Facilitate Dynamic Processor Scheduling / R. Clark ; E. Jensen ; N. Rouquette
Utility-Function Based Resource Allocation for Adaptable Applications in Dynamic, Distributed Real-Time Systems / A. Bruening ; M. Hoefer
Time-Utility Scheduling and Provably Correct Critical Computer-Based Systems / G. Le Lann
On the Joint Utility Accrual Model / H. Wu ; B. Ravindran
CARUSO--An Approach Towards a Network of Low Power Autonomic Systems on Chips for Embedded Real-time Applications / U. Brinkschulte ; T. Ungerer ; J. Becker
Worst Case Execution Time Prediction by Static Program Analysis / C. Ferdinand
On Static WCET Analysis vs. Run-time Monitoring of Execution Time / C. Cavanaugh
Timing Analysis: In Search of Multiple Paradigms / F. Mueller
The Case for Dynamic Real-time Task Timing in Modern Real-Time Systems / S. Brandt
Real-Time Communication for Industrial Embedded Systems Using Switched Ethernet / H. Hoang
Managing Communication in Integrated Modular Architectures / S. Gopalakrishnan
Pulse-modulated Radar Display Processor on a Chip / T. Darwich
Peer-to-Peer Reputations / P. Dewan
A Utility-Based Approach to Scheduling Multimedia Streams in Peer-to-Peer Systems / F. Chen
Increasing Object Availability in Peer-to-Peer Systems / M. Ramanathan
Reconfigurable Architectures Workshop--RAW / Workshop 3：
Of Gates and Wires / P. Lysaght ; D. Levi
A Parallel Architecture for Secure FPGA Symmetric Encryption / E. Swankoski ; R. Brooks ; V. Narayanan ; M. Irwin
Tuning Reconfigurable Microarchitectures for Power Efficiency / A. Dhodapkar ; J. Smith
A Reconfigurable Tag Computation Architecture for Terabit Packet Scheduling / S. Sezer ; C. Toal ; E. Garcia ; V. Stewart
A New Approach for On-line Placement on Reconfigurable Devices / A. Ahmadinia ; C. Bobda ; M. Bednara ; J. Teich
Improving Java Performance Using Dynamic Method Migration on FPGAs / E. Lattanzi ; A. Gayasen ; L. Benini ; A. Bogliolo
An FPGA Run-Time System for Dynamical On-Demand Reconfiguration / M. Ullmann ; M. Huebner ; B. Grimm
Models and Reconfiguration Problems for Multi Task Hyperreconfigurable Architectures / S. Lange ; M. Middendorf
Runtime Reconfigurable Interfaces--The RTR-IFB Approach / S. Ihmor ; W. Hardt
System-Level Parallelism and Throughput Optimization in Designing Reconfigurable Computing Applications / E. El-Araby ; M. Taher ; K. Gaj ; T. El-Ghazawi ; D. Caliga ; N. Alexandridis
Embedded Software Integration for Coarse-grain Reconfigurable Systems / P. Schaumont ; K. Sakiyama ; A. Hodjat ; I. Verbauwhede
An Integrated FPGA Design Framework: Custom Designed FPGA Platform and Application Mapping Toolset Development / V. Kalenteridis ; H. Pournara ; K. Siozios ; K. Tatas ; G. Koytroympezis ; I. Pappas ; S. Nikolaidis ; S. Siskos ; D. Soudris ; A. Thanailakis
Real-time Configuration Code Decompression for Dynamic FPGA Self-Reconfiguration / F. Weissel
Forward-looking Macro Generation and Relational Placement During High Level Synthesis to FPGAs / R. Huang ; R. Vemuri
Integrated Modeling and Generation of a Reconfigurable Network-on-Chip / D. Ching
Dynamic Reconfiguration of Distributed Arithmetic Controllers: Design Space Exploration and Trade-off Analysis / K. Danne
Hardware Assisted Two Dimensional Ultra Fast Placement / M. Handa
System-on-Programmable-Chip Approach Enabling Online Fine-Grained 1D-Placement / H. Kalte ; M. Porrmann ; U. Ruckert
Non-Contiguous Linear Placement for Reconfigurable Fabrics / C. Ababei ; K. Bazargan
Impacting Education Using FPGAs / D. Bouldin
Developing Large-Scale Field-Programmable Analog Arrays / T. Hall ; C. Twigg ; P. Hasler ; D. Anderson
Dynamically Reconfigurable Neuron Architecture for the Implementation of Self-Organizing Learning Array / J. Starzyk ; Y. Guo ; Z. Zhu
Designing a Runtime Reconfigurable Processor for General Purpose Applications / A. Niyonkuru ; H. Zeidler
A Parallel Architecture for Fast Computation of Elliptic Curve Scalar Multiplication over GF(2[superscript m]) / N. Saqib ; F. Rodriguez-Henriquez ; A. Diaz-Perez
Adaptive Processor: A Model of Stream Processing / S. Takano
Probabilistic Analysis of Fault Tolerance of FPGA Switch Block Array / J. Huang ; M. Tahoori ; F. Lombardi
Dynamic Reconfiguration for Management of Radiation-Induced Faults in FPGAs / M. Gokhale ; P. Graham ; E. Johnson ; N. Rollins ; M. Wirthlin
Dynamically Configurable Security for SRAM FPGA Bitstreams / L. Bossuet ; G. Gogniat ; W. Burleson
RECASTER: Synthesis of Fault-Tolerant Embedded Systems Based on Dynamically Reconfigurable FPGAs / C. da Silva ; A. Tokarnia
Adaptive System Architectures / K. Waldschmidt
Implementation of a HiperLAN/2 Receiver on the Reconfigurable Montium Architecture / P. Heysters ; G. Rauwerda ; G. Smit
Mapping of Regular Nested Loop Programs to Coarse-grained Reconfigurable Arrays--Constraints and Methodology / F. Hannig ; H. Dutta
Overlapping Memory Operations with Circuit Evaluation in Reconfigurable Computing / Y. Ben-Asher ; D. Citron ; G. Haber
A High-Performance and Energy-efficient Architecture for Floating-point Based LU Decomposition on FPGAs / G. Govindu ; S. Choi ; V. Daga ; S. Gangadharpalli ; V. Sridhar
Analysis of High-performance Floating-point Arithmetic on FPGAs / L. Zhuo
Synthesizable Reconfigurable Array Targeting Distributed Arithmetic for System-on-Chip Applications / S. Khawam ; T. Arslanm ; F. Westall
Pipelined Multipliers for Reconfigurable Hardware / M. Myjak ; J. Delgado-Frias
Functional Programming for Reconfigurable Computing / A. Strelzoff
A Dynamically-Reconfigurable Image Recognition Processor / K. Maruo ; M. Ichikawa ; N. Miyamoto ; L. Karnan ; T. Yamaguchi ; K. Kotani ; T. Ohmi
MemMap-pd: Performance Driven Technology Mapping Algorithm for FPGAs with Embedded Memory Arrays / M. Kumar ; B. Jayaram ; R. Manimegalai ; V. Kamakoti
Heterogeneous Computing Workshop--HCW / Workshop 1：
Workshop Introduction
Message from the Steering Committee Chair
21.

図書
図書
21. Proceedings, 31st Annual International Symposium on Computer Architecture, München, Germany, June 19-23, 2004
IEEE Computer Society TCCA, ACM SIGARCH
出版情報: Los Alamitos, Calif. : IEEE Computer Society, c2004  xiv, 388 p. ; 28 cm
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目次情報: 続きを見る
General Co-Chairs' Message
Program Chair's Message
Committees
Reviewers
Keynote 1
Computer Architecture: Challenges and Opportunities for the Next Decade / Tilak Agerwala
Architecture Evaluations / Session 1：
Evaluation of the Raw Microprocessor: An Exposed-Wire-Delay Architecture for ILP and Streams / M. Taylor ; W. Lee ; J. Miller ; D. Wentzlaff ; B. Greenwald ; V. Strumpen ; N. Shnidman ; I. Bratt ; H. Hoffmann ; P. Johnson ; J. Kim ; A. Saraf ; J. Psota ; M. Frank|cS. Amarasinghe ; A. Agarwal
Evaluating the Imagine Stream Architecture / J. Ahn ; W. Dally ; B. Khailany ; U. Kapasi ; A. Das
Field-testing IMPACT EPIC Research Results in Itanium 2 / J. Sias ; S. Ueng ; G. Kent ; I. Steiner ; E. Nystrom ; W. Hwu
Parallelism in Microarchitectures / Session 2A：
Wire Delay is Not a Problem for SMT (In the Near Future) / Z. Chishti ; T. Vijaykumar
The Vector-Thread Architecture / R. Krashinsky ; C. Batten ; S. Gerding ; M. Hampton ; B. Pharris ; J. Casper ; K. Asanovic
Single-ISA Heterogeneous Multi-Core Architectures for Multithreaded Workload Performance / R. Kumar ; D. Tullsen ; P. Ranganathan ; N. Jouppi ; K. Farkas
Microarchitecture Optimizations for Exploiting Memory-Level Parallelism / Y. Chou ; B. Fahs ; S. Abraham
Memory Consistency / Session 2B：
Memory Ordering: A Value-Based Approach / H. Cain ; M. Lipasti
Transactional Memory Coherence and Consistency / L. Hammond ; V. Wong ; M. Chen ; B. Hertzberg ; J. Davis ; B. Carlstrom ; M. Prabhu ; H. Wijaya ; C. Kozyrakis ; K. Olukotun
TSOtool: A Program for Verifying Memory Systems Using the Memory Consistency Model / S. Hangal ; D. Vahia ; C. Manovit ; J. Lu ; S. Narayanan
SMTp: An Architecture for Next-generation Scalable Multi-threading / M. Chaudhuri ; M. Heinrich
Panel: Supporting ILP in Tiled Architectures: Wasted Effort, or a Good Idea?
Keynote 2
High Performance Throughput Computing / Marc Tremblay ; Sun Microsystems
Power and Energy / Session 3：
A Formal Approach to Frequent Energy Adaptations for Multimedia Applications / C. Hughes ; S. Adve
Synchroscalar: A Multiple Clock Domain, Power-Aware, Tile-Based Embedded Processor / J. Oliver ; R. Rao ; P. Sultana ; J. Crandall ; E. Czernikowski ; L. Jones ; D. Franklin ; V. Akella ; F. Chong
Power Awareness through Selective Dynamically Optimized Traces / R. Rosner ; Y. Almog ; M. Moffie ; N. Schwartz ; A. Mendelson
Interconnect and I/O / Session 3B：
X-RAY: A Non-Invasive Exclusive Caching Mechanism for RAIDs / L. Bairavasundaram ; M. Sivathanu ; A. Arpaci-Dusseau ; R. Arpaci-Dusseau
Low-Latency Virtual-Channel Routers for On-Chip Networks / R. Mullins ; A. West ; S. Moore
Immunet: A Cheap and Robust Fault-Tolerant Packet Routing Mechanism / V. Puente ; J. Gregorio ; F. Vallejo ; R. Beivide
Compression and Debugging / Session 4A：
Adaptive Cache Compression for High-Performance Processors / A. Alameldeen ; D. Wood
iWatcher: Efficient Architectural Support for Software Debugging / P. Zhou ; F. Qin ; W. Liu ; Y. Zhou ; J. Torrellas
Superscalars / Session 4B：
From Sequences of Dependent Instructions to Functions: An Approach for Improving Performance without ILP or Speculation / S. Yehia ; O. Temam
Prophet/Critic Hybrid Branch Prediction / A. Falcon ; J. Stark ; A. Ramirez ; K. Lai ; M. Valero
Support for Reliability / Session 5A：
Techniques to Reduce the Soft Error Rate of a High-Performance Microprocessor / C. Weaver ; J. Emer ; S. Mukherjee ; S. Reinhardt
The Case for Lifetime Reliability-Aware Microprocessors / J. Srinivasan ; P. Bose ; J. Rivers
Exploiting Resonant Behavior to Reduce Inductive Noise / M. Powell
Register File / Session 5B：
Use-Based Register Caching with Decoupled Indexing / J. Butts ; G. Sohi
A Content Aware Integer File Organization / R. Gonzalez ; A. Cristal ; D. Ortega ; A. Veidenbaum
Physical Register Inlining / B. Mestan ; E. Gunadi
Performance Methodologies / Session 6A：
A First-Order Superscalar Processor Model / T. Karkhanis ; J. Smith
Control Flow Modeling in Statistical Simulation for Accurate and Efficient Processor Design Studies / L. Eckhout ; R. Bell ; B. Stougie ; K. De Bosschere ; L. John
Microarchitectural Concepts / Session 6B：
Extended Split-Issue: Enabling Flexibility in the Hardware Implementation of NUAL VLIW DSPs / B. Iyer ; S. Srinivasan ; B. Jacob
A Complexity-Effective Approach to ALU Bandwidth Enhancement for Instruction-Level Temporal Redundancy / A. Parashar ; S. Gurumurthi ; A. Sivasubramaniam
Author Index
General Co-Chairs' Message
Program Chair's Message
Committees
22.

図書
図書
22. Proceedings, ninth International Symposium on Modeling, Analysis, and Simulation of Computer and Telecommunication Systems, 15-18 August 2001, Cincinnati, Ohio
sponsored by IEEE Computer Society Technical Committee on Simulation, IEEE Computer Society Technical Committee on Computer Architecture ; in cooperation with ACM SIGSIM, ACM SIGARCH
出版情報: Los Alamitos, Calif. : IEEE Computer Society, c2001  xii, 432 p. ; 28 cm
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Message from the General Chair
Message from the Program Chair
Conference Organizers
Program Committee
Opening Remarks / Dr. Anthony Perzigian
Keynote Speech
High-Volume Web Servers: Traffic Patterns, Performance Implications and Resource Management / Dr. Mark S. Squillante
Real Time Systems
Specification and Validation of a Real-Time Parallel Kernel Using LOTOS / C. de Farias ; L. Pires ; W. de Souza ; C. Moron
Performance Analysis of Pools in Soft Real-Time Design Architectures / C. Juiz ; R. Puigjaner ; H. Perros
Dynamic Multipath Routing (DMPR): An Approach to Improve Resource Utilization in Networks for Real-Time Traffic / S. De ; S. Das
Parallel and Distributed Simulation
An Evaluation of Grouping Techniques for State Dissemination in Networked Multi-User Games / L. Zou ; M. Ammar ; C. Diot
Effect of Event Orderings on Memory Requirement in Parallel Simulation / Y. Teo ; B. Onggo ; S. Tay
Time-Parallel Algorithms for Simulation of Multiple Access Protocols / K. Jones
Capacity Planning
Optimal Resource Assignment in Internet Data Centers / X. Zhu ; S. Singhal
Traffic Engineering Label Switched Paths in IP Networks using a Pre-Planned Flow Optimization Model / A. Bagula ; A. Krzesinski
Wireless
QoS for Adaptive Multimedia in Wireless/Mobile Networks / Y. Xiao ; C. Chen
MoSync: A Synchronization Scheme for Cellular Wireless and Mobile Multimedia Systems / A. Boukerche ; S. Hong ; T. Jacob
Routing
Performance Study of a Multipath Routing Method for Wireless Mobile Ad Hoc Networks / K. Wu ; J. Harms
Minimizing Routing State for Light-Weight Network Simulation / P. Huang ; J. Heidemann
Non-Blocking, Localized Routing Algorithm for Balanced Energy Consumption in Mobile Ad Hoc Networks / K. Woo ; C. Yu ; D. Lee ; H. Youn ; B. Lee
Stability Analysis on Active Queue Management Algorithms in Routers / W. Wu ; Y. Ren ; X. Shan
Network Simulation/Emulation
ANML: A Language for Describing Networks / C. Kiddle ; R. Simmonds ; D. Wilson ; B. Unger
Mulit-Resolution Network Simulations Using Dynamic Component Substitution / D. Rao ; P. Wilsey
Packet Reading for Network Emulation / R. Bradford
Split Protocol Stack Network Simulations Using the Dynamic Simulation Backplane / D. Xu ; G. Riley ; R. Fujimoto
Design--Why We Don't Do It Right / Dr. John Hines
Modeling
Low-Cost Performance Prediction of Data-Dependent Data Parallel Programs / H. Gautama ; A. van Gemund
A Modular, Analytical Throughput Model for Modern Disk Arrays / M. Uysal ; G. Alvarez ; A. Merchant
Performing File Prediction with a Program-Based Successor Model / T. Yeh ; D. Long ; S. Brandt
Network Traffic
Improving Ensemble-TCP Performance on Asymmetric Networks / Q. Wu ; C. Williamson
How Does TCP Generate Pseudo-Self-Similarity? / L. Guo ; M. Crovella ; I. Matta
Generalized Processor Sharing with Long-Range Dependent Traffic Input / X. Yu ; L-J. Thng ; Y. Jiang
Benchmarking
Plain End-to-End Measurement for Local Area Network Voice Transmission Feasibility / W. Kampichler ; K. Goeschka
Tuning of the Checkpointing and Communication Library for Optimistic Simulation on Myrinet Based NOWs / F. Quaglia ; A. Santoro ; B. Ciciani
Performance of Finite Field Arithmetic in an Elliptic Curve Cryptosystem / J. Higgins ; Z. Li ; M. Clement
Switching
AQueueing Model for Pipelined Circuit-Switched Networks with the MMPP Traffic / G. Min ; M. Ould-Khaoua
Service Guarantees in Deflection Networks / W. Olesinski ; P. Gburzynski
Analysis of Timeout-Based Adaptive Wormhole Routing / H. Sarbazi-Azad ; A. Khonsari
File Systems
PROFS--Performance-Oriented Data Reorganization for Log-Structured File System on Multi-Zone Disks / J. Wang ; Y. Hu
Aggregating Caches: A Mechanism for Implicit File Prefetching / A. Amer
A Bit-Parallel Search Algorithm for Allocating Free Space / R. Burns ; W. Hineman
Large-Scale Simulation of Replica Placement Algorithms for a Serverless Distributed File System / J. Douceur ; R. Wattenhofer
Tools
Parameterized Mobile Action Generator for a Wireless PCS Network / S-E. Park ; C. Purdy
On-Line Test System Applied in Routing Protocol Test / Y. Zhao ; X. Yin ; B. Han ; J. Wu
PTPlan MPLS: A Tool for MPLS Network Dimensioning / L. Cardoso ; J. Patrao ; C. Lopes ; A. de Sousa ; R. Valadas
BRITE: An Approach to Universal Topology Generation / A. Medina ; A. Lakhina ; J. Byers
On-Line Simulation Techniques for Real-Time Management of Systems / Dr. Richard Fujimoto
WWW
The Structural Cause of File Size Distributions / A. Downey
A Simulation Analysis of Dynamic Server Selection Algorithms for Replicated Web Services / M. Bernardo
Simulation Evaluation of a Heterogeneous Web Proxy Caching Hierarchy / M. Busari
HTTP Simulator Validation Using Real Measurements: A Case Study / B. Davison
Broadband
Performance Evaluation Based on an Aggregate ATM Model / S. Galmes
Modeling and Analysis of an ABR Flow Control Algorithm for a Virtual Source/Virtual Destination Switch / C. Cseh
On Class-Based Isolation of UDP, Short-Lived and Long-Lived TCP Flows / S. Yilmaz
A Stream Tapping Protocol with Partial Preloading / J-F. Paris
Author Index
Message from the General Chair
Message from the Program Chair
Conference Organizers
23.

図書
図書
23. Proceedings, 2001 International Conference on Parallel Architectures and Compilatin Techniques, 8-12 September 2001, Barcelona, Catalunya, Spain (: pbk)
Sponsored by IEEE Computer Society Technical Committee on Computer Architecture, IEEE Computer Society Technical Commitee on Parallel Processing, ACM SIGARCH, IFIP Working Group 10.3 ; with the support of Technical University of Catalunya (UPC) ... [et al.]
出版情報: Los Alamitos, Calif. : IEEE Computer Society, c2001  x, 305 p. ; 28 cm
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General Chair's Message
Conference Organizers
Program Committee
Keynote Address / Randall D. Isaac
Simulation and Modeling / Session 1：
Basic Block Distribution Analysis to Find Periodic Behavior and Simulation Points in Applications / T. Sherwood ; E. Perelman ; B. Calder
Modeling Superscalar Processors via Statistical Simulation / S. Nussbaum ; J. Smith
Hybrid Analytical-Statistical Modeling for Efficiently Exploring Architecture and Workload Design Spaces / L. Eeckhout ; K. De Bosschere
Efficient Caches / Session 2：
Filtering Techniques to Improve Trace-Cache Efficiency / R. Rosner ; A. Mendelson ; R. Ronen
Reactive-Associative Caches / B. Batson ; T. Vijaykumar
Adaptive Mode Control: A Static-Power-Efficient Cache Design / H. Zhou ; M. Toburen ; E. Rotenberg ; T. Conte
Specialized Instruction Sets / Session 3：
Implementation and Evaluation of the Complex Streamed Instruction Set / B. Juurlink ; D. Tcheressiz ; S. Vassiliadis ; H. Wijshoff
On the Efficiency of Reductions in [mu]-SIMD Media Extensions / J. Corbal ; R. Espasa ; M. Valero
Prediction and Recovery / Justin RattnerSession 4：
Boolean Formula-Based Branch Prediction for Future Technologies / D. Jimenez ; H. Hanson ; C. Lin
Using Dataflow Based Context for Accurate Value Prediction / R. Thomas ; M. Franklin
Recovery Mechanism for Latency Misprediction / E. Morancho ; J. Maria Llaberia ; A. Olive
Memory Optimization / Session 5：
A Cost Framework for Evaluating Integrated Restructuring Optimizations / B. Chandramouli ; J. Carter ; W. Hsieh ; S. McKee
Compiling for the Impulse Memory Controller / X. Huang ; Z. Wang ; K. McKinley
On the Stability of Temporal Data Reference Profiles / T. Chilimbi
Program Optimization / Session 6：
Code Reordering and Speculation Support for Dynamic Optimization Systems / E. Nystrom ; R. Barnes ; M. Merten ; W-M. Hwu
A Unified Modulo Scheduling and Register Allocation Technique for Clustered Processors / J. Codina ; J. Sanchez ; A. Gonzalez
Cache-Friendly Implementations of Transitive Closure / M. Penner ; V. Prasanna
Technology Implications / Session 7：
Exploring the Design Space of Future CMPs / J. Huh ; D. Burger ; S. Keckler
Area and System Clock Effects on SMT/CMP Processors / J. Burns ; J-L. Gaudiot
Parallel Machines / Joel EmerSession 8：
Limits on Speculative Module-Level Parallelism in Imperative and Object-Oriented Programs on CMP Platforms / F. Warg ; P. Stenstrom
Compiler and Runtime Analysis for Efficient Communication in Data Intensive Applications / R. Ferreira ; G. Agrawal ; J. Saltz
Architectural Support for Parallel Reductions in Scalable Shared-Memory Multiprocessors / M. Garzaran ; M. Prvulovic ; Y. Zhang ; A. Jula ; H. Yu ; L. Rauchwerger ; J. Torrellas
Data Prefetching / Session 9：
Optimizing Software Data Prefetches with Rotating Registers / G. Doshi ; R. Krishnaiyer ; K. Muthukumar
Multi-Chain Prefetching: Effective Exploitation of Inter-Chain Memory Parallelism for Pointer-Chasing Codes / N. Kohout ; S. Choi ; D. Kim ; D. Yeung
Data Flow Analysis for Software Prefetching Linked Data Structures in Java / B. Cahoon
Comparing and Combining Read Miss Clustering and Software Prefetching / V. Pai ; S. Adve
Author Index
General Chair's Message
Conference Organizers
Program Committee
24.

図書
図書
24. Proceedings : 28th Annual International Symposium on Computer Architecture, June 30-July 4, 2001, Göteborg, Sweden
sponsored by IEEE Computer Society Technical Committee on Computer Architecture, Association for Computing Machinery SIGARCH
出版情報: Los Alamitos, Calif. : IEEE Computer Society, c2001  xi, 291 p. ; 28 cm
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General Chair's Message
Program Chair's Message
Conference Organization
Reviewers
Plenary Session
Opening Remarks
Keynote Speech: Greg Papadopoulos, CTO, Sun Microsystems Inc., USA
Multithreading and Speculation / Session 1：
Execution-based Prediction Using Speculative Slices / C. Zilles ; G. Sohi
Speculative Precomputation: Long-range Prefetching of Delinquent Loads / J. Collins ; H. Wang ; D. Tullsen ; C. Hughes ; Y. Lee ; D. Lavery ; J. Shen
Dynamically Allocating Processor Resources between Nearby and Distant ILP / R. Balasubramonian ; S. Dwarkadas ; D. Albonesi
Memory System Issues / Session 2：
Tolerating Memory Latency through Software-Controlled Pre-Execution in Simultaneous Multithreading Processors / C. Luk
Data Prefetching by Dependence Graph Precomputation / M. Annavaram ; J. Patel ; E. Davidson
Concurrency, Latency, or System Overhead: Which Has the Largest Impact on Uniprocessor DRAM-System Performance? / V. Cuppu ; B. Jacob
Processor Architecture / Session 3：
Focusing Processor Policies via Critical-Path Prediction / B. Fields ; S. Rubin ; R. Bodik
Automated Design of Finite State Machine Predictors for Customized Processors / T. Sherwood ; B. Calder
Better Exploration of Region-Level Value Locality with Integrated Computation Reuse and Value Prediction / Y. Wu ; D. Chen ; J. Fang
Communication Support / Session 4：
CryptoManiac: A Fast Flexible Architecture for Secure Communication / L. Wu ; C. Weaver ; T. Austin
QoS Provisioning in Clusters: An Investigation of Router and NIC Design / K. Yum ; E. Kim ; C. Das
Cache Management / Session 5：
Locality vs. Criticality / S. Srinivasan ; R. Ju ; A. Lebeck ; C. Wilkerson
Dead-Block Prediction and Dead-Block Correlating Prefetchers / A. Lai ; C. Fide ; B. Falsafi
Code Layout Optimizations for Transaction Processing Workloads / A. Ramirez ; L. Barroso ; K. Gharachorloo ; R. Cohn ; J. Larriba-Pey ; P. Lowney ; M. Valero
Architectural Impact of Emerging Technologies / Session 6A：
Exploring and Exploiting Wire-Level Pipelining in Emeging Technologies / M. Niemier ; P. Kogge
NanoFabrics: Spatial Computing Using Molecular Electronics / S. Goldstein ; M. Budiu
Shared-Memory Multiprocessors / Session 6B：
A Simple Method for Extracting Models from Protocol Code / D. Lie ; A. Chou ; D. Engler ; D. Dill
Removing Architectural Bottlenecks to the Scalability of Speculative Parallelization / M. Prvulovic ; M. Garzaran ; L. Rauchwerger ; J. Torrellas
Energy-Effective Designs / Session 7：
Power and Energy Reduction Via Pipeline Balancing / R. Bahar ; S. Manne
Energy-Effective Issue Logic / D. Folegnani ; A. Gonzalez
Cache Decay: Exploiting Generational Behavior to Reduce Cache Leakage Power / S. Kaxiras ; Z. Hu ; M. Martonosi
Performance Tools and Evaluations / Session 8：
Variability in the Execution of Multimedia Applications and Implications for Architecture / P. Kaul ; S. Adve ; R. Jain ; C. Park ; J. Srinivasan
Measuring Experimental Error in Microprocessor Simulation / R. Desikan ; D. Burger ; S. Keckler
Rapid Profiling via Stratified Sampling / S. Sastry ; J. Smith
Author Index
General Chair's Message
Program Chair's Message
Conference Organization
25.

図書
図書
25. Proceedings : the 21st Annual International Symposium on Computer Architecture, April 18-21, 1994, Chicago, Illinois (: paper ; : micro. ; : case)
sponsored by IEEE Computer Society, Technical Committee on Computer Architecture, Association for Computing Machinery, SIGARCH
出版情報: Los Alamitos : IEEE Computer Society Press, c1994  xii, 394 p. ; 28 cm
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26.

図書
図書
26. The 24th Annual International Symposium on Computer Architecture conference proceedings, June 2-4, 1997, Denver, Colorado (: softbound ; : casebound)
sponsored by ACM SIGARCH, IEEE Computer Society, TCCA
出版情報: New York : ACM Press, c1997  vii, 350 p. ; 28 cm
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27.

図書
図書
27. Proceedings, 30th Annual International Symposium on Computer Architecture, San Diego, California, USA, June 9-11, 2003
IEEE Computer Society Technical Committee on Computer Architecture, ACM SIGARCH
出版情報: Los Alamitos, Calif. : IEEE Computer Society, c2003  xi, 448 p. ; 28 cm
シリーズ名: Computer architecture news ; v. 31, no. 2, May 2003
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Symposium Chairman's Welcome
Message from the Program Chair
Committee Members
Thermal and Energy-Aware Microarchitectures / Session 1：
Temperature-Aware Microarchitecture / K. Skadron ; M. Stan ; W. Huang ; S. Velusamy ; K. Sankaranarayanan ; D. Tarjan
Profile-Based Dynamic Voltage and Frequency Scaling for a Multiple Clock Domain Microprocessor / G. Magklis ; M. Scott ; G. Semeraro ; D. Albonesi ; S. Dropsho
Processor Architecture / Session 2：
Half-Price Architecture / I. Kim ; M. Lipasti
Implicitly-Multithreaded Processors / I. Park ; B. Falsafi ; T. Vijaykumar
Panel: Subsetting SPEC When Measuring Results: Valid or Manipulative?
MisSPECulation: Partial and Misleading Use of SPEC CPU2000 in Computer Architecture Conferences / D. Citron
Microarchitecture Techniques / Session 3a：
Banked Multiported Register Files for High-Frequency Superscalar Microprocessors / J. Tseng ; K. Asanovic
Pipeline Damping: A Microarchitectural Technique to Reduce Inductive Noise in Supply Voltage / M. Powell
Smarts: Accelerating Microarchitecture Simulation via Rigorous Statistical Sampling / R. Wunderlich ; T. Wenisch ; J. Hoe
Recovery and Replay / Session 3b：
Transient-Fault Recovery for Chip Multiprocessors / M. Gomaa ; C. Scarbrough ; I. Pomeranz
ReEnact: Using Thread-Level Speculation Mechanisms to Debug Data Races in Multithreaded Codes / M. Prvulovic ; J. Torrellas
A "Flight Data Recorder" for Enabling Full-System Multiprocessor Deterministic Replay / M. Xu ; R. Bodik ; M. Hill
Energy-Saving Designs / Session 4a：
A Highly-Configurable Cache Architecture for Embedded Systems / C. Zhang ; F. Vahid ; W. Najjar
Energy Efficient Co-Adaptive Instruction Fetch and Issue / A. Buyuktosunoglu ; T. Karkhanis ; P. Bose
Positional Adaptation of Processors: Application to Energy Reduction / M. Huang ; J. Renau
DRPM: Dynamic Speed Control for Power Management in Server Class Disks / S. Gurumurthi ; A. Sivasubramaniam ; M. Kandemir ; H. Franke
Interconnects and Multiprocessors / Session 4b：
Token Coherence: Decoupling Performance and Correctness / M. Martin ; D. Wood
GOAL: A Load-Balanced Adaptive Routing Algorithm for Torus Networks / A. Singh ; W. Dally ; A. Gupta ; B. Towles
Using Destination-Set Prediction to Improve the Latency/Bandwidth Tradeoff in Shared-Memory Multiprocessors / P. Harper ; D. Sorin
Performance Analysis of the Alpha 21364-Based HP GS1280 Multiprocessor / Z. Cvetanovic
Front-End Scheduling / Session 5：
Parallelism in the Front-End / P. Oberoi ; G. Sohi
Effective ahead Pipelining of Instruction Block Address Generation / A. Seznec ; A. Fraboulet
Cyclone: A Broadcast-Free Dynamic Instruction Scheduler with Selective Replay / D. Ernst ; A. Hamel ; T. Austin
Clustered Processors / Session 6a：
Improving Dynamic Cluster Assignment for Clustered Trace Cache Processors / R. Bhargava ; L. John
Dynamically Managing the Communication-Parallelism Trade-off in Future Clustered Processors / R. Balasubramonian ; S. Dwarkadas
A Pipelined Memory Architecture for High Throughput Network Processors / T. Sherwood ; G. Varghese ; B. Calder
Efficient Use of Memory Bandwidth to Improve Network Processor Throughput / J. Hasan ; S. Chandra
Prediction / Session 7a：
Improving Branch Prediction by Dynamic Dataflow-Based Identification of Correlated Branches from a Large Global History / R. Thomas ; M. Franklin ; C. Wilkerson ; J. Stark
Detecting Global Stride Locality in Value Streams / H. Zhou ; J. Flanagan ; T. Conte
Phase Tracking and Prediction / S. Sair
Mechanisms and Support / Session 7b：
Virtual Simple Architecture (VISA): Exceeding the Complexity Limit in Safe Real-Time Systems / A. Anantaraman ; K. Seth ; K. Patil ; E. Rotenberg ; F. Mueller
DISE: A Programmable Macro Engine for Customizing Applications / M. Corliss ; E. Lewis ; A. Roth
Building Quantum Wires: The Long and the Short of It / M. Oskin ; F. Chong ; I. Chuang ; J. Kubiatowicz
Memory Issues / Session 8：
Guided Region Prefetching: A Cooperative Hardware/Software Approach / Z. Wang ; D. Burger ; S. Reinhardt ; K. McKinley ; C. Weems
Overcoming the Limitations of Conventional Vector Processors / C. Kozyrakis ; D. Patterson
A Performance Analysis of PIM, Stream Processing, and Tiled Processing on Memory-Intensive Signal Processing Kernels / J. Suh ; E. Kim ; S. Crago ; L. Srinivasan ; M. French
Exploiting Parallelisms / Session 9：
Exploiting ILP, TLP and DLP with the Polymorphous TRIPS Architecture / K. Sankaralingam ; R. Nagarajan ; H. Liu ; C. Kim ; J. Huh ; S. Keckler ; C. Moore
The Jrpm System for Dynamically Parallelizing Java Programs / M. Chen ; K. Olukotun
Author Index
Symposium Chairman's Welcome
Message from the Program Chair
Committee Members
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