| Message from the General Chair |
| Message from the Program Chairs |
| Committees |
| Reviewers |
| Keynote |
| Fifty Years of Microarchitecture / H. Cragon |
| Novel Ideas / Session 1： |
| Skipper: A Microarchitecture for Exploiting Control-Flow Independence / C. Cher ; T. Vijaykumar |
| Performance Characterization of a Hardware Mechanism for Dynamic Optimization / B. Fahs ; S. Bose ; M. Crum ; B. Slechta ; F. Spadini ; T. Tung ; S. Patel ; S. Lumetta |
| Using Variable-MHz Microprocessors to Efficiently Handle Uncertainty in Real-Time Systems / E. Rotenberg |
| A Design Space Evaluation of Grid Processor Architectures / R. Nagarajan ; K. Sankaralingam ; D. Burger ; S. Keckler |
| Memory Hierarchies / Session 2： |
| Reducing Set-Associative Cache Energy via Way-Prediction and Selective Direct-Mapping / M. Powell ; A. Agrawal ; B. Falsafi ; K. Roy |
| A Code Decompression Architecture for VLIW Processors / Y. Xie ; W. Wolf ; H. Lekatsas |
| Direct Load: Dependence-Linked Dataflow Resolution of Load Address and Cache Coordinate / B. Chung ; J. Zhang ; J. Peir ; S. Lai ; K. Lai |
| Energy Efficient Architectures / Session 3： |
| Reducing Power Requirements of Instruction Scheduling through Dynamic Allocation of Multiple Datapath Resources / D. Ponomarev ; G. Kucuk ; K. Ghose |
| Exploiting VLIW Schedule Slacks for Dynamic and Leakage Energy Reduction / W. Zhang ; N. Vijaykrishnan ; M. Kandemir ; M. Irwin ; D. Duarte ; Y. Tsai |
| Reducing Power with Dynamic Critical Path Information / J. Seng ; E. Tune ; D. Tullsen |
| Direct Addressed Caches for Reduced Power Consumption / E. Witchel ; S. Larsen ; C. Ananian ; K. Asanovic |
| Emerging Applications for the Connected Home / A. Wolfe |
| Modulo Scheduling / Session 4： |
| Modulo Schedule Buffers / M. Merten ; W. Hwu |
| Graph-Partitioning Based Instruction Scheduling for Clustered Processors / A. Aleta ; J. Codina ; J. Sanchez ; A. Gonzalez |
| Modulo Scheduling with Integrated Register Spilling for Clustered VLIW Architectures / J. Zalamea ; J. Llosa ; E. Ayguade ; M. Valero |
| Compilation / Session 5： |
| Efficient Static Single Assignment Form for Predication / A. Stoutchinin ; F. de Ferriere |
| The Impact of If-Conversion and Branch Prediction on Program Execution on the Intel Itanium Processor / Y. Choi ; A. Knies ; L. Gerke ; T. Ngai |
| Mapping Reference Code to Irregular DSPs within the Retargetable, Optimizing Compiler COGEN(T) / G. Grewal ; C. Wilson |
| Superscalar Architectures / Session 6： |
| Select-Free Instruction Scheduling Logic / M. Brown ; J. Stark ; Y. Patt |
| Dual Use of Superscalar Datapath for Transient-Fault Detection and Recovery / J. Ray ; J. Hoe |
| A High-Speed Dynamic Instruction Scheduling Scheme for Superscalar Processors / M. Goshima ; K. Nishino ; Y. Nakashima ; S. Mori ; T. Kitamura ; S. Tomita |
| Reducing the Complexity of the Register File in Dynamic Superscalar Processors / R. Balasubramonian ; S. Dwarkadas ; D. Albonesi |
| Multimedia and Graphics / Session 7： |
| Saving Energy with Architectural and Frequency Adaptations for Multimedia Applications / C. Hughes ; J. Srinivasan ; S. Adve |
| Enhancing Loop Buffering of Media and Telecommunications Applications using Low-Overhead Predication / J. Sias ; H. Hunter |
| Cool-Cache for Hot Multimedia / O. Unsal ; R. Ashok ; I. Koren ; C. Krishna ; C. Moritz |
| ZR: A 3D API Transparent Technology for Chunk Rendering / E. Hsieh ; V. Pentkovski ; T. Piazza |
| Multithreading and Value Prediction / Session 8： |
| Speculative Lock Elision: Enabling Highly Concurrent Multithreaded Execution / R. Rajwar ; J. Goodman |
| Dynamic Speculative Precomputation / J. Collins ; H. Wang ; J. Shen |
| Handling Long-latency Loads in a Simultaneous Multithreading Processor / J. Brown |
| Correctly Implementing Value Prediction in Microprocessors that Support Multithreading or Multiprocessing / M. Martin ; D. Sorin ; H. Cain ; M. Hill ; M. Lipasti |
| Index of Authors |
| Message from the General Chair |
| Message from the Program Chairs |
| Committees |
ＥＢ
