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図書
図書
1. ASPLOS XII : Twelfth International Conference on Architectural Support for Programming Languages and Operating Systems, October 21-25, 2006, San Jose, California, USA ([:pbk])
sponsored by SIGARCH, SIGPLAN, SIGOPS ; with support from AMD ... [et.al]
出版情報: New York : Association for Computing Machinery, c2006  xi, 428 p. ; 28 cm
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図書
図書
2. ASPLOS XI : Eleventh International Conference on Architectural Support for Programming Languages and Operating Systems, October 9-13, 2004, Boston, Massachusetts ([:pbk])
sponsored by SIGARCH, SIGPLAN, SIGOPS ; with support from AMD ... [et.al]
出版情報: New York : Association for Computing Machinery, c2004  x, 286 p. ; 28 cm
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目次情報:
Includes bibliographical references and author index
Includes bibliographical references and author index
3.

図書
図書
3. Proceedings : Ninth International Symposium on High-Performance Computer Architecture, 8-12 February 2003, Anaheim, California
sponsored by the IEEE Computer Society Technical Committee on Computer Architecture
出版情報: Los Alamitos, Cailf. : IEEE Computer Society Press, c2003  xiv, 390 p. ; 28 cm
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図書
図書
4. ASPLOS-IX proceedings : ninth International Conference on Architectural Support for Programming Languages and Operating Systems, Cambridge, Massachusetts, November 12-15, 2000
International Conference on Architectural Support for Programming Languages and Operating Systems ; Association for Computing Machinery ; SIGARCH ; ACM Special Interest Group in Operating Systems ; ACM Special Interest Group in Programming Languages
出版情報: New York, N.Y. : Association for Computing Machinery, c2000  ix, 271 p. ; 28 cm
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5.

図書
図書
5. ASPLOS-X proceedings : Tenth International Conference on Architectural Support for Programming Languages and Operating Systems, SanJose, California, October 5-9, 2002
International Conference on Architectural Support for Programming Languages and Operating Systems
出版情報: New York, N.Y. : Association for Computing Machinery, c2002  xiv, 320 p. ; 28 cm
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6.

図書
図書
6. Proceedings, seventh Workshop on Interaction between Compilers and Computer Architectures, INTERACT-7 2003, 8 February 2003, Anaheim, California
sponsored by Samsung Electronics, IEEE Computer Society
出版情報: Los Alamitos, Calif. : IEEE Computer Society, c2003  viii, 95 p. ; 28 cm
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7. Proceedings, Fifth IEEE International Workshop on Computer Architecture for Machine Perception, September 11-13, 2000, Padova, Italy
edited by Virginio Cantoni, Concettina Guerra ; sponsored by IEEE Computer Society Technical Committees on Pattern Analysis and Recognition, Parallell Processing and Cmputer Architecture ; in cooperation with ACM SIGARCH
出版情報: Los Alamitos, CA ; Tokyo : IEEE Computer Society, c2000  xi, 364 p. ; 28 cm
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8.

図書
図書
8. Proceedings of the 27th International Symposium on Computer Architecture, Jun 12-14, 2000, Vancouver, British Columbia, Canada (: case ; ACM)
sponsored by IEEE Computer Society TCCA, ACM SIGARCH
出版情報: Los Alamitos, CA : IEEE Computer Society, c2000 , New York, NY : the Association for Computing Machinery, c2000  vi, 328 p. ; 28 cm
シリーズ名: Computer architecture news ; v.28, no.2, May 2000
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9. Proceedings : Eighth International Symposium on High-Performance Computer Architecture, 2-6 February 2002, Cambridge, Massachusetts
sponsored by IEEE Computer Society Technical Committee on Computer Architecture
出版情報: Los Alamitos, Cailf. : IEEE Computer Society Press, c2002  xiii, 323 p. ; 28 cm
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10. Proceedings : 29th Annual International Symposium on Computer Architecture, 25-29 May 2002, Anchorage, Alaska
sponsored by IEEE TCCA, ACM SIGARCH
出版情報: Los Alamitos, Calif. : IEEE Computer Society, c2002  xv, 331 p. ; 28 cm
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目次情報: 続きを見る
Message from the General Chair
Message from the Program Chair
Organizing Committee
Steering Committee
Program Committee
Reviewers
Welcoming Remarks
Keynote Address / Burton J. Smith
Processor Pipelines / Session 1：
The Optimum Pipeline Depth for a Microprocessor / A. Hartstein ; T. Puzak
The Optimal Logic Depth per Pipeline Stage Is 6 to 8 FO4 Inverter Delays / M. Hrishikesh ; N. Jouppi ; K. Farkas ; D. Burger ; S. Keckler ; P. Shivakumar
Increasing Processor Performance by Implementing Deeper Pipelines / E. Sprangle ; D. Carmean
Processor Scheduling / Session 2：
Efficient Dynamic Scheduling through Tag Elimination / D. Ernst ; T. Austin
Slack: Maximizing Performance under Technological Constraints / B. Fields ; R. Bodik ; M. Hill
A Large, Fast Instruction Window for Tolerating Cache Misses / A. Lebeck ; J. Koppanalil ; T. Li ; J. Patwardhan ; E. Rotenberg
An Instruction Set and Microarchitecture for Instruction Level Distributed Processing / H.-S. Kim ; J. Smith
Safety and Reliability / Robert P. ColwellSession 3：
Transient-Fault Recovery Using Simultaneous Multithreading / T. Vijaykumar ; I. Pomeranz ; K. Cheng
Detailed Design and Evaluation of Redundant Multithreading Alternatives / S. Mukherjee ; M. Kontz ; S. Reinhardt
ReVive: Cost-Effective Architectural Support for Rollback Recovery in Shared-Memory Multiprocessors / M. Prvulovic ; Z. Zhang ; J. Torrellas
SafetyNet: Improving the Availability of Shared Memory Multiprocessors with Global Checkpoint/Recovery / D. Sorin ; M. Martin ; D. Wood
Power Aware Architecture / Session 4：
Dynamic Fine-Grain Leakage Reduction Using Leakage-Biased Bitlines / S. Heo ; K. Barr ; M. Hampton ; K. Asanovic
Drowsy Caches: Simple Techniques for Reducing Leakage Power / K. Flautner ; N. Kim ; S. Martin ; D. Blaauw ; T. Mudge
Power and Performance Evaluation of Globally Asynchronous Locally Synchronous Processors / A. Iyer ; D. Marculescu
Memory Systems / Session 5：
Using a User-Level Memory Thread for Correlation Prefetching / Y. Solihin ; J. Lee
Avoiding Initialization Misses to the Heap / J. Lewis ; B. Black ; M. Lipasti
Going the Distance for TLB Prefetching: An Application-Driven Study / G. Kandiraju ; A. Sivasubramaniam
Dynamic Optimization / Session 6：
Timekeeping in the Memory System: Predicting and Optimizing Memory Behavior / Z. Hu ; S. Kaxiras ; M. Martonosi
Implementing Optimizations at Decode Time / I. Kim
Managing Multi-configuration Hardware via Dynamic Working Set Analysis / A. Dhodapkar
Data and Storage Networks / Session 7：
Queue Pair IP: A Hybrid Architecture for System Area Networks / P. Buonadonna ; D. Culler
Experiences with VI Communication for Database Storage / Y. Zhou ; A. Bilas ; S. Jagannathan ; C. Dubnicki ; J. Philbin ; K. Li
Vector Architectures / Session 8：
Speculative Dynamic Vectorization / A. Pajuelo ; A. Gonzalez ; M. Valero
Tarantula: A Vector Extension to the Alpha Architecture / R. Espasa ; F. Ardanaz ; J. Emer ; S. Felix ; J. Gago ; R. Gramunt ; I. Hernandez ; T. Juan ; G. Lowney ; M. Mattina ; A. Seznec
Supporting Deep Speculation / Session 9：
Design Tradeoffs for the Alpha EV8 Conditional Branch Predictor / V. Krishnan ; Y. Sazeides
Difficult-Path Branch Prediction Using Subordinate Microthreads / R. Chappell ; F. Tseng ; A. Yoaz ; Y. Patt
A Scalable Instruction Queue Design Using Dependence Chains / S. Raasch ; N. Binkert
Author Index
Message from the General Chair
Message from the Program Chair
Organizing Committee
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