| Co-Chairs and Program Committee |
| Tools 1 / Session 1： |
| Macro-Based Hardware Compilation of Java Bytecodes into a Dynamic Reconfigurable Computing System / J.M.P. Cardoso ; H.C. Neto |
| A CAD Suite for High-Performance FPGA Design / B. Hutchings ; P. Bellows ; J. Hawkins ; S. Hemmert ; B. Nelson ; M. Rytting |
| Formal Verification of Reconfigurable Cores / S. Singh ; C.J. Lillieroth |
| Network Applications / Session 2： |
| Transmutable Telecom System and Its Application / T. Miyazaki ; T. Murooka ; M. Katayama ; A. Takahara |
| Implementation and Evaluation of a Prototype Reconfigurable Router / J.R. Hess ; D.C. Lee ; S.J. Harper ; M.T. Jones ; P.M. Athanas |
| Compilation / Session 3： |
| Pipeline Vectorization for Reconfigurable Systems / M. Weinhardt ; W. Luk |
| Automatic Allocation of Arrays to Memories in FPGA Processors with Multiple Memory Banks / M.B. Gokhale ; J.M. Stone |
| Parallelizing Applications into Silicon / J. Babb ; M. Rinard ; C.A. Moritz ; W. Lee ; M. Frank ; R. Barua ; S. Amarasinghe |
| Architectures / Session 4： |
| Reconfigurable Elements for a Video Pipeline Processor / M.R. Piacentino ; G.S. van der Wal ; M.W. Hansen |
| ConCISe: A Compiler-Driven CPLD-Based Instruction Set Accelerator / B. Kastrup ; A. Bink ; J. Hoogerbrugge |
| Tools 2 / Session 5： |
| CPR: A Configuration Profiling Tool / S. Cadambi ; S.C. Goldstein |
| Debugging Techniques for Dynamically Reconfigurable Hardware / N. McKay |
| Improving Simulation Accuracy in Design Methodologies for Dynamically Reconfigurable Logic Systems / M. Vasilko ; D. Cabanis |
| Graphics Applications / Session 6： |
| Reconfigurable Computing for Augmented Reality / T.K. Lee ; J.R. Rice ; N. Shirazi ; P.Y.K. Cheung |
| Sepia: Scalable 3D Compositing using PCI Pamette / L. Moll ; A. Heirich ; M. Shand |
| Applications / Session 7： |
| An Edge-Endpoint-Based Configurable Hardware Architecture for VLSI CAD Layout Design Rule Checking / Z. Luo ; M. Martonosi ; P. Ashar |
| Fafner--Accelerating Nesting Problems with FPGAs / J.C. Alves ; J.C. Ferreira ; C. Albuquerque ; J.F. Oliveira ; J.S. Ferreira ; J. Silva Matos |
| DSP Applications / Session 8： |
| Field Programmable Gate Array Based Radar Front-End Digital Signal Processing / T.J. Moeller ; D.R. Martinez |
| Optimizing FPGA-Based Vector Product Designs / D. Benyamin ; J. Villasenor |
| Run Time Systems / Session 9： |
| PCI-PipeRench and the SwordAPI: A System for Stream-based Reconfigurable Computing / R. Laufer ; R.R. Taylor ; H. Schmit |
| Safe and Protected Execution for the Morph/AMRM Reconfigurable Processor / A.A. Chien ; J.H. Byun |
| Implementing an API for Distributed Adaptive Computing Systems / M. Jones ; L. Scharf ; J. Scott ; C. Twaddle ; M. Yaconis ; K. Yao ; P. Athanas ; B. Schott |
| Arithmetic / Session 10： |
| A Super-Serial Galois Fields Multiplier for FPGAs and its Application to Public-Key Algorithms / G. Orlando ; C. Paar |
| Automatic Floating to Fixed Point Translation and its Application to Post-Rendering 3D Warping / M.P. Leong ; M.Y. Yeung ; C.K. Yeung ; C.W. Fu ; P.A. Heng ; P.H.W. Leong |
| Dynamic Precision Management for Loop Computations on Reconfigurable Architectures / K. Bondalapati ; V.K. Prasanna |
| Poster Session 1 |
| Accelerating Run-Time Reconfiguration on FCCMs / J.-P. Heron ; R.F. Woods |
| A Virtual Hardware Handler for RTR Systems / R. Turner ; S. Sezer |
| Algorithm Analysis and Mapping Environment for Adaptive Computing Systems: Further Results / E.K. Pauer ; P.D. Fiore ; J.M. Smith |
| Development System for FPGA-Based Digital Circuits / V. Sklyarov ; J. Fonseca ; R. Monteiro ; A. Oliveira ; A. Melo ; N. Lau ; I. Skliarova ; P. Neves ; A. Ferrari |
| Design of a JTAG Based Run Time Reconfigurable System / C. Cousineau ; F. Laperle ; Y. Savaria |
| Architectures for System-Level Applications of Adaptive Computing / C. Chen ; S. Crago ; J. Czarnaski ; M. French ; I. Hom ; T. Tho ; T. Valenti |
| Task-level Partitioning and RTL Design Space Exploration for Multi-FPGA Architectures / V. Srinivasan ; R. Vemuri |
| Enabling Automatic Module Generation for FCCM Compilers / A. Koch |
| Poster Session 2 |
| ICARUS: A Dynamically Reconfigurable Computer Architecture / M. Baxter |
| SONIC--A Plug-In Architecture for Video Processing / S.D. Haynes ; J. Stone |
| A Reconfigurable Platform for Academic Purposes / C. Teuscher ; J.-O. Haenni ; F.J. Gomez ; H.F. Restrepo ; E. Sanchez |
| VHDL Placement Directives for Parametric IP Blocks / J. Hwang ; C. Patterson ; S. Mitra |
| Runlength Compression Techniques for FPGA Configurations / S. Hauck ; W.D. Wilson |
| Poster Session 3 |
| Accelerating An IR Automatic Target Recognition Application with FPGAs / J. Jean ; X. Liang ; B. Drozd ; K. Tomko |
| Mapping of an Automated Target Recognition Application from a Graphical Software Environment to FPGA-based Reconfigurable Hardware / B. Levine ; S. Natarajan ; C. Tan ; D. Newport ; D. Bouldin |
| Hybrid Data/Configuration Caching for Striped FPGAs / D. Deshpande ; A.K. Somani ; A. Tyagi |
| On Reconfiguring Cache for Computing / H.-S. Kim |
| Reconfigurable Pipelines in VLIW Execution Units / R.D. Williams ; B.D. Kuebert |
| Fast Online Placement for Reconfigurable Computing Systems / K. Bazargan ; M. Sarrafzadeh |
| Poster Session 4 |
| A Compact Fast Variable Key Size Elliptic Curve Cryptosystem Coprocessor / L. Gao ; S. Shrivastava ; H. Lee ; G.E. Sobelman |
| A Virtual Logic Algorithm for Solving Satisfiability Problems Using Reconfigurable Hardware / M. Abramovici ; J.T. de Sousa |
| Reducing Compilation Time of Zhong's FPGA-based SAT solver / P.K. Chan ; M.J. Boyd ; S. Goren ; K. Klenk ; V. Kodavati ; R. Kundu ; M. Margolese ; J. Sun ; K. Suzuki ; E. Thorne ; X. Wang ; J. Xu ; M. Zhu |
| FPGA-based Structures for On-line FFT and DCT / D. Lau ; A. Schneider ; M.D. Ercegovac |
| An FPGA-based Fan Beam Image Reconstruction Module / L. Maltar ; F.M.G. Franca ; V.C. Alves ; C.L. Amorim |
| Bezier Curve Rendering on Virtex / D. MacVicar ; R. Slous |
| Author Index |
| Co-Chairs and Program Committee |
| Tools 1 / Session 1： |
| Macro-Based Hardware Compilation of Java Bytecodes into a Dynamic Reconfigurable Computing System / J.M.P. Cardoso ; H.C. Neto |
図書
