| Plenary Talks |
| Reconfigurable Computing for High Performance Networking Applications / Gordon Brebner |
| Biologically-Inspired Massively-Parallel Architectures: A Reconfigurable Neural Modelling Platform / Steve Furber |
| Reconfigurable Accelerators I |
| A Reconfigurable Audio Beamforming Multi-Core Processor / Dimitris Theodoropoulos ; Georgi Kuzmanov ; Georgi Gaydadjiev |
| A Regular Expression Matching Circuit Based on a Decomposed Automaton / Hiroki Nakahara ; Tsutomu Sasao ; Munehiro Matsuura |
| Design and Implementation of a Multi-Core Crypto-Processor for Software Defined Radios / Michael Grand ; Lilian Bossuet ; Bertrand Le Gal ; Guy Gogniat ; Dominique Dallet |
| Design Tools |
| Application Specific Memory Access, Reuse and Reordering for SDRAM / Samuel Bayliss ; George A. Constantinides |
| Automatic Generation of FPGA-Specific Pipelined Accelerators / Christophe Alias ; Bogdan Pasca ; Alexandru Plesco |
| HLS Tools for FPGA: Faster Development with Better Performance / Alexandre Cornu ; Steven Derrien ; Dominique Lavenier |
| Posters 1 |
| A (Fault-Tolerant)2 Scheduler for Real-Time Hw Tasks / Xabier Iturbe ; Khaled Benkrid ; Tughrul Arslan ; Mikel Azkarate ; Imanol Martinez |
| A Compact Gaussian Randon Number Generator for Small Word Lengths / Subhasis Das ; Sachin Patkar |
| Accurate Floating Point Arithmetic through Hardware Error-Free Transformations / Manouk V. Manoulkian |
| Active storage Networks for Acceleratinog K-Means Data Clustering / Janardhan Singaraju ; John A. Chandy |
| An FPGA Implementation for Texture Analysis Considering the Real-Time Requirements of Vision-Based Systems / Mario-Alberto ; Ibarra-Manzano ; Dora-Luz ; Almanza-Ojeda |
| CReAMS: An Embedded Multiprocessor Platform / Mateus B. Rutzig ; Antonio Carlos S. Beck ; Luigi Carro |
| Dataflow Graph Partitioning for Optimal Spatio-Temporal Computation on a Coarse Grain Recofigurable Architecture / Ratna Krishnamoorthy ; Keshavan Varadarajan ; Masahiro Fujita ; Mythri Alle ; S.K. Nandy ; Ranjani Narayan |
| Reconfigurable Processors |
| A Pipeline Interleaved Heterogeneous SIMD Soft Processor Array Architecture for MIMO-OFDM / Xuezheng Chu ; John McAlister ; Roger Woods |
| Design Implementation, and Verification of an Adaptable Processor in Lava HDL / Stefan Schulze ; Sergei Sawitzki |
| Towards an Adaptable Multiple-ISA Reconfigurable Processor / Jair Fajardo Junior ; Antonio Carlos S. ; Beck |
| Applications |
| FPGA-Based Cherenkov Ring Rcognition in Nuclear and Particle Physics Experiments / Ming Liu ; Zhonghai Lu ; Wolfgang Kuehn ; Axel Jantsch |
| Waync Luk / Yoshiki Yamaguchi ; Hung Kuen Tsoi |
| Index to Constant Weight Codeword Converter / Jon T. Butler |
| On-Chip Ego-Motion Estimation Based on Optical Flow / Mauricio Vanegas ; Leonardo Rubio ; Matteo Tomasi ; Javier Diaz ; Eduardo Ros |
| Device Architecture |
| Comparison between Heterogeneous Mesh-Based and Tree-Based Application Specific FPGAa / Umer Farooq ; Husain Parvez ; Zied Marrakchi ; Habib Mehrez |
| Dynamic VDD Switching Technique and Mapping Optimization in Dynamically Reconfigurable Processor for Efficient Energy Reduction / Tatsuya Yamamoto ; Kazuei Hironaka ; Yuki Hayakawa ; Masayuki Kimura ; Hideharu Amano ; Kimiyoshi Usami |
| MEMS Interleaving Read Operation of a Holographic Memory for Optically Reconfigurable Gate Arrays / Hironobu Morita ; Minoru Watanabe |
| Posters 2 |
| FaRM: Fast Reconfiguration Manager for Reducing Reconfiguration Time Overhead on FPGA / François Duhem ; Fabrice Muller ; Philippe Lorenzini |
| Feasibility Analysis of Reconfigurable Computing in Low-Power Wireless Sensor Applications / Andreas Engel ; Björn Liebig ; Andreas Koch |
| Hierarchical Optical Flow Estimation Architecture Using Color Cues / Francisco Barranco |
| Magnetic Look-Up Table (MLUT) Featuring Radiation Hardness, High Performance and Low power / Yahya Lakys ; Weisheng Zhao ; Jacques-Olivier Klein ; Claude Chappert |
| Reconfigurable Stream-Processing Architecture for Sparse Linear Solvers / Kevin Cunningham ; Prawat Naguajara |
| The Krawczyk Algorithm: Rigorous Bounds for Linear Equation Solution on an FPGA / Christophe Le Lann ; David Boland ; George Constantinides |
| A Dynamic Reconfigurable CPLD Architecture for Structured ASIC Technology / Traian Tulbure |
| Reconfigurable Accelerators II |
| FPGA Accelerated Parallel Sparse Matrix Factorization for Circuit Simulations / Wei Wu ; Yi Shan ; Xiaoming Chen ; Yu Wang ; Huazhong Yang |
| FPGA Optimizations for a Pipelined Floating-Point Exponential Unit / Nikolaos Alachiotis ; Alexandros Stamatakis |
| NetStage/DPR: A Self-adaptable FPGA Platform for Application-Level Network Security / Sascha Muhlbach |
| Methodology and Simulation |
| A Correlation Power Analysis Attack against Tate Pairing on FPGA / Weibo Pan ; William P. Marnane |
| From Plasma to BeeFarm: Design Experience of an FPGA-Based Multicore Prototype / Nehir Sonmez ; Oriol Arcas ; Gokhan Sayilar ; Osman S. Unsal ; Adrián Cristal ; Ibrahim Hur ; Satnam Singh ; Mateo Valero |
| System Architecture |
| Architectural Support for Multithreading on Reconfigurable Hardware / Pavel G. Zaykov |
| High Performance Programmable FPGA Overlay for Digital Signal Processing / Seamas McGettrick ; Kunjan Patel ; Chris Bleakley |
| Secure Virtualization within a Multi-processor Soft-Core System-en-Chip Architecture / Alexander Biedermann ; Marc Stöttinger ; Lijing Chen ; Sarin A.Huss |
| Author Index |
| Plenary Talks |
| Reconfigurable Computing for High Performance Networking Applications / Gordon Brebner |
| Biologically-Inspired Massively-Parallel Architectures: A Reconfigurable Neural Modelling Platform / Steve Furber |
