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図書
1. Proceedings, 17th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2002, 6-8 November 2002, Vancouver, BC, Canada
[sponsored by the IEEE Computer Society Test Technology Technical Council, the IEEE Computer Society Technical Committee on Fault-Tolerant Computing]
出版情報: Los Alamitos, Calif. : IEEE Computer Society, c2002  xiii, 441 p. ; 23 cm
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Message from the Symposium Chairs
Organizing Committee
Program Committee
Yield I / Session 1：
Manufacturability Analysis of Analog CMOS ICs Through Examination of Multiple Layout Solutions / P. Khademsameni ; M. Syrzycki
Effect of Static Power Dissipation in Burn-In Environment on Yield of VLSI / A. Vassighi ; O. Semenov ; M. Sachdev ; A. Keshavarzi
Yield Estimates for the TESH Multicomputer Network / B. M. Maziarz ; V. K. Jain
Crosstalk Faults / Session 2：
A Simplified Gate-Level Fault Model for Crosstalk Effects Analysis / P. Civera ; L. Macchiarulo ; M. Violante
A Test-Vector Generation Methodology for Crosstalk Noise Faults / H. Hashempour ; Y.-B. Kim ; N. Park
Self-Checking and ABFT / Session 3：
A Parity Code Based Fault Detection for an Implementation of the Advanced Encryption Standard / G. Bertoni ; L. Breveglieri ; I. Koren ; P. Maistri ; V. Piuri
Designing Self-Checking FPGAs Through Error Detection Codes / C. Bolchini ; F. Salice ; D. Sciuto
Self-Checking 1-out-of-n CMOS Current-Mode Checker / J. Mathew ; E. Dubrova
Partially Duplicated Code-Disjoint Carry-Skip Adder / D. Marienfeld ; V. Ocheretnij ; M. Gossel ; E. S. Sogomonyan
Input Ordering in Concurrent Checkers to Reduce Power Consumption / K. Mohanram ; N. A. Touba
Fault Simulation and Injection I / Session 4：
New Methods for Evaluating the Impact of Single Event Transients in VDSM ICs / D. Alexandrescu ; L. Anghel ; M. Nicolaidis
Injecting Bit Flip Faults by Means of a Purely Software Approach: A Case Studied / R. Velazco ; A. Corominas ; P. Ferreyra
Gate-Delay Fault Diagnosis Using the Inject-and-Evaluate Paradigm / H.-B. Wang ; S.-Y. Huang ; J.-R. Huang
Scan Design / Session 5：
Scan Architecture for Shift and Capture Cycle Power Reduction / P. M. Rosinger ; B. M. Al-Hashimi ; N. Nicolici
Inserting Test Points to Control Peak Power During Scan Testing / R. Sankaralingam
Adaptable Voltage Scan Testing of Charge-Sharing Faults for Domino Circuits / C.-H. Cheng
Test Application / Session 6：
Matrix-Based Test Vector Decompression Using an Embedded Processor / K. J. Balakrishnan
Data Compression for System-on-Chip Testing Using ATE / F. Karimi ; W. Meleis ; Z. Navabi ; F. Lombardi
Test Generation / Session 7：
Fortuitous Detection and Its Impact on Test Set Sizes Using Stuck-At and Transition Faults / J. Dworak ; J. Wingfield ; B. Cobb ; S. Lee ; L.-C. Wang ; M. R. Mercer
Test Time Reduction in a Manufacturing Environment by Combining BIST and ATE / F. J. Meyer
Testing Digital Circuits with Constraints / A. A. Al-Yamani ; S. Mitra ; E. J. McCluskey
Concurrent Error Detection / Session 8：
On-Line Testing of Transient Faults Affecting Functional Blocks of FCMOS, Domino and FPGA-Implemented Self-Checking Circuits / C. Metra ; S. Di Francescantonio ; G. Marrale
Self-Checking and Fault Tolerance Quality Assessment Using Fault Sampling / F. M. Goncalves ; M. B. Santos ; I. C. Teixeira ; J. P. Teixeira
A Memory Overhead Evaluation of the Interleaved Signature Instruction Stream / F. Rodriguez ; J. C. Campelo ; J. J. Serrano
Fault-Tolerant CAM Architectures: A Design Framework / M. G. Sami ; R. Stefanelli
Fault Simulation and Injection II / Session 9：
Using Run-Time Reconfiguration for Fault Injection in Hardware Prototypes / L. Antoni ; R. Leveugle ; B. Feher
A Fault Hypothesis Study on the TTP/C Using VHDL-Based and Pin-Level Fault Injection Techniques / S. Blanc ; J. Gracia ; P. J. Gil
Fault List Compaction Through Static Timing Analysis for Efficient Fault Injection Experiments / M. Sonza Reorda
Interconnect / Session 10：
Performance of Deadlock-Free Adaptive Routing for Hierarchical Interconnection Network TESH / S. Horiguchi ; Y. Miura
Modeling of FPGA Local/Global Interconnect Resources and Derivation of Minimal Test Configurations / X. Sun ; A. Alimohammad ; P. Trouborst
Testing Layered Interconnection Networks
Yield II / Session 11：
Repair Yield Simulation with Iterative Critical Area Analysis for Different Types of Failure / Y. Hamamura ; K. Nemoto ; T. Kumazawa ; H. Iwata ; K. Okuyama ; S. Kamohara ; A. Sugimoto
Yield Modeling of a WSI Telcom Router Architecture / B. Qiu ; Y. Savaria ; M. Lu ; C. Wang ; C. Thibeault
System-on-Chip Test / Session 12：
Fast and Energy-Frugal Deterministic Test Through Test Vector Correlation Exploitation / O. Sinanoglu ; A. Orailoglu
Adaptive Test Scheduling in SoC's by Dynamic Partitioning / D. Zhao ; S. Upadhyaya
Feasibility of CED / Session 13：
Duplication-Based Concurrent Error Detection in Asynchronous Circuits: Shortcomings and Remedies / T. Verdel ; Y. Makris
Feasibility Study of Designing TSC Sequential Circuits with 100% Fault Coverage / S. J. Piestrak
Test / Session 14：
Emulation-Based Design Errors Identification / A. CasteInuovo ; A. Fin ; F. Fummi ; F. Sforza
A New Functional Fault Model for FPGA Application-Oriented Testing / M. Rebaudengo
Neighbor Current Ratio (NCR): A New Metric for I[subscript DDQ] Data Analysis / S. S. Sabade ; D. M. H. Walker
CMOS Standard Cells Characterization for I[subscript DDQ] Testing / W. A. Pleskacz ; T. Borejko ; W. Kuzmicz
On-Chip Jitter Measurement for Phase Locked Loops / T. Xia ; J.-C. Lo
Neural Networks-Based Parametric Testing of Analog IC / V. Stopjakova ; D. Micusik ; L. Benuskova ; M. Margala
Reliable and Repairable Memories / Session 15：
Balanced Redundancy Utilization in Embedded Memory Cores for Dependable Systems / M. Choi ; Y. B. Kim
Repairability Evaluation of Embedded Multiple Region DRAMs / Y. Chang
Author Index
TTTC Information
Message from the Symposium Chairs
Organizing Committee
Program Committee
2.

図書
図書
2. Records of the 2003 International Workshop on Memory Technology, Design and Testing, 28-29 July 2003, San Jose, California
sponsored by IEEE Computer Society, IEEE Computer Society Technical Committee on VLSI, IEEE Computer Society Technical Council on Test Technology ; in cooperation with IEEE Solid State Circuits Society ; [edited by Tom Wik, Adit Singh, and Rochit Rajsuman]
出版情報: Los Alamitos, Calif. : IEEE Computer Society, c2003  ix, 95 p. ; 28 cm
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3.

図書
図書
3. Proceedings, 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 3-5 November 2003, Boston, Massachusetts
[edited by C. Bolchini ... [et al.] ] ; sponsored by the Counci the IEEE Computer Society Technical Committee on Fault-Tolerant Computing, IEEE Computer Society Test Technology Technicall
出版情報: Los Alamitos, Calif. : IEEE Computer Society, c2003  xii, 607 p. ; 23 cm
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Message from the Symposium Chairs
Committees
Yield and Defects / Session 1：
Yield Analysis of Compiler-Based Arrays of Embedded SRAMs / X. Wang ; M. Ottavi ; F. Lombardi
Reliability Estimation Model of IC's Interconnect Based on Uniform Distribution of Defects on a Chip / T. Zhao ; X. Duan ; Y. Hao
IEEE 1149.1 Based Defect and Fault Tolerant Scan Chain for Wafer Scale Integration / M. Lu ; Y. Savaria ; B. Qiu ; J. Taillefer
Calibration of Open Interconnect Yield Models / D. de Vries ; P. Simon
Yield Modeling and Analysis of a Clockless Asynchronous Wave Pipeline with Pulse Faults / T. Feng ; N. Park ; Y. Kim ; V. Piuri
Optoelectronics / Session 2：
Level-Hybrid Optoelectronic TESH Interconnection Network / V. Jain ; G. Chapman
Implementation and Testing of Fault-Tolerant Photodiode-Based Active Pixel Sensor (APS) / S. Djaja ; D. Cheung ; Y. Audet
Fault Analysis, Injection & Simulation / Session 3：
Clock Calibration Faults and Their Impact on Quality of High Performance Microprocessors / C. Metra ; T. Mak ; D. Rossi
A Tool for Injecting SEU-Like Faults into the Configuration Control Mechanism of Xilinx Virtex FPGAs / M. Alderighi ; F. Casini ; S. D'Angelo ; M. Mancini ; A. Marmo ; S. Pastore ; G. Sechi
CodSim--A Combined Delay Fault Simulator / W. Qiu ; X. Lu ; Z. Li ; D. Walker ; W. Shi
Test & Diagnosis / Session 4：
BIST Based Fault Diagnosis Using Ambiguous Test Set / H. Takahashi ; Y. Tsugaoka ; H. Ayano ; Y. Takamatsu
On the Test and Diagnosis of the Perfect Shuffle / L. Schiano
Detecting and Locating Faults in VLSI Implementations of the Advanced Encryption Standard / G. Bertoni ; L. Breveglieri ; I. Koren ; P. Maistri
Current Test & Diagnosis / Session 5：
3DSDM: A 3 Data-Source Diagnostic Method / Y. Hariri ; C. Thibeault
Power Supply Current Test Approach for Resistive Fault Screening in Embedded Analog Circuits / M. Dragic ; M. Margala
CROWNE: Current Ratio Outliers with Neighbor Estimator / S. Sabade
Chip Level Power Supply Partitioning for I[subscript DDQ] Testing Using Built-In Current Sensors / A. Prasad
Test Generation & Application / Session 6：
ATE-Amenable Test Data Compression with No Cyclic Scan Registers / H. Hashempour
A Digital and Wide Power Bandwidth H-Field Generator for Automatic Test Equipment / F. Zhang ; Y. Lee ; T. Kane ; M. Momenzadeh ; Y.-B. Kim ; F. Meyer ; S. Max ; P. Perkinson
Function-Based Dynamic Compaction and Its Impact on Test Set Sizes / J. Wingfield ; J. Dworak ; M. Mercer
Constrained ATPG for Broadside Transition Testing / X. Liu ; M. Hsiao
Scan Design & Test / Session 7：
Test Compaction by Using Linear-Matrix Driven Scan Chains / S. Bhatia
Multiple Scan Chain Design Technique for Power Reduction during Test Application in BIST / D. Ghosh ; S. Bhunia ; K. Roy
Design Scan Test Strategy for Single Phase Dynamic Circuits / C.-H. Cheng
BIST / Session 8：
Scan-Based BIST Diagnosis Using an Embedded Processor / K. Balakrishnan ; N. Touba
Hybrid BIST Using an Incrementally Guided LFSR / C. Krishna
Hybrid BIST Time Minimization for Core-Based Systems with STUMPS Architecture / G. Jervan ; P. Eles ; Z. Peng ; R. Ubar ; M. Jenihhin
Error Correcting Codes / Session 9：
A Single Error Correcting and Double Error Detecting Coding Scheme for Computer Memory Systems / P. Lala
Array Codes Correcting a Cluster of Unidirectional Errors for Two-Dimensional Matrix Symbols / H. Kaneko ; E. Fujiwara
Quadruple Time Redundancy Adders / W. Townsend ; J. Abraham ; E. Swartzlander, Jr.
Error Correcting Codes for Crosstalk Effect Minimization / S. Cavallotti
Invited Talk
A View from the Bottom: Nanometer Technology AC Parametric Failures--Why, Where, and How to Detect / C. Hawkins ; A. Keshavarzi ; J. Segura
Analogue & Mixed Signal Test / Session 10：
Analysis and Testing of Analog and Mixed-Signal Circuits by an Operation-Region Model: A Case Study of Application and Implementation / Y. Miura ; D. Kato
An Approach for Selection of Test Points for Analog Fault Diagnosis / K. Pinjala ; B. Kim
BiST Model for IC RF-Transceiver Front-End / J. Dabrowski
A Monolithic Spectral BIST Technique for Control or Test of Analog or Mixed-Signal Circuits / J. Emmert ; J. Cheatham ; B. Jagannathan ; S. Umarani
Defect Tolerance and Testing / Session 11：
Thermal Management of High Performance Microprocessors in Burn-In Environment / A. Vassighi ; O. Semenov ; M. Sachdev
Fault Recovery Based on Checkpointing for Hard Real-Time Embedded Systems / Y. Zhang ; K. Chakrabarty
Fault Tolerant Multi-layer Neural Networks with GA Training / E. Sugawara ; M. Fukushi ; S. Horiguchi
Detailed Comparison of Dependability Analyses Performed at RT and Gate Levels / A. Ammari ; R. Leveugle ; M. Sonza-Reorda ; M. Violante
Low Cost Convolutional Code Based Concurrent Error Detection in FSMs / K. Rokas ; Y. Makris ; D. Gizopoulos
Reducing Test Power, Time and Data Volume in SoC Testing Using Selective Trigger Scan Architecture / S. Sharifi ; M. Hosseinabadi ; P. Riahi ; Z. Navabi
An FFT Approximation Technique Suitable for On-Chip Generation and Analysis of Sinusoidal Signals
Fault Tolerant Hopfield Associative Memory on Torus / R. Ayoubi ; H. Ziade ; M. Bayoumi
Efficiency of Transient Bit-Flips Detection by Software Means: A Complete Study / B. Nicolescu ; P. Peronnard ; R. Velazco
Buffer and Controller Minimisation for Time-Constrained Testing of System-On-Chip / A. Larsson ; E. Larsson
Regressive Testing for System-on-Chip with Unknown-Good-Yield / N.-J. Park ; B. Jin ; K. George ; M. Choi
Error Detection in Signed Digit Arithmetic Circuit with Parity Checker / G. Cardarilli ; S. Pontarelli ; M. Re ; A. Salsano
Application-Dependent Testing of FPGA Interconnects / M. Tahoori
Automatic Modification of Sequential Circuits for Self-Checking Implementation / S. Di Francescantonio ; M. Omana
Control Constrained Resource Partitioning for Complex SoCs / D. Zhao ; S. Upadhyaya
Partial Error Masking to Reduce Soft Error Failure Rate in Logic Circuits / K. Mohanram
FPGA & Memory Test / Session 12：
An Integrated Design Approach for Self-Checking FPGAs / C. Bolchini ; F. Salice ; D. Sciuto ; R. Zavaglia
Power-Constrained Embedded Memory BIST Architecture / B. Fang ; N. Nicolici
A Memory Built-In Self-Repair for High Defect Densities Based on Error Polarities / M. Nicolaidis ; N. Achouri ; L. Anghel
Redundancy, Repair, and Test Features of a 90nm Embedded SRAM Generator / R. Aitken ; N. Dogra ; D. Gandhi ; S. Becker
An Efficient Functional Test for the Massively-Parallel C-RAM Logic-Enhanced Memory Architecture / X. Sun ; B. Cockburn ; D. Elliott
Design Verification & Synthesis / Session 13：
Dependability Analysis Using a Fault Injection Tool Based on Synthesizability of HDL Models / H. Zarandi ; S. Miremadi ; A. Ejlali
Preliminary Validation of an Approach Dealing with Processor Obsolescence / S. Saleh ; S. Deswaertes ; A. El Moucary
SoC & Core Test / Session 14：
Efficient Test Data Decompression for System-on-a-Chip Using an Embedded FPGA Core / G. Zeng ; H. Ito
A Unified SoC Test Approach Based on Test Data Compression and TAM Design / V. Iyengar ; A. Chandra
Embedded Compact Deterministic Test for IP-Protected Cores / A. Kinsman ; J. Hewitt
System Reliability / Session 15：
System-Level Analysis of Fault Effects in Automotive Environment / F. Corno ; S. Tosato ; P. Gabrielli
Dependability Analysis of CAN Networks: An Emulation-Based Approach / J. Perez ; M. Sonza Reorda
Fault Tolerance / Session 16：
Exploiting Instruction Redundancy for Transient Fault Tolerance / T. Sato
An Integrated Fault-Tolerant Design Framework for VLIW Processors / Y.-Y. Chen ; S.-J. Horng ; H.-C. Lai
Fault Tolerant Design of Combinational and Sequential Logic Based on a Parity Check Code / S. Almukhaizim
Heterogeneous Redundancy for Fault and Defect Tolerance with Complexity Independent Area Overhead / V. Kumar ; J. Lach
Soft Errors / Session 17：
Soft-Error Detection Using Control Flow Assertions / O. Goloubeva ; M. Rebaudengo
SIED: Software Implemented Error Detection
Techniques for Transient Fault Sensitivity Analysis and Reduction in VLSI Circuits / A. Maheshwari ; W. Burleson
Author Index
Message from the Symposium Chairs
Committees
Yield and Defects / Session 1：
4.

図書
図書
4. Proceedings of the 2002 IEEE International Workshop on Memory Technology, Design and Testing : (MTDT 2002) : 10-12 July, 2002, Isle of Bendor, France (: bookbroker)
editors, Bernard Courtois, Thomas Wik, Yervant Zorian ; sponsored by IEEE Computer Society, IEEE Computer Society Technical Council on Test Technology, IEEE Computer Society Technical Committee on VLSI ; in cooperation with IEEE Solid-State Circuits Society
出版情報: Los Alamitos, Calif. : IEEE Computer Society, c2002  xii, 182 p. ; 28 cm
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Message from the Chairs
Conference Committee
TTTC Information
Joint Session with The Eighth IEEE International On-Line Testing Workshop (IOLTW 2002)
Plenary Session / Session A：
Keynote Address: Embedded Memory Test and Repair / A. Kablanian
Memory BIST Analysis and Application / Session B：
Defect-Oriented Analysis of Memory BIST Tests / A. Jee
A BIST-Based Solution for the Diagnosis of Embedded Memories Adopting Image Processing Techniques / D. Appello ; A. Fudoli ; V. Tancorre ; F. Corno ; M. Rebaudengo ; M. Sonza Reorda
A Scan-Bist Environment for Testing Embedded Memories / F. Karimi ; F. Lombardi
Memory ECC and Soft Errors / Session C：
Soft Error Protection for Embedded Memories / M. Nicolaidis
Fast and Compact Error Correcting Scheme for Reliable Multilevel Flash Memories / D. Rossi ; C. Metra ; B. Ricco
High Speed 15 ns 4 Mbits SRAM for Space Application / B. Coloma ; P. Delaunay ; O. Husson
High Reliability in Railway and Automotive Systems / Session D：
The YATE Fail-Safe Interface: The User's Point of View / D. Bied-Charreton ; D. Guillon ; B. Jacques
Fault Tolerant Insertion and Verification: A Case Study / A. Manzone ; D. De Costantini
Design and Implementation of a Self-Checking Scheme for Railway Trackside Systems / L. Schiano ; D. Marino
Embedded Memory Yield Enhancement / Session E：
A Silicon-Based Yield Gain Evaluation Methodology for Embedded-SRAMs with Different Redundancy Scenarios / E. Rondey ; Y. Tellier ; S. Borri
A March-Based Fault Location Algorithm for Static Random Access Memories / V. A. Vardanian ; Y. Zorian
A Simulator for Evaluating Redundancy Analysis Algorithms of Repairable Embedded Memories / R.-F. Huang ; J.-F. Li ; J.-C. Yeh ; C.-W. Wu
MTDT
Keynote Address: Challenges and Opportunities Created by the SoC Shockwave / M. Templeton
Embedded Memory Systems and Test Optimization / Session 1：
Design and Test of a 9-Port SRAM for a 100 Gb/s STS-1 Switch / R. Gibbins ; R. D. Adams ; T. Eckenrode ; M. Ouellette ; Y. Wu
Design of Embedded System for Video Coding with Logic-Enhanced DRAM and Configurable Process / T. Kaya ; I. Shirakawa ; R. Miyamoto ; T. Onoye
Adder Merged DRAM Architecture / M. Hashimoto
Memory Test Strategies / Session 2：
March SS: A Test for All Static Simple RAM Faults / S. Hamdioui ; A. J. van de Goor ; M. Rodgers
Random Testing of Multi-Port Static Random Access Memories / F. J. Meyer
Fault Modeling / Session 3：
A Fault Modeling Technique to Test Memory BIST Algorithms / R. Venkatesh ; S. Kumar ; J. Philip ; S. Shukla
Fault Modeling and Pattern-Sensitivity Testing for a Multilevel DRAM / M. Redeker ; B. F. Cockburn ; D. G. Elliott ; Y. Xiang ; S. A. Ung
An Investigation into Crosstalk Noise in DRAM Structures
Embedded Memory Compiler Tutorial / Session 4：
Keynote Address: SoC's Trends and Challenges going to 0.10 [mu]m / P. Magarshack
EPROM/EEPROM Design / Session 5：
An Automated Design Methodology for EEPROM Cell (ADE) / J. M. Portal ; L. Forli ; H. Aziza ; D. Nee
A Novel Memory Array Based on an Annular Single-Poly EPROM Cell for Use in Standard CMOS Technology / C. Dray ; P. Gendrier
A New Single Ended Sense Amplifier for Low Voltage Embedded EEPROM Non Volatile Memories / C. Papaix ; J. M. Daga
Process Technology and Reliability / Session 6：
Validated 90 nm CMOS Technology Platform with Low-k Copper Interconnects for Advanced System-on-Chip (SoC) / T. Devoivre ; M. Lunenborg ; C. Julien ; J-P. Carrere ; P. Ferreira ; W. J. Toren ; A. VandeGoor ; P. Gayet ; T. Berger ; O. Hinsinger ; P. Vannier ; Y. Trouiller ; Y. Rody ; P-J. Goirand ; R. Palla ; I. Thomas ; F. Guyader ; D. Roy ; B. Borot ; N. Planes ; S. Naudet ; F. Pico ; D. Duca ; F. Lalanne ; D. Heslinga ; M. Haond
Converting an Embedded Low-Power SRAM from Bulk to PD-SOI / M. R. Casu ; P. Flatresse
Decreasing EEPROM Programming Bias with Negative Voltage, Reliability Impact / R. Laffont ; J. Razafindramora ; P. Canet ; R. Bouchakour ; J. M. Mirabel
Advanced Memory Technologies Panel / Session 7：
Panel on Advanced Embedded Memory Technologies
Author Index
Message from the Chairs
Conference Committee
TTTC Information
5.

図書
図書
5. Proceedings, IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 25-27 October, 2000, Yamanashi, Japan (: case)
sponsored by IEEE Computer Society, IEEE Computer Society Technical Committee on Fault-Tolerant Computing, IEEE Computer Society Test Technology Technical Committee ; in cooperation with Technical Group on Fault Torerant Systems, IEICE, Japan
出版情報: Los Alamitos, CA. : IEEE Computer Society, c2000  xii, 422 p. ; 23 cm
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Message from the Symposium Chairpersons
Organizing Committee
Yield Analysis and Modeling / Session 1：
The Effect of Placement on Yield for Standard Cell Designs / R. Prasad ; I. Koren
IC Critical Volume Calculation through Ray-Casting of CSG Trees / M. Moran ; G. Allan
A New Defect Outline Model Used for Critical Area Estimation in VLSI / X. Jiang ; Y. Hao ; S. Horiguchi
Predicting the Yield Efficacy of a Defect-Tolerant Embedded Core / F. Meyer ; N. Park
Yield Enhancement Techniques / Session 2：
VLSI Yield Optimization Based on the Sub-Processing-Element Level Redundancy / T. Zhao ; Y. Jiao
Quality-Effective Repair of Multichip Module Systems / F. Lombardi
A Self-Correcting Active Pixel Camera / G. Chapman ; Z. Koren
Wafer Scale/Large Area Systems / Session 3：
Introduction to Special Session
A High Speed and High Fault Tolerant Reconfigurable Reasoning System: Toward a Wafer Scale Reconfigurable Reasoning LSI / M. Yasunaga ; I. Yoshihara ; J. Kim
Self-Configuration of a Large Area Integrated Multiprocessor System for Video Applications / M. Rudack ; M. Redeker ; D. Treytnar ; O. Mende ; K. Herrmann
A Reconfigurable WSI Massively Data-Parallel Processing Device for Cost-Effective 3D Sensor Data Processing / R. Lea ; P. Tetnowski ; M. Covic
Optimization of Wafer Scale H-Tree Clock Distribution Network Based on a New Statistical Skew Model
Implementation of a Multiprocessor System with Distributed Embedded DRAM on a Large Area Integrated Circuit / S. Moch ; J. Hilgenstock ; P. Pirsch
A Multifunctional Laser Linking and Cutting Structure for Standard 0.25 [mu]m CMOS-Technology
Fault-Tolerant Interconnections / Session 4：
On the Complexity of Switch Programming in Fault-Tolerant Configurable Chips / W. Shi ; K. Kumar
Design of Switching Blocks Tolerating Defects/Faults in FPGA Interconnection Resources / A. Doumar ; H. Ito
Design of a Fault Tolerant Multistage Interconnection Network with Parallel Duplicated Switches / N. Kamiura ; T. Kodera ; N. Matsui
Fault-Tolerant Systems / Session 5：
Achieving Fault-Tolerance by Shifted and Rotated Operands in TMR Non-Diverse ALUs / M. Alderighi ; S. D'Angelo ; C. Metra ; G. Sechi
Fault-Tolerant High-Performance Cordic Processors / J.-H. Kwak ; V. Piuri ; E. Swartzlander, Jr.
A Fault-Tolerant 176 Gbit Solid State Mass Memory Architecture / G. Cardarilli ; P. Marinucci ; M. Ottavi ; A. Salsano
Error Coding / Session 6：
Evaluations of Burst Error Recovery for VF Arithmetic Coding / M. Kitakami ; H. Chen ; E. Fujiwara
Single Byte Error Control Codes with Double Bit within a Block Error Correcting Capability for Semiconductor Memory Systems / G. Umanesan
Efficient Error Correction Code Configurations for Quasi-Nonvolatile Data Retention by DRAMs / Y. Katayama ; Y. Negishi ; S. Morioka
Reconfiguration and Repair / Session 7：
Built-In Self-Reconfiguring Systems for Mesh-Connected Processor Arrays with Spares on Two Rows/Columns / I. Takanami
Fault-Tolerant Ring-and Toroidal Mesh-Connected Processor Arrays Able to Enhance Emulation of Hypercubes / N. Tsuda
Self-Repairing in a Micro-Programmed Processor for Dependable Applications / A. Benso ; S. Chiusano ; P. Prinetto ; P. Simonotti ; G. Ugo
Self-Reconfigurable Mesh Array System on FPGA / M. Fukushi
Online Testing / Session 8：
How Does Resource Utilization Affect Fault Tolerance? / C. Scherrer ; A. Steininger
An Experimental Evaluation of the Effectiveness of Automatic Rule-Based Transformations for Safety-Critical Applications / M. Rebaudengo ; M. Reorda ; M. Torchiano ; M. Violante
Synthesis of On-Line Testing Control Units: Flow Graph Coding/Monitoring Approach / S. Demidenko ; E. Levine
An On-Line Reconfigurable FPGA Architecture / P. Lala ; A. Walker
Built-In Self-Test / Session 9：
Test Cost Minimization for Hybrid BIST / G. Jervan ; Z. Peng ; R. Ubar
BIST Architectures Selection Based on Behavioral Testing / G. Biasoli ; F. Ferrandi ; A. Fin ; F. Fummi ; D. Sciuto
Brains: A BIST Compiler for Embedded Memories / C. Cheng ; C.-T. Huang ; J.-R. Huang ; C.-W. Wu ; C.-J. Wey ; M.-C. Tsai
Testing Strategies / Session 10：
Testing the Configurability of Dynamic FPGAs / S. Ruiwale
Design for Testability to Achieve High Test Coverage--A Case Study / S. Mukherjee
Low-Speed Scan Testing of Charge-Sharing Faults for CMOS Domino Circuits / C. Chen ; W. Jone ; J. Wang ; S. Chang
Path Delay Fault Testability Analysis / J. Sosnowski ; T. Wabia ; T. Bech
I[subscript DDQ] Testing / Session 11：
Threshold Voltage and Power-Supply Tolerance of CMOS Logic Design Families / M. Kishor ; J. de Gyvez
A New Light-Based Logic IC Screening Method / S. Ohnishi ; M. Nishihara
Testability Analysis of I[subscript DDQ] Testing with Large Threshold Value / M. Hashizume ; H. Yotsuyanagi ; T. Tamesada ; M. Takeda
The 2nd Order Analysis of I[subscript DDQ] Test Data / S. Li ; K. Zhang ; J.-C. Lo
Fault Injection / Session 12：
"BOND": An Interposition Agents Based Fault Injector for Windows NT / A. Baldini
A Prototype of a VHDL-Based Fault Injection Tool / J. Baraza ; J. Gracia ; D. Gil ; P. Gil
Using Run-Time Reconfiguration for Fault Injection in Hardware Prototypes / L. Antoni ; R. Leveugle ; B. Feher
Fault Injection in VHDL Descriptions and Emulation
Author Index
Message from the Symposium Chairpersons
Organizing Committee
Yield Analysis and Modeling / Session 1：
6.

図書
図書
6. Records of the 2000 IEEE International Workshop on Memory Technology, Design and Testing, August 7-8, 2000, San Jose, California, USA (:case.)
edited by R. Rajsuman, T. Wik ; sponsored by IEEE Computer Society, IEEE Computer Society Technical Committee on VLSI, IEEE Computer Society Technical Council on Test Technology ; in cooperation with The IEEE Solid State Circuits Society
出版情報: Los Alamitos, Calif. : Institute of Electrical and Electronics Engieers, c2000  x, 131 p. ; 28 cm
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Message from the General Chair
Message from the Technical Program Chair
Conference Committee
Plenary Session
Welcome Message / R. Rajsuman, General Chair
Program Introduction / T. Wik, Program Chair
Keynote Address
Key Trends in Memory Applications and Impact on Memory Technology and Design / Dr. Handel Jones
Failure Mechanism/Defects / Betty PrinceSession 1：
Failure Mechanisms in Semiconductor Memory Circuits / R. Haythornthwaite
Diagnosing the Interconnect of Bus-Connected Multi-RAM Systems under Restricted and General Fault Models / J. Zhao ; F. Meyer ; F. Lombardi
Optimizing Memory Tests by Analyzing Defect Coverage / A. Jee ; J. Colburn ; V. Irrinki ; M. Puri
Flash/EEPROM Design / Alex Shubat ; Virage LogicSession 2：
Hierarchical Sector Biasing Organization for Flash Memories / R. Micheloni ; M. Zammattio ; G. Campardo ; O. Khouri ; G. Torelli
Fast Voltage Regulator for Multilevel Flash Memories / S. Gregori
Design Techniques for Embedded Eeprom Memories in Portable Asic and Assp Solutions / J. Daga ; C. Papaix ; M. Merandat ; S. Ricard ; G. Medulla ; J. Guichaoua ; D. Auvergne
New Ideas / Fabrizio LombardiSession 3：
Windowed Mram Sensing Scheme / R. Zhang ; W. Black, Jr. ; M. Hassoun
Panel: Future Memorq Challenges / Session 4：
Test and Yield / Robert EvansSession 5：
Tutorial: Synchronous Dynamic Memory Test Construction: A Field Approach / J. Vollrath
Yield Analysis Methodology for Low Defectivity Wafer Fabs / K. Rajkanan
Memorq Testing and Built-In Self-Test / Swamy IrrinkiSession 6：
March Tests for Realistic Faults in Two-Port Memories / S. Hamdioui ; M. Rodgers ; Ad J. van de Goor ; D. Eastwick
A Simple Built-In Self Test for Dual Ported SRAMs / K. Truong
Using Glfsrs for Pseudo-Random Memory Bist / M. Redeker ; M. Rudack ; T. Lobbe ; D. Niggemeyer
Invited Rddress
1-T Sram / Fu-Chieh Hsu
Memorq Design / Robert GibbinsSession 7：
Optimizing Meory Bandwidth with ILP Based Memory Exploration and Assignment for Low Power Embedded Systems / W.-T. Shiue
66MHz 2.3M Ternary Dynamic Content Addressable Memory / V. Lines ; A. Ahmed ; P. Ma ; S. Ma ; R. McKenzie ; H.-S. Kim ; C. Mar
A Low Voltage Embedded Single Port Sram Generator in a 0.18[mu]m Standard Cmos Process / C. Frey ; F. Genevaux ; C. Issartel ; D. Turgis ; JP. Schoellkopf
Diagnosis / Sharon MurraySession 8：
Diagnostic Testing of Embedded Memories Based on Output Tracing / E. Rudnick
Defect Analysis and Realistic Fault Model Extensions for Static Random Access Memories / K. Zarrineh ; A. Deo ; R. Adams
Crosstalk in Deep Submicron Drams / Z. Yang ; S. Mourad
Author Index
Message from the General Chair
Message from the Technical Program Chair
Conference Committee
7.

図書
図書
7. Proceedings : International Test Conference 2000, [October 3-5, 2000, New Atlantic City Convention Center, Atlantic City, NJ, USA] (: soft ; : case ; : microfiche)
[sponsored by IEEE Computer Society, Test Technology Technical Council and IEEE Philadelphia Section]
出版情報: Washington, D.C. : International Test Conference, c2000  xiv, 1158 p. ; 29 cm
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8.

図書
図書
8. Proceedings, 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 24-26 October, 2001, San Francisco, California (: case)
sponsored by IEEE Computer Society Technical Committee on Fault-Tolerant Computing, IEEE Computer Society Test Technology Technical Council
出版情報: Los Alamitos, Calif. : IEEE Computer Society, c2001  xiii, 468 p. ; 23 cm
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9.

図書
図書
9. Records of the 2004 International Workshop on Memory Technology, Design and Testing : MTDT 2004 : 9-10 August, 2004, San Jose, California, USA
edited by R. Rajsuman and T. Wik ; sponsored by IEEE Computer Society, IEEE Computer Society Test Technology Technical Council, IEEE Computer Society Technical Committee on VLSI ; in cooperation with IEEE Solid-State Circuits Society
出版情報: Los Alamitos, Calif. : IEEE Computer Society, c2004  vii, 121 p. ; 28 cm
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10.

図書
図書
10. Proceedings 14th Asian Test Symposium, Calcutta, India, December 18-21, 2005
Asian Test Symposium ; IEEE Computer Society ; IEEE Computer Society. Test Technology Technical Council
出版情報: Los Alamitos, Calif. : IEEE Computer Society, c2005  xxxv, 476 p. ; 28 cm
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