Message from the Symposium Chair |
Message from the Co-Chairs |
Reviewers |
Invited Address / Session 1: |
Computational Neurobiology Meets Semiconductor Engineering / D. Hammerstrom |
Neural and Threshold Nets / Session 2a: |
Multi-Valued Logic Pass Gate Network Using Neuron-MOS Transistors / J. Shen ; M. Inaba ; K. Tanno ; O. Ishizuka |
The Synthesis of Multiple-Valued Logic Circuits Using Local-Excitation-Type Neuron Models / M. Matsumoto ; Y. Ueda ; I. Nomoto |
Multi-Input Variable-Threshold Circuits for Multi-Valued Logic Functions / M. Syuto |
The Computing Capacity of Three-Input Multiple-Valued One-Threshold Perceptrons / A. Ngom ; I. Stojmenovic ; R. Tosic |
Spectral Methods / Session 2b: |
MDD-Based Synthesis of Multi-Valued Logic Networks / R. Drechsler ; M. Thornton ; D. Wessels |
Fast Transforms for Multiple-Valued Input Binary Output PLI Logic / B. Falkowski ; S. Rahardja |
Computation of Spectral Information from Logic Netlists |
Fault Analysis of the Multiple Valued Logic Using Spectral Method / J. Kim ; P. Lala ; Y. Kim ; H. Kim |
Neural Networks: Binary Monotonic and Multiple-Valued / J. ZuradaSession 3: |
Decomposition and Data Mining / Session 4a: |
Data Mining of Weak Functional Decompositions / S. Jaroszewicz ; D. Simovici |
Multi-Valued Sub-Function Encoding in Functional Decomposition Based on Information Relationships Measures / A. Chojnacki ; L. Jozwiak |
On the Number of Dependent Variables for Incompletely Specified Multiple-Valued Functions / T. Sasao |
Algebra I / Session 4b: |
Some Properties of Discrete Interval Truth Valued Logic / N. Takagi ; K. Nakashima |
Independence of the Axioms of Boolean Algebra in Multiple-Valued Logic / T. Ninomiya ; M. Mukaidono |
On Urquhart's C Logic / A. Ciabattoni |
Fuzzy Logic / Session 5a: |
A New Class of Fuzzy Modifiers / M. De Cock ; E. Kerre |
Fuzzy Decision Diagrams for the Representation, Analysis and Optimization of Rule Bases / K. Strehl ; C. Moraga ; K.-H. Temme ; R. Stankovic |
On Algebraic Foundations of Information Granulation III Investigating the HATA-MUKAIDONO Approach / H. Thiele |
Reed-Muller Logic and Its Extensions / Session 5b: |
Experiments on FPRM Expressions for Partially Symmetric Logic Functions / S. Yanushkevich ; J. Butler ; G. Dueck ; V. Shmerko |
Representations of Multiple-Output Switching Functions Using Multiple-Valued Pseudo-Kronecker Decision Diagrams / H. Babu |
A New Algorithm to Compute Quaternary Reed-Muller Expansions |
Evolvable Hardware: From On-Chip Circuit Synthesis to Evolvable Space Systems / A. StoicaSession 6: |
Logic and Algebra / Session 7a: |
De Morgan Bisemilattices / J. Brzozowski |
Finite-Valued Approximations of Product Logic / S. Aguzzoli ; B. Gerla |
Integration of Information in Four-Valued Logics under Non-Uniform Assumptions / Y. Loyer ; N. Spyratos ; D. Stamate |
Decision Diagrams / Session 7b: |
Lower Bound Sifting for MDDs / D. Jankovic ; W. Gunther |
Implementation of Multiple-Output Functions Using PQMDDs / Y. Iguchi ; M. Matsuura |
Fibonacci Decision Diagrams and Spectral Fibonacci Decision Diagrams / M. Stankovic ; J. Astola ; K. Egiazarian |
Circuits I / Session 8a: |
Cost-Analysis of 4-Valued Unary Functions Implemented Using Current-Mode CMOS Circuits / M. Abd-El-Barr ; A. Al-Mutawa |
Implementation of Multiple-Valued Multiplier on GF(3[subscript m]) Using Current Mode CMOS / H. Seong ; J. Choi ; B. Shin |
Novel II-Type Resistor Network in D/A Converter Based on Multiple-Valued Logic / X. Wu ; X. Zhou |
Decision Diagrams and Test / Session 8b: |
Mod-p Decision Diagrams: A Data Structure for Multiple-Valued Functions / H. Sack ; E. Dubrova ; C. Meinel |
Dynamic Re-Encoding During MDD Minimization / F. Schmiedle |
Controllability/Observability Measures for Multiple-Valued Test Generation Based on D-Algorithm / N. Kamiura ; Y. Hata ; N. Matsui |
Evolutionary and Information Theory Approaches / Session 9a: |
Evolutionary Multi-Level Network Synthesis in Given Design Style / T. Luba ; M. Opoka |
An Evolutionary Computing Approach to Multilevel Logic Synthesis Using Various Logic Operations / T. Hozumi ; O. Kakusho ; K. Yamato |
Information Theoretic Approach to Minimization of Polynomial Expressions over GF(4) / D. Popel ; V. Cheushev |
Image and Language Processing / Session 9b: |
On an Architecture of Medical Image Registration System Based on Multiple-Valued Logic / S. Kobashi ; Y. Kitamura ; T. Yanagida |
Gray Scale Image Compression Based on Multiple-Valued Input Binary Functions, Walsh and Reed-Muller Spectra / L.-S. Lim |
A Four-Valued Logic B(4) of E(9) for Modeling Human Communication / D. Rine ; R. Alnakari |
Structures with Many-Valued Information and Their Relational Proof Theory / I. Duntsch ; W. MacCaull ; E. OrlowskaSession 10: |
Circuits II / Session 11a: |
Demonstration of a Novel Multiple-Valued T-Gate Using Multiple-Junction Surface Tunnel Transistors and Its Application to Three-Valued Data Flip-Flop / T. Uemura ; T. Baba |
A Study on the Ternary Parallel Circuit Design with DCG Properties Based on the Matrix Equation / G.-N. Byun ; C.-U. Lee ; S.-Y. Park ; H.-S. Kim |
Novel Resonant-Tunneling Multiple-Threshold Logic Circuit Based on Switching Sequence Detection / T. Waho ; K. Hattori ; K. Honda |
Standard CMOS Implementation of a Multiple-Valued Logic Signed-Digit Adder Based on Negative Differential-Resistance Devices / A. Gonzalez ; M. Bhattacharya ; S. Kulkarni ; P. Mazumder |
Theorem-Proving and Applications / Session 11b: |
The 2-SAT Problem of Regular Signed CNF Formulas / B. Beckert ; R. Hahnle ; F. Manya |
Chaining Techniques for Automated Theorem Proving in Many-Valued Logics / H. Ganzinger ; V. Sofronie-Stokkermans |
High-Radix Parallel VLSI Dividers without Using Quotient Digit Selection Tables / T. Aoki ; K. Nakazawa ; T. Higuchi |
Properties of Independent Components of Self-Motion Optical Flow / M. Jabri ; K.-Y. Park ; S.-Y. Lee ; T. SejnowskiSession 12: |
Panel Discussion / Session 13: |
Multiple-Valued Logic: Provocative Questions / D. Hammerstrom M. Kameyama ; R. Baltar ; Y. Takahashi |
A Multilevel-Cell 32MB Flash Memory / M. Bauer ; R. Alexis ; G. Atwood ; B. Baltar ; A. Fazio ; K. Frary ; M. Hensel ; M. Ishac ; J. Javanifard ; M. Landgraf ; D. Leak ; K. Loe ; D. Mills ; P. Ruby ; R. Rozman ; S. Sweha ; S. Talreja ; K. WojciechowskiSession 14: |
Circuits III / Session 15a: |
Hardware Implementation of "Supplementary Symmetrical Logic Circuit Structure" Concepts / D. Olson ; K. Current |
Design of a Quaternary Latch Circuit Using a Binary CMOS RS Latch |
Low-Power Dual-Rail Multiple-Valued Current-Mode Logic Circuit Using Multiple Input-Signal Levels / T. Hanyu ; T. Ike ; M. Kameyama |
Clones and Asynchronous Machines / Session 15b: |
Rigidity Problem of Autodual Clones / M. Miyakawa ; I. Rosenberg |
On the Intersection of Maximal Partial Clones and the Join of Minimal Partial Clones / L. Haddad ; H. Machida |
Logic Synthesis of Controllers for B-Ternary Asynchronous Systems / Y. Nagata ; D. Miller |
Silicon Single-Electron Devices and Their Applications / A. Fujiwara ; Y. Ono ; K. MuraseSession 16: |
Arithmetics and Systems / Session 17a: |
DRAM-Cell-Based Multiple-Valued Logic-in-Memory VLSI with Charge Addition and Charge Storage / H. Kimura |
An Efficient Data Transmission Technique for VLSI Systems Based on Multiple-Valued Code-Division Multiple Access / Y. Yuminaka ; O. Katoh ; Y. Sasaki |
Arithmetic-Oriented Multiple-Valued Logic-in-Memory VLSI Based on Current-Mode Logic / S. Kaeriyama |
Verification and Power Estimation / Session 17b: |
A Method for Approximate Equivalence Checking |
Propagation Algorithm of Behavior Probability in Power Estimation Based on Multiple-Valued Logic / M. Pedram |
Probabilistic Verification of Multiple-Valued Functions |
Author Index |
Message from the Symposium Chair |
Message from the Co-Chairs |
Reviewers |