| Preface |
| Electronics Division Award Address |
| Radical Reaction Based Semiconductor Manufacturing for Very Advanced ULSI Process Integration / T. Ohmi |
| Keynote Papers |
| From Ambient Intelligence to Silicon Process Technology / C.J. van der Poel |
| From the Lab to the Fab: Transistors to Integrated Circuits / H. R. Huff |
| Diffused Silicon Transistors and Switches (1954-1955): The Beginning of Integrated Circuit Technology / N. Holonyak Jr. |
| Current Status and Future Prospects in Mixed Signal SOC / A. Matsuzawa |
| Process Integration for Memory Devices |
| DRAM Technology for 100nm and Beyond / K.H. Kusters ; J. Alsmeier ; J. Faul ; J. Lutzen ; T. Zell |
| Logic Based Embedded DRAM Technologies / C. Mallardeau |
| Flash Memory Technology Evolution / R. Bez ; E. Camerlenghi |
| FeRAM Technology: Today and Future / I. Kunishima ; N. Nagel |
| Effects of Nitridation Treatment for Electrochemical Properties of MONOS Non-Volatile Memories / H. Aozasa ; I. Fujiwara ; K. Nomoto ; H. Komatsu ; T. Kobayashi |
| The Crystallization Behavior and Interfacial Reaction of Ge[subscript 2]Sb[subscript 2]Te[subscript 5] Thin Films Between Dielectric Material for the Application to the Phase Change Memory / E.J. Jung ; S.K. Kang ; B.G. Min ; D.H. Ko |
| Full Process Integration Aspects |
| Single-Wafer Technology in a 300-mm Wafer Fab / S. Ikeda ; K. Nemoto ; M. Funabashi |
| The Impact of Single Wafer Processing on Process Integration / R. Singh ; M. Fakhruddin ; K.F. Poole |
| Advanced Multilevel Interconnects Technologies for 40-nm Lg Devices / T. Ohba |
| Performance Limitations of Metal Interconnects and Possible Alternatives / K.C. Saraswat ; P. Kapur ; S. Souri |
| Plasma Technologies for Low-k Dry Etching / T. Tatsumi |
| A Novel Approach to Contact Integration at 90-nm and Beyond / A. Singhal ; T. Sparks ; K. Strozewski ; F. Huang ; S. Parihar ; J. Schmidt ; B. Boeck ; J. Fretwell ; G. Yeap ; V. Sheth ; S. Veeraghavan ; B. Melnick |
| SiGe Process Integration |
| BiCMOS Integration of High-Speed SiGe:C HBTs / H. Rucker ; B. Heinemann ; R. Barth ; D. Knoll ; D. Schmidt ; W. Winkler |
| Applications of Silicon Germanium Electrodes in ULSI / E.-X. Ping ; E. Blomiley ; F. Gonzalez |
| Noise Properties and Hetero-Interface Traps in SiGe-Channel PMOSFETs / T. Tsuchiya ; J. Murota |
| Ultra-Shallow Junction Formation by Low Energy Ion Implantation and Flash Lamp Annealing / K. Suguro ; T. Ito ; T. Itani ; T. Iinuma |
| Integration Aspects for Emerging Technologies |
| Single and Few Electron Devices. Integration Trends / J. Gautier |
| Achieving Low Junction Capacitance on Bulk Si MOSFET Using SDOI Process / Z. Wang ; T. Abbott ; J. Trivedi ; C.-C. Cho ; M. Violette |
| Differential Silicide Thickness for ULSI Scaling / W.J. Taylor Jr. ; J. Smith ; J.-Y. Nguyen ; R. Rai ; O. Adetutu ; J. Geren ; J. Ybarra ; D. Petru |
| High-Voltage CMOS and Scaling Trends / H. Ballan |
| Emerging Device Solutions for the Post-Classical CMOS Era / K. De Meyer ; N. Collaert ; S. Kubicek ; A. Kottontharayil ; H. van Meer ; P. Verheyen |
| Modeling End-of-the-Roadmap Transistors / A. Asenov ; A.R. Brown ; J.R. Watling |
| Thin Film Transistors in ULSI--Status and Future / Y. Kuo |
| Extending Planar Single-Gate CMOS & Accelerating the Realization of Double-Gate/Multi-Gate CMOS Devices / J.O. Borland ; H. Iwai ; W. Maszara ; H. Wang |
| Surface Preparation and Gate Module |
| Cleaning for Sub 0.1 [mu]m Technology: A Particular Challenge / D.M. Knotter |
| Si Channel Surface Dependence of Electrical Characteristics in Ultra-Thin Gate Oxide CMOS / H.S. Momose |
| Integration Issues with High k Gate Stacks / C.M. Osburn ; S.K. Han ; I. Kim ; S.A. Campbell ; E. Garfunkel ; T. Gustafson ; J. Hauser ; T.-J. King ; Q. Liu ; P. Ranade ; A. Kingon ; D.-L. Kwong ; S.J. Lee ; C.H. Lee ; J. Lee ; K. Onishi ; C.S. Kang ; R. Choi ; H. Cho|cR. Nich ; G. Lucovsky ; J.G. Hong ; T.P. Ma ; W. Zhu ; Z. Luo ; J.P. Maria ; D. Wicaksana ; V. Misra ; J.J. Lee ; Y.S. Suh ; G. Parksons ; D. Niu ; S. Stemmer |
| Compatibility of Polysilicon with HfO[subscript 2]-based Gate Dielectrics for CMOS Applications / V. Kaushik ; S. De Gendt ; M. Caymax ; E. Young ; E. Rohr ; S. Van Elshocht ; A. Delabie ; M. Claes ; X. Shi ; J. Chen ; R. Carter ; T. Conard ; W. Vandervorst ; M. Schaekers ; M. Heyns |
| Analysis of CMOS Gate-To-Drain Leakage Current and Proposition of a New Cobalt Salicide Selective Etch Chemistry for High DRAM Yield / B. Froment ; C. Regnier ; M.-T. Basso |
| Electrical Characteristics and Thermal Stability of W[subscript 2]N/Ta[subscript 2]O[subscript 5]/Si MOS Capacitors in N[subscript 2]:H[subscript 2] or H[subscript 2] Ambients / P.C. Jiang ; J.S. Chen |
| Sub-Quarter Micron PMOSFET DC and AC NBTI Degradation / E. Li ; S. Prasad ; S. Park ; J. Walker |
| Process Integration in Integrated Circuit Applications |
| Physical Analysis and Modeling of Plasma Etching Mechanism for ULSI Application / M. Kanoh ; S. Onoue ; K. Nishitani ; T. Shinmura ; K. Iyanagi ; S. Kinoshita ; S. Takagi |
| Process Strategy for Built-in Reliability of Cu Damascene Interconnect System for 0.13um-Node and Beyond / H. Yamaguchi ; T. Oshima ; J. Noguchi ; K. Ishikawa ; H. Aoki ; T. Saito ; T. Furusawa ; K. Hinode |
| Impact of Wafer Backside Cu Contamination to 0.18 um Node Devices / S.Q. Gu ; L. Duong ; J. Elmer |
| Integrated Multiscale Process Simulation of Damescene Structures / M.O. Bloomfield ; Y.H. Im ; J. Seok ; C.P. Sukam ; J.A. Tichy ; T.S. Cale |
| An Analysis of the Effect of the Steps for Isolation Formation on STI Process Integration / A. Pavan ; D. Brazzelli ; M. Aiello ; C. Capolupo ; C. Clementi ; C. Cremonesi ; A. Ghetti |
| Defect Generation and Suppression in Device Processes Using a Shallow Trench Isolation Scheme / D. Peschiarolli ; M. Brambilla ; G.P. Carnevale ; A. Cascella ; F. Cazzaniga ; c. Clementi ; A. Gilardini ; M. Martinelli ; A. Maurelli ; I. Mica ; G. Pavia ; F. Piazza ; M.L. Polignano ; V. Soncini ; E. Bonera |
| Electrodeposition of Low-Dimensional Phases on Au Studied by EQCM and XRD / C. Shannon |
| Silicon-on-Insulator |
| 60-nm Gate Length SOI CMOS Technology Optimized for "System-on-a-SOI-Chip" Solution / K. Imai ; S. Maruyama ; T. Suzuki ; T. Kudo ; S. Miyake ; M. Ikeda ; T. Abe ; S. Masuda ; A. Tanabe ; J.-W. Lee ; K. Shibahara ; S. Yokoyama ; H. Ooka |
| Emerging Silicon-On-Nothing (SON) Devices Technology / T. Skotnicki ; S. Monfray ; C. Frenouillet-Beranger |
| High Performance Strained-SOI CMOSFETs / S.-I. Takagi ; T. Mizuno ; T. Tezuka ; N. Sugiyama ; T. Numata ; K. Usuda ; Y. Moriyama ; S. Nakaharai ; J. Koga ; T. Maeda |
| Extremely Scaled Ultra-Thin Body and FinFET CMOS Devices / S. Balasubramanion ; L. Chang ; Y.-K. Choi ; D. Ha ; S. Xiong ; J. Bokor ; C. Hu |
| Fully Depleted SOI Process and Device Technology for Digital and RF Applications / F. Ichikawa ; Y. Nagatomo ; Y. Katakura ; S. Itoh ; H. Matsuhashi ; N. Hirashita ; S. Baba |
| Status and Future Development of PDSOI MOSFETs / S. Krishnan |
| Multi-fin Double Gate MOSFET Fabricated by Using (110)-Oriented SOI Wafers and Orientation dependent Etching / Y.X. Liu ; K. Ishii ; T. Tsutsumi ; M. Masahara ; H. Takashima ; E. Suzuki |
| Optimization of Ultra-Thin Body, Fully-Depleted-SOI Device, with Raised Source/Drain or Raised Extension / J.L. Egley ; A. Vandooren ; B. Winstead ; E. Verret ; B. White ; B.-Y. Nguyen |
| Partially Depleted SOI Dynamic Threshold MOSFET for Low-Voltage and Microwave Applications / M. Dehan ; D. Vanhoenacker-Janvier ; J.-P. Raskin |
| New Characterization Techniques for SOI and Related Devices / S. Okhonin ; M. Nagoga ; P. Fazan |
| Authors Index |
| Subject Index |
| Preface |
| Electronics Division Award Address |
| Radical Reaction Based Semiconductor Manufacturing for Very Advanced ULSI Process Integration / T. Ohmi |
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