| Foreword |
| Committees |
| DFT & BIST |
| TPI for Improving PR Fault Coverage of Boolean and Three-State Circuits / M.J. Geuzebroek ; A.J. van de Goor |
| On the Selection of Efficient Arithmetic Additive Test Pattern Generators / S. Manich ; L. Garcia ; L. Balado ; E. Lupon ; J. Rius ; R. Rodriguez ; J. Figueras |
| Parity-Based Output Compaction for Core-Based SOCs / O. Sinanoglu ; A. Orailoglu |
| Memory Test |
| Defect-Oriented Dynamic Fault Models for Embedded-SRAMs / S. Borri ; M. Hage-Hassan ; P. Girard ; S. Pravossoudovitch ; A. Virazel |
| Importance of Dynamic Faults for New SRAM Technologies / S. Hamdioui ; R. Wadsworth ; J.D. Reyes |
| Yield Analysis for Repairable Embedded Memories / A. Sehgal ; A. Dubey ; E.J. Marinissen ; C. Wouters ; H. Vranken ; K. Chakrabarty |
| Asynchronous Test |
| Scan Test Strategy for Asynchronous-Synchronous Interfaces / O. Petre ; H.G. Kerkhoff |
| SoC Testing |
| An Efficient Approach to SoC Wrapper Design, TAM Configuration and Test Scheduling / J. Pouget ; E. Larsson ; Z. Peng ; M.-L. Flottes ; B. Rouzeyre |
| Control-Aware Test Architecture Design for Modular SOC Testing / S.K. Goel |
| Issues in Test Application |
| A Practical Evaluation of I[subscript DDQ] Test Strategies for Deep Submicron Production Test Application: Experiences and Targets from the Field / A. Fudoli ; A. Ascagni ; D. Appello ; H. Manhaeve |
| Automating the Device Interface Board Modeling for Virtual Test / M. Rona ; G. Krampl ; F. Raczkowski |
| Defect-Oriented Test |
| Signal Integrity Loss in Bus Lines Due to Open Shielding Defects / V. Avendano ; V. Champac |
| Process-Variability Aware Delay Fault Testing of [Delta]V[subscript T] and Weak-Open Defects / D. Arumi-Delgado ; R. Rodriguez-Montanes ; J. Pineda de Gyvez ; G. Gronthoud |
| Modeling Feedback Bridging Faults with Non-Zero Resistance / I. Polian ; P. Engelke ; M. Renovell ; B. Becker |
| ATPG |
| Automating Test Program Generation in STIL - Expectations and Experiences Using IEEE 1450 / H. Lang ; B. Pande ; H. Ahrens |
| Automatic Worst Case Pattern Generation Using Neural Networks & Genetic Algorithm for Estimation of Switching Noise on Power Supply Lines in CMOS Circuits / E. Liau ; D. Schmitt-Landsiedel |
| Functional Validation |
| Code Generation for Functional Validation of Pipelined Microprocessors / F. Corno ; G. Squillero ; M. Sonza Reorda |
| Scan and Core Testing |
| Enhanced P1500 Compliant Wrapper Suitable for Delay Fault Testing of Embedded Cores / H.J. Vermaak |
| RF, EME, and Probing |
| RF ATE Equipment Benefit from Advanced Network Analyzer Technology / M. Seth |
| Characterization of the EME of Integrated Circuits with the Help of the IEC Standard 61967 / T. Ostermann ; B. Deutschmann |
| Delay Testing |
| On Path Selection for Delay Fault Testing Considering Operating Conditions / B. Seshadri ; I. Pomeranz ; S. Reddy ; S. Kundu |
| Requirements for Delay Testing of Look-Up Tables in SRAM-Based FPGAs / O. Heron |
| Exploiting 1149.1 for Debug and Core Test |
| Debug Architecture for System on Chip Taking Full Advantage of the Test Access Port / E. Moerman ; S. Bocq ; J. Verfaillie |
| Author Index |
| Foreword |
| Committees |
| DFT & BIST |
| TPI for Improving PR Fault Coverage of Boolean and Three-State Circuits / M.J. Geuzebroek ; A.J. van de Goor |
| On the Selection of Efficient Arithmetic Additive Test Pattern Generators / S. Manich ; L. Garcia ; L. Balado ; E. Lupon ; J. Rius ; R. Rodriguez ; J. Figueras |
| Parity-Based Output Compaction for Core-Based SOCs / O. Sinanoglu ; A. Orailoglu |
