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1.

コンピュータファイル

コンピュータファイル
sponsored by IEEE Computer Society TCCA, ACM SIGARCH ; with support from The Georgia Institute of Technology
出版情報: Los Alamitos, CA : IEEE Computer Society, c1999  1 CD-ROM ; 12 cm
シリーズ名: Computer architecture news ; vol. 27, no. 2 May 1999 special issue
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2.

図書

図書
sponsored by IEEE Computer Society Technical Committee on Computer Architecture, IEEE Computer Society Technical Commitee on Parallel Processing ... [et al.]
出版情報: Los Alamitos, Calif. : IEEE Computer Society, c2002  xviii, 305 p. ; 28 cm
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Message from the General Chairs
Message from the Program Chairs
Organizing Committee
Steering Committee
Program Committee
Reviewers
Keynote Address
Parallelism in Mainstream Enterprise Platforms of the Future / D. Bhandarkar
Data Parallelism and Threading / Session 1:
An Evaluation of Data-Parallel Compiler Support for Line-Sweep Applications / D. Chavarria-Miranda ; J. Mellor-Crummey
Increasing and Detecting Memory Address Congruence / S. Larsen ; E. Witchel ; S. Amarasinghe
Transparent Threads: Resource Sharing in SMT Processors for High Single-Thread Performance / G. K. Dorai ; D. Yeung
Compiler Support for Architecture / Session 2:
Compiler-Controlled Caching in Superword Register Files for Multimedia Extension Architectures / J. Shin ; J. Chame ; M. W. Hall
Effective Compilation Support for Variable Instruction Set Architecture / J. Liu ; T. Kong ; F. Chow
A Framework for Parallelizing Load/Stores on Embedded Processors / X. Zhuang ; S. Pande ; J. S. Greenland Jr.
Program Characterization / Session 3:
Workload Design: Selecting Representative Program-Input Pairs / L. Eeckhout ; H. Vandierendonck ; K. De Bosschere
Dataflow Frequency Analysis Based on Whole Program Paths / B. Scholz ; E. Mehofer
Quantifying Instruction Criticality / E. S. Tune ; D. M. Tullsen ; B. Calder
The Role of Computational Science in Energy Efficiency and Renewable Energy / S. Hammond
Power / Session 4:
Application Transformations for Energy and Performance-Aware Device Management / T. Heath ; E. Pinheiro ; J. Hom ; U. Kremer ; R. Bianchini
Leakage Energy Management in Cache Hierarchies / L. Li ; I. Kadayif ; Y-F. Tsai ; N. Vijaykrishnan ; M. Kandemir ; M. J. Irwin ; A. Sivasubramaniam
Integrating Adaptive On-Chip Storage Structures for Reduced Dynamic Power / S. Dropsho ; A. Buyuktosunoglu ; R. Balasubramonian ; D. H. Albonesi ; S. Dwarkadas ; G. Semeraro ; G. Magklis ; M. L. Scott
Prediction / Session 5:
The Use of Prediction for Accelerating Upgrade Misses in cc-NUMA Multiprocessors / M. E. Acacio ; J. Gonzalez ; J. M. Garcia ; J. Duato
Predicting Conditional Branches with Fusion-Based Hybrid Predictors / G. H. Loh ; D. S. Henry
Memory Performance / Session 6:
Speculative Sequential Consistency with Little Custom Storage / C. Gniady ; B. Falsafi
Cost-Effective Compiler Directed Memory Prefetching and Bypassing / D. Ortega ; E. Ayguade ; J.-L. Baer ; M. Valero
Using the Compiler to Improve Cache Replacement Decisions / Z. Wang ; K. S. McKinley ; A. L. Rosenberg ; C. C. Weems
Memory Aliasing / Session 7:
Software Bubbles: Using Predication to Compensate for Aliasing in Software Pipelines / B. Goldberg ; E. Crutcher ; C. Huneycutt ; K. Palem
Speculative Alias Analysis for Executable Code / M. Fernandez ; R. Espasa
Cost Effective Memory Dependence Prediction Using Speculation Levels and Color Sets / S. Onder
The Computational Grid: Aggregating Performance and Enhanced Capability from Federated Resources / R. Wolski
Java and IA-64 / Session 8:
Just-in-Time Java Compilation for the Itanium Processor / T. Shpeisman ; G.-Y. Lueh ; A.-R. Adl-Tabatabai
Eliminating Exception Constraints of Java Programs for IA-64 / K. Ishizaki ; T. Inagaki ; H. Komatsu ; T. Nakatani
Clustered Microarchitectures / Session 9:
Optimizing Loop Performance for Clustered VLIW Architectures / Y. Qian ; S. Carr ; P. Sweany
Exploiting Pseudo-Schedules to Guide Data Dependence Graph Partitioning / A. Aleta ; J. M. Codina ; J. Sanchez ; A. Gonzalez ; D. Kaeli
Efficient Interconnects for Clustered Microarchitectures / J.-M. Parcerisa ; J. Sahuquillo
Sigarch Conference Guidelines
Author Index
Message from the General Chairs
Message from the Program Chairs
Organizing Committee
3.

図書

図書
editors, Jeffrey Arnold, Kenneth L. Pocek ; sponsored by IEEE Computer Society Technical Committee on Computer Architecture
出版情報: Los Alamitos, Calif. : IEEE Computer Society, c2002  x, 322 p. ; 28 cm
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Conference Organizers
Applications I / Session 1:
Image Registration of Real-Time Video Data Using the SONIC Reconfigurable Computer Platform / W. J. C. Melis ; P. Y. K. Cheung ; W. Luk
A Massively Parallel RC4 Key Search Engine / K. H. Tsoi ; K. H. Lee ; P. H. W. Leong
An FPGA Implementation of Triangle Mesh Decompression / T. Mitra ; T. Chiueh
Networking I / Session 2:
Single-Chip Gigabit Mixed-Version IP Router on Virtex-II Pro / G. Brebner
Control and Configuration Software for a Reconfigurable Networking Hardware Platform / T. S. Sproull ; J. W. Lockwood ; D. E. Taylor
Tool I / Session 3:
Peer-to-Peer Hardware-Software Interfaces for Reconfigurable Fabrics / M. Budiu ; M. Mishra ; A. R. Bharambe ; S. C. Goldstein
Pam-Blox II: Design and Evaluation of C++ Module Generation for Computing with FPGAs / O. Mencer
Coarse-Grain Pipelining on Multiple FPGA Architectures / H. Ziegler ; B. So ; M. Hall ; P. C. Diniz
Template Matching / Session 4:
FPGA-Based Template Matching Using Distance Transforms / S. Hezel ; A. Kugel ; R. Manner ; D. M. Gavrila
Reconfigurable Shape-Adaptive Template Matching Architectures / J. Gause
Networking II / Session 5:
Assisting Network Intrusion Detection with Reconfigurable Hardware / B. L. Hutchings ; R. Franklin ; D. Carver
GRIP: A Reconfigurable Architecture for Host-Based Gigabit-Rate Packet Processing / P. Bellows ; J. Flidr ; T. Lehman ; B. Schott ; K. D. Underwood
Design and Analysis of a Layer Seven Network Processor Accelerator Using Reconfigurable Logic / G. Memik ; S. O. Memik ; W. H. Mangione-Smith
Architecture I / Session 6:
Using On-Chip Configurable Logic to Reduce Embedded System Software Energy / G. Stitt ; B. Grattan ; J. Villarreal ; F. Vahid
Queue Machines: Hardware Compilation in Hardware / H. Schmit ; B. Levine ; B. Ylvisaker
Applications II / Session 7:
Custom Computing Machines for the Set Covering Problem / C. Plessl ; M. Platzner
Analysis and Implementation of the Discrete Element Method Using a Dedicated Highly Parallel Architecture in Reconfigurable Computing / B. Carrion Schafer ; S. F. Quigley ; A. H. C. Chan
Using Floating-Point Arithmetic on FPGAs to Accelerate Scientific N-Body Simulations / G. Lienhart
Architecture II / Session 8:
Mobile Memory: Improving Memory Locality in Very Large Reconfigurable Fabrics / R. Yan
Hardware-Assisted Fast Routing / A. DeHon ; R. Huang ; J. Wawrzynek
Tools II / Session 9:
Optimum Wordlength Allocation / G. A. Constantinides
Precis: A Design-Time Precision Analysis Tool / M. L. Chang ; S. Hauck
Fast Area Estimation to Support Compiler Optimizations in FPGA-Based Reconfigurable Systems / D. Kulkarni ; W. A. Najjar ; R. Rinker ; F. J. Kurdahi
Image Compression / Session 10:
Hyperspectral Image Compression on Reconfigurable Platforms / T. W. Fry
MPEG-Compliant Entropy Decoding on FPGA-Augmented TriMedia/CPU64 / M. Sima ; S. Cotofana ; S. Vassiliadis ; J. T. J. van Eijndhoven ; K. Vissers
On Sparse Matrix-Vector Multiplication with FPGA-Based System / H. ElGindy ; Y.-L. ShuePoster Session 1:
Implementing a Simple Continuous Speech Recognition System on an FPGA / S. J. Melnikoff ; M. J. Russell
RACER--A Rapid Prototyping Accelerator for Pulsed Neural Networks / C. Grassmann ; J. K. Anlauf
Accelerating Radiosity Calculations Using Reconfigurable Platforms / H. Styles
On Implementing a Configware/Software SAT Solver / N. A. Reis ; J. T. de Sousa
Reconfigurable Object Detection in FLIR Image Sequences / J. E. Scalera ; C. F. Jones III ; M. Soni ; M. B. Bucciero ; P. M. Athanas ; A. L. Abbott ; A. Mishra
TCP-Stream Reassembly and State Tracking in Hardware / M. Necker ; D. Contis ; D. Schimmel
Fast and Guaranteed C Compilation onto the PACT-XPP Reconfigurable Computing Platform / J. M. P. Cardoso ; M. WeinhardtPoster Session 2:
Module Generators Driving the Compilation for Adaptive Computing Systems / A. Koch ; N. Kasprzyk
System-Level Modelling and Implementation Technique for Run-Time Reconfigurable Systems / T. Rissa ; M. Vasilko ; J. Niittylahti
Tabu Search with Intensification Strategy for Functional Partitioning in Hardware-Software Codesign / T. Wiangtong
Automatic Latency-Optimal Design of FPGA-Based Systolic Arrays / J. G. Nash
Compiling ATR Probing Codes for Execution on FPGA Hardware / W. Bohm ; R. Beveridge ; B. Draper ; C. Ross ; M. Chawathe ; W. Najjar
The Effects of Datapath Placement and C-Slow Retiming on Three Computational Benchmarks / N. Weaver
A Scalable FPGA-Based Custom Computing Machine for a Medical Image Processing / T. Yokota ; M. Nagafuchi ; Y. Mekada ; T. Yoshinaga ; K. Ootsu ; T. BabaPoster Session 3:
The Design of the Amalgam Reconfigurable Cluster / J. D. Walstrom ; J. J. Cook ; D. B. Gottlieb ; S. Ferrera ; C.-W. Wang ; N. P. Carter
Mapping Algorithms to the Amalgam Programmable-Reconfigurable Processor
Customising Floating-Point Designs / A. A. Gaffar ; N. ShiraziPoster Session 4:
Mapping Multi-Mode Circuits to LUT-Based FPGA Using Embedded MUXes / T. Courtney ; R. Turner ; R. Woods
Author Index
Conference Organizers
Applications I / Session 1:
Image Registration of Real-Time Video Data Using the SONIC Reconfigurable Computer Platform / W. J. C. Melis ; P. Y. K. Cheung ; W. Luk
4.

図書

図書
sponsored by IEEE TCCA, ACM SIGARCH
出版情報: Los Alamitos, Calif. : IEEE Computer Society, c2002  xv, 331 p. ; 28 cm
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目次情報: 続きを見る
Message from the General Chair
Message from the Program Chair
Organizing Committee
Steering Committee
Program Committee
Reviewers
Welcoming Remarks
Keynote Address / Burton J. Smith
Processor Pipelines / Session 1:
The Optimum Pipeline Depth for a Microprocessor / A. Hartstein ; T. Puzak
The Optimal Logic Depth per Pipeline Stage Is 6 to 8 FO4 Inverter Delays / M. Hrishikesh ; N. Jouppi ; K. Farkas ; D. Burger ; S. Keckler ; P. Shivakumar
Increasing Processor Performance by Implementing Deeper Pipelines / E. Sprangle ; D. Carmean
Processor Scheduling / Session 2:
Efficient Dynamic Scheduling through Tag Elimination / D. Ernst ; T. Austin
Slack: Maximizing Performance under Technological Constraints / B. Fields ; R. Bodik ; M. Hill
A Large, Fast Instruction Window for Tolerating Cache Misses / A. Lebeck ; J. Koppanalil ; T. Li ; J. Patwardhan ; E. Rotenberg
An Instruction Set and Microarchitecture for Instruction Level Distributed Processing / H.-S. Kim ; J. Smith
Safety and Reliability / Robert P. ColwellSession 3:
Transient-Fault Recovery Using Simultaneous Multithreading / T. Vijaykumar ; I. Pomeranz ; K. Cheng
Detailed Design and Evaluation of Redundant Multithreading Alternatives / S. Mukherjee ; M. Kontz ; S. Reinhardt
ReVive: Cost-Effective Architectural Support for Rollback Recovery in Shared-Memory Multiprocessors / M. Prvulovic ; Z. Zhang ; J. Torrellas
SafetyNet: Improving the Availability of Shared Memory Multiprocessors with Global Checkpoint/Recovery / D. Sorin ; M. Martin ; D. Wood
Power Aware Architecture / Session 4:
Dynamic Fine-Grain Leakage Reduction Using Leakage-Biased Bitlines / S. Heo ; K. Barr ; M. Hampton ; K. Asanovic
Drowsy Caches: Simple Techniques for Reducing Leakage Power / K. Flautner ; N. Kim ; S. Martin ; D. Blaauw ; T. Mudge
Power and Performance Evaluation of Globally Asynchronous Locally Synchronous Processors / A. Iyer ; D. Marculescu
Memory Systems / Session 5:
Using a User-Level Memory Thread for Correlation Prefetching / Y. Solihin ; J. Lee
Avoiding Initialization Misses to the Heap / J. Lewis ; B. Black ; M. Lipasti
Going the Distance for TLB Prefetching: An Application-Driven Study / G. Kandiraju ; A. Sivasubramaniam
Dynamic Optimization / Session 6:
Timekeeping in the Memory System: Predicting and Optimizing Memory Behavior / Z. Hu ; S. Kaxiras ; M. Martonosi
Implementing Optimizations at Decode Time / I. Kim
Managing Multi-configuration Hardware via Dynamic Working Set Analysis / A. Dhodapkar
Data and Storage Networks / Session 7:
Queue Pair IP: A Hybrid Architecture for System Area Networks / P. Buonadonna ; D. Culler
Experiences with VI Communication for Database Storage / Y. Zhou ; A. Bilas ; S. Jagannathan ; C. Dubnicki ; J. Philbin ; K. Li
Vector Architectures / Session 8:
Speculative Dynamic Vectorization / A. Pajuelo ; A. Gonzalez ; M. Valero
Tarantula: A Vector Extension to the Alpha Architecture / R. Espasa ; F. Ardanaz ; J. Emer ; S. Felix ; J. Gago ; R. Gramunt ; I. Hernandez ; T. Juan ; G. Lowney ; M. Mattina ; A. Seznec
Supporting Deep Speculation / Session 9:
Design Tradeoffs for the Alpha EV8 Conditional Branch Predictor / V. Krishnan ; Y. Sazeides
Difficult-Path Branch Prediction Using Subordinate Microthreads / R. Chappell ; F. Tseng ; A. Yoaz ; Y. Patt
A Scalable Instruction Queue Design Using Dependence Chains / S. Raasch ; N. Binkert
Author Index
Message from the General Chair
Message from the Program Chair
Organizing Committee
5.

図書

図書
sponsored by IEEE Computer Society Technical Committee on Computer Architecture, Association for Computing Machinery SIGARCH
出版情報: Los Alamitos, Calif. : IEEE Computer Society, c2001  xi, 291 p. ; 28 cm
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General Chair's Message
Program Chair's Message
Conference Organization
Reviewers
Plenary Session
Opening Remarks
Keynote Speech: Greg Papadopoulos, CTO, Sun Microsystems Inc., USA
Multithreading and Speculation / Session 1:
Execution-based Prediction Using Speculative Slices / C. Zilles ; G. Sohi
Speculative Precomputation: Long-range Prefetching of Delinquent Loads / J. Collins ; H. Wang ; D. Tullsen ; C. Hughes ; Y. Lee ; D. Lavery ; J. Shen
Dynamically Allocating Processor Resources between Nearby and Distant ILP / R. Balasubramonian ; S. Dwarkadas ; D. Albonesi
Memory System Issues / Session 2:
Tolerating Memory Latency through Software-Controlled Pre-Execution in Simultaneous Multithreading Processors / C. Luk
Data Prefetching by Dependence Graph Precomputation / M. Annavaram ; J. Patel ; E. Davidson
Concurrency, Latency, or System Overhead: Which Has the Largest Impact on Uniprocessor DRAM-System Performance? / V. Cuppu ; B. Jacob
Processor Architecture / Session 3:
Focusing Processor Policies via Critical-Path Prediction / B. Fields ; S. Rubin ; R. Bodik
Automated Design of Finite State Machine Predictors for Customized Processors / T. Sherwood ; B. Calder
Better Exploration of Region-Level Value Locality with Integrated Computation Reuse and Value Prediction / Y. Wu ; D. Chen ; J. Fang
Communication Support / Session 4:
CryptoManiac: A Fast Flexible Architecture for Secure Communication / L. Wu ; C. Weaver ; T. Austin
QoS Provisioning in Clusters: An Investigation of Router and NIC Design / K. Yum ; E. Kim ; C. Das
Cache Management / Session 5:
Locality vs. Criticality / S. Srinivasan ; R. Ju ; A. Lebeck ; C. Wilkerson
Dead-Block Prediction and Dead-Block Correlating Prefetchers / A. Lai ; C. Fide ; B. Falsafi
Code Layout Optimizations for Transaction Processing Workloads / A. Ramirez ; L. Barroso ; K. Gharachorloo ; R. Cohn ; J. Larriba-Pey ; P. Lowney ; M. Valero
Architectural Impact of Emerging Technologies / Session 6A:
Exploring and Exploiting Wire-Level Pipelining in Emeging Technologies / M. Niemier ; P. Kogge
NanoFabrics: Spatial Computing Using Molecular Electronics / S. Goldstein ; M. Budiu
Shared-Memory Multiprocessors / Session 6B:
A Simple Method for Extracting Models from Protocol Code / D. Lie ; A. Chou ; D. Engler ; D. Dill
Removing Architectural Bottlenecks to the Scalability of Speculative Parallelization / M. Prvulovic ; M. Garzaran ; L. Rauchwerger ; J. Torrellas
Energy-Effective Designs / Session 7:
Power and Energy Reduction Via Pipeline Balancing / R. Bahar ; S. Manne
Energy-Effective Issue Logic / D. Folegnani ; A. Gonzalez
Cache Decay: Exploiting Generational Behavior to Reduce Cache Leakage Power / S. Kaxiras ; Z. Hu ; M. Martonosi
Performance Tools and Evaluations / Session 8:
Variability in the Execution of Multimedia Applications and Implications for Architecture / P. Kaul ; S. Adve ; R. Jain ; C. Park ; J. Srinivasan
Measuring Experimental Error in Microprocessor Simulation / R. Desikan ; D. Burger ; S. Keckler
Rapid Profiling via Stratified Sampling / S. Sastry ; J. Smith
Author Index
General Chair's Message
Program Chair's Message
Conference Organization
6.

図書

図書
sponsored by IEEE Computer Society Technical Committee on Simulation, IEEE Computer Society Technical Committee on Computer Architecture ; in cooperation with ACM SIGSIM, ACM SIGARCH
出版情報: Los Alamitos, Calif. : IEEE Computer Society, c2001  xii, 432 p. ; 28 cm
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Message from the General Chair
Message from the Program Chair
Conference Organizers
Program Committee
Opening Remarks / Dr. Anthony Perzigian
Keynote Speech
High-Volume Web Servers: Traffic Patterns, Performance Implications and Resource Management / Dr. Mark S. Squillante
Real Time Systems
Specification and Validation of a Real-Time Parallel Kernel Using LOTOS / C. de Farias ; L. Pires ; W. de Souza ; C. Moron
Performance Analysis of Pools in Soft Real-Time Design Architectures / C. Juiz ; R. Puigjaner ; H. Perros
Dynamic Multipath Routing (DMPR): An Approach to Improve Resource Utilization in Networks for Real-Time Traffic / S. De ; S. Das
Parallel and Distributed Simulation
An Evaluation of Grouping Techniques for State Dissemination in Networked Multi-User Games / L. Zou ; M. Ammar ; C. Diot
Effect of Event Orderings on Memory Requirement in Parallel Simulation / Y. Teo ; B. Onggo ; S. Tay
Time-Parallel Algorithms for Simulation of Multiple Access Protocols / K. Jones
Capacity Planning
Optimal Resource Assignment in Internet Data Centers / X. Zhu ; S. Singhal
Traffic Engineering Label Switched Paths in IP Networks using a Pre-Planned Flow Optimization Model / A. Bagula ; A. Krzesinski
Wireless
QoS for Adaptive Multimedia in Wireless/Mobile Networks / Y. Xiao ; C. Chen
MoSync: A Synchronization Scheme for Cellular Wireless and Mobile Multimedia Systems / A. Boukerche ; S. Hong ; T. Jacob
Routing
Performance Study of a Multipath Routing Method for Wireless Mobile Ad Hoc Networks / K. Wu ; J. Harms
Minimizing Routing State for Light-Weight Network Simulation / P. Huang ; J. Heidemann
Non-Blocking, Localized Routing Algorithm for Balanced Energy Consumption in Mobile Ad Hoc Networks / K. Woo ; C. Yu ; D. Lee ; H. Youn ; B. Lee
Stability Analysis on Active Queue Management Algorithms in Routers / W. Wu ; Y. Ren ; X. Shan
Network Simulation/Emulation
ANML: A Language for Describing Networks / C. Kiddle ; R. Simmonds ; D. Wilson ; B. Unger
Mulit-Resolution Network Simulations Using Dynamic Component Substitution / D. Rao ; P. Wilsey
Packet Reading for Network Emulation / R. Bradford
Split Protocol Stack Network Simulations Using the Dynamic Simulation Backplane / D. Xu ; G. Riley ; R. Fujimoto
Design--Why We Don't Do It Right / Dr. John Hines
Modeling
Low-Cost Performance Prediction of Data-Dependent Data Parallel Programs / H. Gautama ; A. van Gemund
A Modular, Analytical Throughput Model for Modern Disk Arrays / M. Uysal ; G. Alvarez ; A. Merchant
Performing File Prediction with a Program-Based Successor Model / T. Yeh ; D. Long ; S. Brandt
Network Traffic
Improving Ensemble-TCP Performance on Asymmetric Networks / Q. Wu ; C. Williamson
How Does TCP Generate Pseudo-Self-Similarity? / L. Guo ; M. Crovella ; I. Matta
Generalized Processor Sharing with Long-Range Dependent Traffic Input / X. Yu ; L-J. Thng ; Y. Jiang
Benchmarking
Plain End-to-End Measurement for Local Area Network Voice Transmission Feasibility / W. Kampichler ; K. Goeschka
Tuning of the Checkpointing and Communication Library for Optimistic Simulation on Myrinet Based NOWs / F. Quaglia ; A. Santoro ; B. Ciciani
Performance of Finite Field Arithmetic in an Elliptic Curve Cryptosystem / J. Higgins ; Z. Li ; M. Clement
Switching
AQueueing Model for Pipelined Circuit-Switched Networks with the MMPP Traffic / G. Min ; M. Ould-Khaoua
Service Guarantees in Deflection Networks / W. Olesinski ; P. Gburzynski
Analysis of Timeout-Based Adaptive Wormhole Routing / H. Sarbazi-Azad ; A. Khonsari
File Systems
PROFS--Performance-Oriented Data Reorganization for Log-Structured File System on Multi-Zone Disks / J. Wang ; Y. Hu
Aggregating Caches: A Mechanism for Implicit File Prefetching / A. Amer
A Bit-Parallel Search Algorithm for Allocating Free Space / R. Burns ; W. Hineman
Large-Scale Simulation of Replica Placement Algorithms for a Serverless Distributed File System / J. Douceur ; R. Wattenhofer
Tools
Parameterized Mobile Action Generator for a Wireless PCS Network / S-E. Park ; C. Purdy
On-Line Test System Applied in Routing Protocol Test / Y. Zhao ; X. Yin ; B. Han ; J. Wu
PTPlan MPLS: A Tool for MPLS Network Dimensioning / L. Cardoso ; J. Patrao ; C. Lopes ; A. de Sousa ; R. Valadas
BRITE: An Approach to Universal Topology Generation / A. Medina ; A. Lakhina ; J. Byers
On-Line Simulation Techniques for Real-Time Management of Systems / Dr. Richard Fujimoto
WWW
The Structural Cause of File Size Distributions / A. Downey
A Simulation Analysis of Dynamic Server Selection Algorithms for Replicated Web Services / M. Bernardo
Simulation Evaluation of a Heterogeneous Web Proxy Caching Hierarchy / M. Busari
HTTP Simulator Validation Using Real Measurements: A Case Study / B. Davison
Broadband
Performance Evaluation Based on an Aggregate ATM Model / S. Galmes
Modeling and Analysis of an ABR Flow Control Algorithm for a Virtual Source/Virtual Destination Switch / C. Cseh
On Class-Based Isolation of UDP, Short-Lived and Long-Lived TCP Flows / S. Yilmaz
A Stream Tapping Protocol with Partial Preloading / J-F. Paris
Author Index
Message from the General Chair
Message from the Program Chair
Conference Organizers
7.

図書

図書
Sponsored by IEEE Computer Society Technical Committee on Computer Architecture, IEEE Computer Society Technical Commitee on Parallel Processing, ACM SIGARCH, IFIP Working Group 10.3 ; with the support of Technical University of Catalunya (UPC) ... [et al.]
出版情報: Los Alamitos, Calif. : IEEE Computer Society, c2001  x, 305 p. ; 28 cm
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General Chair's Message
Conference Organizers
Program Committee
Keynote Address / Randall D. Isaac
Simulation and Modeling / Session 1:
Basic Block Distribution Analysis to Find Periodic Behavior and Simulation Points in Applications / T. Sherwood ; E. Perelman ; B. Calder
Modeling Superscalar Processors via Statistical Simulation / S. Nussbaum ; J. Smith
Hybrid Analytical-Statistical Modeling for Efficiently Exploring Architecture and Workload Design Spaces / L. Eeckhout ; K. De Bosschere
Efficient Caches / Session 2:
Filtering Techniques to Improve Trace-Cache Efficiency / R. Rosner ; A. Mendelson ; R. Ronen
Reactive-Associative Caches / B. Batson ; T. Vijaykumar
Adaptive Mode Control: A Static-Power-Efficient Cache Design / H. Zhou ; M. Toburen ; E. Rotenberg ; T. Conte
Specialized Instruction Sets / Session 3:
Implementation and Evaluation of the Complex Streamed Instruction Set / B. Juurlink ; D. Tcheressiz ; S. Vassiliadis ; H. Wijshoff
On the Efficiency of Reductions in [mu]-SIMD Media Extensions / J. Corbal ; R. Espasa ; M. Valero
Prediction and Recovery / Justin RattnerSession 4:
Boolean Formula-Based Branch Prediction for Future Technologies / D. Jimenez ; H. Hanson ; C. Lin
Using Dataflow Based Context for Accurate Value Prediction / R. Thomas ; M. Franklin
Recovery Mechanism for Latency Misprediction / E. Morancho ; J. Maria Llaberia ; A. Olive
Memory Optimization / Session 5:
A Cost Framework for Evaluating Integrated Restructuring Optimizations / B. Chandramouli ; J. Carter ; W. Hsieh ; S. McKee
Compiling for the Impulse Memory Controller / X. Huang ; Z. Wang ; K. McKinley
On the Stability of Temporal Data Reference Profiles / T. Chilimbi
Program Optimization / Session 6:
Code Reordering and Speculation Support for Dynamic Optimization Systems / E. Nystrom ; R. Barnes ; M. Merten ; W-M. Hwu
A Unified Modulo Scheduling and Register Allocation Technique for Clustered Processors / J. Codina ; J. Sanchez ; A. Gonzalez
Cache-Friendly Implementations of Transitive Closure / M. Penner ; V. Prasanna
Technology Implications / Session 7:
Exploring the Design Space of Future CMPs / J. Huh ; D. Burger ; S. Keckler
Area and System Clock Effects on SMT/CMP Processors / J. Burns ; J-L. Gaudiot
Parallel Machines / Joel EmerSession 8:
Limits on Speculative Module-Level Parallelism in Imperative and Object-Oriented Programs on CMP Platforms / F. Warg ; P. Stenstrom
Compiler and Runtime Analysis for Efficient Communication in Data Intensive Applications / R. Ferreira ; G. Agrawal ; J. Saltz
Architectural Support for Parallel Reductions in Scalable Shared-Memory Multiprocessors / M. Garzaran ; M. Prvulovic ; Y. Zhang ; A. Jula ; H. Yu ; L. Rauchwerger ; J. Torrellas
Data Prefetching / Session 9:
Optimizing Software Data Prefetches with Rotating Registers / G. Doshi ; R. Krishnaiyer ; K. Muthukumar
Multi-Chain Prefetching: Effective Exploitation of Inter-Chain Memory Parallelism for Pointer-Chasing Codes / N. Kohout ; S. Choi ; D. Kim ; D. Yeung
Data Flow Analysis for Software Prefetching Linked Data Structures in Java / B. Cahoon
Comparing and Combining Read Miss Clustering and Software Prefetching / V. Pai ; S. Adve
Author Index
General Chair's Message
Conference Organizers
Program Committee
8.

図書

図書
sponsored by IEEE Computer Society Technical Committee on Computer Architecture, ACM SIGARCH
出版情報: Los Alamitos, Calif. : IEEE Computer Society, c2005  xviii, 557 p. ; 27 cm.
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9.

図書

図書
sponsored by IEEE Computer Society Technical Committee on Computer Architecture ... [et al.]
出版情報: Los Alamitos, Calif. ; Tokyo : IEEE Computer Society, c2005  xv, 363 p. ; 28 cm.
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10.

図書

図書
sponsored by IEEE Computer Society Technical Committee on Computer Architecture ; [edited by Jeffrey Arnold and Kenneth L. Pocek]
出版情報: Los Alamitos, Calif. ; Tokyo : IEEE Computer Society, c2005  xi, 338 p. ; 28 cm
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